JPS61263345A - Multiplex transmission equipment - Google Patents

Abstract

PURPOSE:To improve transmission efficiency by providing a transmission/ receiving means with providing in parallel the transmission line of a time series code and a data transmission line, detecting an address addressed to its own from the time series code and opening a transmitting/receiving gate according to the length of transmission data. CONSTITUTION:To a bit transmission line 3 and a data transmission line 5 connected with an address lock generator 1, a transmitter 7 and a receiver 9 are connected. When a bit pattern from the address lock is coincided 15 with its own address 13, the receiver 7 sets an FF17 and opens a gate 19 and with P/S converting data from a data input part 25, outputs them to a transmission line synchronizing with a clock signal RC. The receiver 9 also detects 11 the bit pattern from a transmission line 3 and when it is coincided 15 with its own address 13, the FF17 is set and the gate 19 is opened and the data from the transmission line 5 are S/P converted 29 and are stored 31 and are outputted 33 synchronizing with the clock signal. Counter circuits 23 and 35 are extended or compressed according to a bit length. Thereby, the transmission efficiency is improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a multiplex transmission device used in vehicles and the like.

[Description of Prior Art] As an example of a conventional multiplex transmission device, for example,
There is one as shown in Japanese Patent No.-13367.

This multiplex transmission device transmits three signals based on a clock signal of a predetermined period.
A code string signal generation means for generating a code string signal of repeating seven types of signals of the next M sequence code, that is, 1100101; a code string signal transmission path for transmitting the code string signal; By monitoring, if the pattern of predetermined bits of the code string signal that appears sequentially for each periodic signal matches the self-assigned address, for example 101, the bit pattern of the code string signal that appears sequentially for each periodic signal matches the self-assigned address, for example, 101, the bit pattern is changed to 1 at a predetermined timing according to the signal period of the synchronization signal.
It is configured to include a transmitting/receiving means capable of transmitting/receiving bit data, and a data transmission path for transmitting these data.

Therefore, by assigning a predetermined bit, for example, a 3-bit address to the transmitting/receiving means of this multiplex transmission device, the bits that are circular by 1 in the repeated code string signal between the transmitting/receiving means assigned the same address. 1 in sync with the pattern
This means that bit data can be sent and received. For example, if one transmitting/receiving means is assigned the same address according to a vehicle switch and a load operated corresponding to this switch, multiplex transmission of up to seven numbers is possible. It can be done.

However, in the conventional multiplex transmission device as described above, each switch and each load are configured to correspond to the above-mentioned transmitting/receiving means. There is a problem in that a transmitting/receiving means must be provided, making the device bulky.

[Object of the invention] The present invention improves the above-mentioned problems and efficiently transmits single or multiple bit combination data formed according to the degree of concentration of switches, loads, etc. according to the number of bits of the data. The purpose of the present invention is to provide a multiplex transmission device with a simple configuration that can perform the following functions.

[Summary of the Invention] In order to achieve the above object, the present invention includes a time series code generation means for generating a time series code of a predetermined system based on a synchronization signal of a predetermined period, and a time series code generating means for generating the time series code based on a synchronization signal of a predetermined period. A time series code transmission line to be transmitted, a data transmission line installed in parallel with the transmission line, and a data transmission line connected to the time series code transmission line and the data transmission line and capable of transmitting and receiving data via the data transmission line. The transmitting/receiving means detects a temporal pattern of predetermined 1-pips of the time-series code, and if the pattern matches the address assigned to itself, the transmitting/receiving means transmits the transmitted data. a gate control means for opening a data transmission/reception gate for a time corresponding to the number of pits; and a gate control means for opening a data transmission/reception gate for a time corresponding to the number of pits; The device is configured to include serial data input/output means for transmitting/receiving data as data, and is configured to transmit/receive data according to the bit length of the transmitted data.

[Explanation code for the example] Hereinafter, the present invention will be described in detail with reference to examples.

Figures 1 to 3 show an example. Figure 1 is a detailed circuit diagram of a transmitter as a transmitter, Figure 2 is a time chart showing the operation of each part, and Figure 3 is a receiver as a receiver. FIG. 3 is a detailed circuit diagram of the receiver.

As shown in FIG. 1, this multiplex transmission device includes an address lock generator 1 which is a time series code generating means, and an address lock generator 1 which is a time series code generating means.
Address lock signal AC, which is a time series code output from
The transmitter 7 has an address lock line (time series code transmission line) 3 for transmitting the data, and a data line (data transmission line) 5 installed in parallel with the line drawing 3. It is connected to wire 5. On the other hand, as shown in FIG. 3, the reception ta9 is also connected to the address lock signal line 3 and the data line 5. The transmitter 7 is provided, for example, in an instrument panel of a vehicle, and the receiver 9 is provided near a load, such as a headlamp, corresponding to one of the switches.

The address lock generator 1 width-modulates the M-sequence code with the clock signal of the period flJJT, and as shown in FIG.
” signal or a narrow “0” signal is output to the address lock line 3 in a predetermined order. In this example, it is assumed that the M-sequence signal is of fourth order.

As shown in FIG. 1, the transmitter 7 includes a 4-bit bit pattern detection circuit 11, an address setting circuit 13, and
It has an address comparison circuit 15.

The address setting circuit 13 can set any 4-bit address, but here, for example, address 111
Suppose that it is set to 1.

The bit pattern detection circuit 11 is a rising synchronization one-shot circuit 11 which inputs the address clock signal AC.
a and a 4-bit shift register 11b,
The demodulated clock signal RC, which is the output signal of the rising synchronization one-shot circuit, also serves as a shift synchronization signal for the shift register 11b.

Output signal RC of the rising synchronization one-shot circuit 11a
As shown in FIG. 2(b), is a demodulated clock signal with a period T that remains at a high level for a predetermined period of time in synchronization with the rise of the address lock signal AC. The period T of this clock signal RC matches the period T of the clock signal of the address clock generator 1.

The 4-bit shift register 11b is shown in FIG.
receives the address clock signal AC shown in the first bit DO, and in synchronization with the fall of the demodulated clock signal RC,
Address clock signals such as 101111... are sequentially reproduced, and the reproduced codes are sequentially transferred to register D1→
Move from D2 to D3. Therefore, a new bit pattern will appear one after another in the 4-bit shift register 11b, and for example, at time t4--t5- in FIG. 2, the bit pattern will be rllllJ.

The address comparison circuit 15 constantly compares the bit pattern with the set address, and if they match, it outputs an address match signal X at time T as shown in FIG. 2(d''). Output.

Further, the transmitter 7 receives the address match signal X at the set terminal S and outputs the gate open signal G as shown in FIG.
a set flip-flop 17 which outputs the signal O, a gate circuit 19 which inputs the gate opening signal Go from the output terminal Q of the flip-flop 17 and opens the gate for data transmission, and a gate circuit 19 which outputs the The AND circuit 21 inputs the demodulated clock signal RC to the other input terminal and outputs the demodulated clock signal RC while the gate opening signal Go is being output. Let this output signal be RC'. Further, the output signal RC' from the circuit 21 and the gate open signal GO of the flip-flop 17 are inputted, and the reset terminal R of the flip-flop 17 is input until the counted value of the number of pulses of the signal RC- exceeds the number of data bits 4. It has a counter circuit 23 which outputs a high level signal H as shown in FIG. 2<a).

The set value of the counter circuit 23 is set according to the number of bits, 4, of the transmission data. Said flip-flop 1
7 is the point in time when the counter circuit 23 counts the predetermined number 4 and then the rising edge of the signal RC- is input to the counter circuit (
t9), thereby stopping the output of the gate open signal GO.

Further, the transmitter 7 includes a data input section 25 capable of setting 4-bit data as a data output means, and a data input section 25 that can set 4-bit data.
5 in parallel and transfer these data to the second
As shown in FIG. 3(h), it has a data output shift register 27 which outputs one bit at a time to the data line 5 in synchronization with the rise of the signal RC'. The number of bits of data input to the data input section 25 is set to 4 in this example, but this number n is determined to be an appropriate number depending on the number of contacts of the switch group, and parity bits are added to this as appropriate. In addition, it shall be stipulated. In this example, it is assumed that the first bit of the 4-bit data is a switch signal for the headlights of the vehicle.

With the above configuration, the transmitter 7 transmits data to the data input unit 25 in an appropriate number of bits depending on the number of contacts of the switch group.
is input to the shift register 11 by the address comparison circuit 15.
If it is detected that the bit pattern appearing in b matches the set address, the second
The gate open signal Go shown in FIG. 2(e) is output from the 7-lip flop 17, and the data can be serially output to the data line 5 at the timing shown in FIG. 2(h).

On the other hand, as shown in FIG. 3, the receiver 9, like the transmitter 7, includes a bit pattern detection circuit 11, an address setting circuit 13, an address comparison circuit 15, a flip-flop 17, and a data reception gate. These components have exactly the same configuration as those of the transmitter 7.

In this example, the same address M111J as the transmitter is set in the address setting circuit.

However, in this example, this address r1111J is used to receive data of the first bit of the 4-bit data, and if data of other bits is to be received, another address must be set.

The receiver n9 has this counter circuit 23a, two data input shift registers as data input means, a data output memory 31, and a data output section 33.

The counter circuit 23a is set to the number 1 according to the number of bits of input data (1 in this example).

The data input shift register 29 receives the output signal RC' from the AND circuit 21 and takes in serial data from the data line 5 via the data input gate circuit 19 in synchronization with the fall of this signal RC'. The serial data is output from the transmitter 7, and in this example, its data length is only 1 bit.

The memory 31 takes in the data taken in by the shift register 29 in parallel in synchronization with the fall of the output signal H of the counter circuit 23a, and outputs this to the data output section 33. The data output section outputs data temporarily stored in the memory 31 to a predetermined load.

With the above configuration, the receiver 9, like the transmitter 7, opens the gate according to the number of data bits (1 bit) and synchronizes with the transmitter 7 at a predetermined time (t5- to t6-). Data of a predetermined number of bits (one bit) will be taken in.

As described above, according to the embodiment shown in FIGS. 1 to 3, the transmitter 7 and the receiver 9 perform the following operations based on the gate opening signals determined by the respective count circuits 23 and 238 of their own.
During this time, the gate of itself is opened and data is transmitted and received at predetermined timings according to the number of bits of transmitted and received data. In addition, the receiver transmits 1% in this example! 7
An example has been shown in which the first bit of 4-bit data sent from , it is also possible to sequentially and continuously receive one bit from the above-mentioned transmission and farewell or one bit from another transmitter. In addition, as another aspect, it is possible to continuously receive an appropriate number of bits from the transmitter shown in FIG. can be controlled to a predetermined value.

Other embodiments of the transmitter/receiver are shown in FIGS. 4 and 5.

FIG. 4 is a circuit diagram of the transmitter 7a, and FIG. 5 is a circuit diagram of the receiver 9a.

In this embodiment, a data length changeover switch 35 is attached to each of the counter circuits 23 of the transmitter 7a and the receiver 9a.

In the transmitter/receiver shown in this embodiment, the count number of the counter circuit 23 can be changed depending on the number of data bits at the location where it is used, making it possible to provide the transmitter/receiver with versatility.

Next, the present invention will be explained in detail using FIGS. 6 and 7. In the figure, T, T+, T2...Tn are transmitters, R
, R+, R2-Rn are the receivers, Sl...SO are the switches, and Ll...Ln are the switches S1...S.
The load corresponding to O is shown.

The example of application in Fig. 6 is an example of application to a warning indicator, and transmits R for every switch S1...3n such as a door switch, oil pressure switch, battery fluid M switch, etc.
T + ...Tn are installed, and these transmitters T1
...Receive one data sent from Tn 11R
and the indicator L1 on the instrument panel.
...[n] is lit.

In this application example, the count number 1 is set in the counter circuit of the transmitter shown in FIG. 1 or FIG. 4, and
The count number n may be set in the count circuit of the receiver shown in FIG. 3 or FIG. 5.

In this case, address No. 1 is set for the transmitter 1 and the receiver mR, and the transmitter T2...Tn is set to the quartic code string signal (
All you have to do is set the next address in sequence.

The application example in FIG. 7 is an application example where the power load is distributed such as in a cluster switch, and one transmitter T is provided corresponding to a group of centralized switches on the instrument panel.
Receivers R1 and R1 are installed for distributed loads such as the rear differential, trunk opener, fuel lid, and power antenna.
...Rn is attached.

In this application example, a count number n is set in the count circuit 23 of the transmitter T, and each reception Ill R+...Rn
The count circuit 23 is set to a count number of 1. Then, address number 121 is set in the transmitter T and receiver R1, and the next address in the fourth order M sequence signal is sequentially set in the receivers aR2...Rn. In this way, the n-bit data transmitted from the transmitting IIIT is sequentially taken into the receiving flR+...Rn one bit at a time, and each load performs a predetermined operation.

In this application example, the correspondence between the number of transmitters and the number of receivers is 1:n.
However, if the address setting method is appropriate, it goes without saying that these correspondences can be set in various ways depending on the switch or the degree of concentration of the load.

[Effects of the Invention] According to the present invention, the opening and closing times of the transmitting and receiving gates of the transmitting and receiving means are respectively controlled according to the number of data bits, and predetermined data are transmitted and received by the transmitting and receiving means respectively according to the data length. Since it is a multiplex transmission device that transmits data in a predetermined time period, it is possible to create a predetermined number of bits of data depending on the concentration of data supply parts such as switches.
A predetermined bit of data can be received depending on the concentration of data usage portions such as load, which has the effect of increasing system efficiency.

In addition, if the time width of the gate opening/closing control is performed by a count circuit installed in the transmitter/receiver, and the number of counts of this count circuit can be changed according to the data length, the transmitter/receiver of the multiplex transmission device can each be manufactured with the same configuration, making it possible to provide a highly versatile multiplex transmission device.

[Brief explanation of the drawing]

Figures 1 to 3 show an embodiment of the present invention. Figure 1 is a circuit diagram of a transmitter, Figure 2 is a time chart of signal states of various parts, and Figure 3 is a circuit diagram of a receiver. . FIGS. 4 and 5 are circuit diagrams showing other embodiments of the transmitter/receiver. FIG. 6 and FIG. 7 are explanatory diagrams showing an example of application of the present invention. 1...Address lock generator 3...Address lock line 5...Data line 7...Transmitter 9...Receiver 11...Bit pattern detection circuit 23.23a...Counter circuit patent Applicant Nissan Motor Co., Ltd. Figure 1

Claims (1)

[Claims] a time-series code generation means for generating a predetermined series of time-series codes based on a synchronization signal of a predetermined period; a time-series code transmission path for transmitting the time-series codes; and a data transmission path installed in parallel with the transmission path. , data transmitting/receiving means connected to the time series code transmission path and the data transmission path and transmitting/receiving data via the data transmission path; gate control means that detects a temporal pattern of predetermined bits of the code and opens a data transmission/reception gate for a time corresponding to the number of bits of the transmission data when the pattern matches the address assigned to itself; Serial data input/reception for transmitting/receiving data as serial data one bit at a time in accordance with the signal cycle of the synchronization signal while the data transmission/reception gate is open.
1. A multiplex transmission device comprising: output means.