JPS61263268A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS61263268A JPS61263268A JP60105503A JP10550385A JPS61263268A JP S61263268 A JPS61263268 A JP S61263268A JP 60105503 A JP60105503 A JP 60105503A JP 10550385 A JP10550385 A JP 10550385A JP S61263268 A JPS61263268 A JP S61263268A
- Authority
- JP
- Japan
- Prior art keywords
- case
- light emitting
- chip
- receiving elements
- stitch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000007789 sealing Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路に関し、特に半導体チップ（
以下単にチップとｈう）を封入するケースの構造に関す
る。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor chip (
The present invention relates to the structure of a case for enclosing a chip (hereinafter simply referred to as a chip).
従来、チップ選別工程により選別された良品チ、プは、
次工程としてケースに封入するべく組立工程にまわされ
る。第３図はこの組立工程において、ワイヤボンディン
グされた状態を示したものであシ、チップ１内に存在す
るワイヤボンディング用のバッド２と、このチップ１を
搭載している下側ケース３上のステ、チロとはＡｕ線な
どのワイヤにより接続されている。このあと上側ケース
４がかぶせられ、チップｌは上側ケース４と下側ケース
３とによシ封入される。Conventionally, good chips are selected through the chip sorting process.
The next step is an assembly process to seal it into a case. Figure 3 shows the wire bonding state in this assembly process, showing the wire bonding pad 2 inside the chip 1 and the lower case 3 on which the chip 1 is mounted. The station and chiro are connected by wires such as Au wires. After that, the upper case 4 is covered, and the chip l is enclosed between the upper case 4 and the lower case 3.
上述した従来構造のケースを用いたチップの封入方法で
は、チップｌのバッド２と、ステ、チロとはそれぞれ１
本のワイヤによシワイヤボンダーによって接続される為
、半導体の信号線数の増加に伴ないワイヤボンディング
に要する時間が増大する欠点がある。特に最近は半導体
集積回路の多ビン化に伴ない、この傾向は増々顕著にな
って来てお一シ、ワイヤボンディング工程の時間を短縮
することが望まれている。In the chip encapsulation method using the case with the conventional structure described above, the pad 2 of the chip L, the stage, and the chiro are each 1
Since the wires are connected using a wire bonder, there is a drawback that the time required for wire bonding increases as the number of signal lines of the semiconductor increases. In particular, this trend has become more and more pronounced as the number of semiconductor integrated circuits increases, and it is desired to shorten the time required for the wire bonding process.
本発明の目的は、上記欠点を除去し、ワイヤボンディン
グに要する時間をなくし、組立時間の短縮可能なケース
を有する半導体集積回路を提供することＫある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit which eliminates the above-mentioned drawbacks, eliminates the time required for wire bonding, and has a case in which assembly time can be shortened.
本発明の半導体集積回路は発光・受光素子を形成した入
出力パッドを複数個有する半導体チップを実装固定し７
’（第１のケースと、発光・受光素子を形成した複数個
のステッチを有する第２のケースと、前記第１のケース
の入出力パッドと前記第２のケースのステッチとを接続
する導光管とを有するものである。The semiconductor integrated circuit of the present invention has a semiconductor chip having a plurality of input/output pads forming light emitting/light receiving elements mounted and fixed.
(a first case, a second case having a plurality of stitches forming light emitting/light receiving elements, and a light guide connecting the input/output pad of the first case and the stitch of the second case) It has a tube.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を説明する為の斜視図であシ
、第２図は第１図におけるパッド部とステッチ部近傍の
断面図である。FIG. 1 is a perspective view for explaining one embodiment of the present invention, and FIG. 2 is a sectional view of the vicinity of the pad portion and stitch portion in FIG. 1.
第１図及び第２図において、チップ１は発光・受光素子
が形成されたパッド２を有し、下側ケース３に搭載され
ている。また上側ケース４には端子５、およびステ、チ
ロを接続する為の配線７が形成されており、さらにステ
ッチ６にはチップ１のパッド２と同様に発光・受光素子
が形成されている。そしてステッチ６の先端には中空の
導光管８が接続されている。In FIGS. 1 and 2, a chip 1 has a pad 2 on which a light emitting/light receiving element is formed, and is mounted on a lower case 3. Further, the upper case 4 is formed with a terminal 5 and wiring 7 for connecting the stem and chiro, and the stitch 6 is further formed with a light emitting/light receiving element similar to the pad 2 of the chip 1. A hollow light guide tube 8 is connected to the tip of the stitch 6.
上側ケース４の複数の導光管８は、それぞれ下側ケース
３に搭載されたチップ１の複数のパッド２に形成されて
いる発光・受光素子と対応しておシ、テップ１を下側ケ
ース３に固定後、上側ケース４と下側ケース３を接続封
止するときに、同時にそれぞれ対応するパッド２に接続
するように構成されている。従ってチップ１内の回路と
、ケースの端子５との間の電気信号は、全てこの発光・
受光素子によシ光に変換されて送受信されるととＫなる
為、従来のワイヤボンディングによらずにチップ１と端
子５との接続が可能となる。The plurality of light guide tubes 8 of the upper case 4 correspond to the light emitting/light receiving elements formed on the plurality of pads 2 of the chip 1 mounted on the lower case 3, respectively. 3, and when the upper case 4 and the lower case 3 are connected and sealed, they are simultaneously connected to the corresponding pads 2. Therefore, all electrical signals between the circuit inside the chip 1 and the terminal 5 of the case are transmitted by this light emission.
When the light is converted into light by the light receiving element and transmitted and received, it becomes K, so it becomes possible to connect the chip 1 and the terminals 5 without using conventional wire bonding.
以上説明したように、本発明によれば、上側ケースに端
子、配線、発光・受光素子を形成したステッチおよび導
光管を形成すると同時に、下側ケースに搭載される半導
体チップのパッド部にも発光・受光素子を形成し、これ
らステッチおよびパッド内のそれぞれ対応する発光・受
光素子間は、上側ケースのステ、チ部に用意された導光
管を通して、上側ケースを下側ケースに接続するときに
、同時に接続されるように構成した半導体集積回路が得
られるのでワイヤボンディング作業が不要となシ、組立
工程の時間短縮に大きな効果がある。As explained above, according to the present invention, the terminals, wiring, stitches and light guide tubes in which the light emitting and light receiving elements are formed are formed on the upper case, and at the same time, the pads of the semiconductor chips mounted on the lower case are also formed. When connecting the upper case to the lower case, the light emitting and light receiving elements are formed and the corresponding light emitting and light receiving elements in these stitches and pads are connected through light guide tubes prepared in the stem and groove parts of the upper case. Furthermore, since a semiconductor integrated circuit configured to be connected simultaneously can be obtained, wire bonding work is not necessary, which has a great effect on shortening the assembly process time.
第１図は本発明の一実施例を説明するための斜視図、第
２図は第１図におけるパッド部とステ。
チ部近傍の断面図、第３図は従来の半導体集積回路の組
立を示す斜視図である。
１・・・・・・チップ、２・・・・・・パッド、３・・
・・・・下側ケース、４・・・・・・上側ケース、５・
・・・・・端子、６・・・・・・ステッチ、７・・・・
・・配線、８・・・・・・導光管。
＄−１凹
茅 Ｚ 回FIG. 1 is a perspective view for explaining one embodiment of the present invention, and FIG. 2 is a pad portion and a stem in FIG. 1. FIG. 3 is a cross-sectional view of the vicinity of the chip, and FIG. 3 is a perspective view showing the assembly of a conventional semiconductor integrated circuit. 1...chip, 2...pad, 3...
...Lower case, 4...Upper case, 5.
...Terminal, 6...Stitch, 7...
...Wiring, 8...Light guide tube. $-1 concave Z times
Claims (1)
半導体チップを実装固定した第１のケースと、発光・受
光素子を形成した複数個のステッチを有する第２のケー
スと、前記第１のケースの入出力パッドと前記第２のケ
ースのステッチとを接続する導光管とを含むことを特徴
とする半導体集積回路。a first case in which a semiconductor chip having a plurality of input/output pads forming light emitting and light receiving elements is mounted and fixed; a second case having a plurality of stitches forming light emitting and light receiving elements; and the first case. A semiconductor integrated circuit comprising: a light guide tube connecting the input/output pad of the second case to the stitch of the second case.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60105503A JPS61263268A (en) | 1985-05-17 | 1985-05-17 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60105503A JPS61263268A (en) | 1985-05-17 | 1985-05-17 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61263268A true JPS61263268A (en) | 1986-11-21 |
Family
ID=14409401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60105503A Pending JPS61263268A (en) | 1985-05-17 | 1985-05-17 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61263268A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5382810A (en) * | 1991-02-27 | 1995-01-17 | Asea Brown Boveri Ab | Optoelectronic component |
-
1985
- 1985-05-17 JP JP60105503A patent/JPS61263268A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5382810A (en) * | 1991-02-27 | 1995-01-17 | Asea Brown Boveri Ab | Optoelectronic component |
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