JPS6126284A - Hybrid integrated circuit board - Google Patents
Hybrid integrated circuit boardInfo
- Publication number
- JPS6126284A JPS6126284A JP14804384A JP14804384A JPS6126284A JP S6126284 A JPS6126284 A JP S6126284A JP 14804384 A JP14804384 A JP 14804384A JP 14804384 A JP14804384 A JP 14804384A JP S6126284 A JPS6126284 A JP S6126284A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- circuit board
- conductor film
- insulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は高周波を扱う混成集積回路を量産する場合に用
いることができる混成集積回路基板に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a hybrid integrated circuit board that can be used in the mass production of hybrid integrated circuits that handle high frequencies.
従来例の構成とその問題点
従来混成集積回路は第１図に示すように絶縁基板１の一
方の面にのみチップ抵抗３．チップコンデンサ４および
トランジスタ５等の混成集積回路構成部品を載置するこ
とを主として、設計、製造されてきた。そして、エレク
トロニクス技術の進展により、上記混成集積回路も高周
波化に対応する必要に迫られてきている。この高周波回
路を上記混成集積回路で構成した場合、平面導体２の引
きまわしによシインダクタンスを形成し、またそのわず
かな導体抵抗により所望の高周波特性が得られなくなる
。このような場合、基板１の裏面に全面の導体膜６を設
けこれを接地することにより表面の導体回路の対接地イ
ンピーダンスを減少させ、上記の寄生インダクタンスや
寄生抵抗による影響をなくし、所望の高周波特性を得る
ことができる。Conventional Structure and Problems In the conventional hybrid integrated circuit, as shown in FIG. 1, a chip resistor 3. It has been designed and manufactured primarily for mounting hybrid integrated circuit components such as chip capacitors 4 and transistors 5. With the progress of electronics technology, the above-mentioned hybrid integrated circuits are also required to be compatible with higher frequencies. When this high frequency circuit is constructed from the above-mentioned hybrid integrated circuit, an inductance is formed due to the routing of the planar conductor 2, and the slight conductor resistance makes it impossible to obtain desired high frequency characteristics. In such a case, by providing a conductor film 6 on the entire surface of the substrate 1 and grounding it, the impedance to ground of the conductor circuit on the front surface is reduced, the influence of the above-mentioned parasitic inductance and parasitic resistance is eliminated, and the desired high frequency characteristics can be obtained.
ところが裏面に導体膜を設けることによシ、混成集積回
路基板に微小部品を載置しハンダリフローで組み立てる
際、上記基板裏面の全面導体膜が絶縁物である基板材料
よシ熱膨張係数が大きいため、ハンダリフローの温度上
昇により第２図に示すように基板が凹型に反シを生じ、
微小部品のハンダによる位置固定に支障を来たすという
、量産上の問題点があった。However, by providing a conductive film on the back side, when microcomponents are mounted on a hybrid integrated circuit board and assembled by solder reflow, the coefficient of thermal expansion is higher than that of a substrate material in which the entire conductive film on the back side of the board is an insulator. As a result, the board becomes warped in a concave shape as shown in Figure 2 due to the rise in temperature during solder reflow.
There was a problem in mass production in that it interfered with fixing the position of minute parts with solder.
発明の目的
本発明はこのような従来の欠点を除去するものであり、
簡単な構成で量産上の問題点を解消し、しかも高周波特
性をも損うことのない優れた混成集積回路基板を提供す
るものである。OBJECTS OF THE INVENTION The present invention obviates these conventional drawbacks,
The object of the present invention is to provide an excellent hybrid integrated circuit board that has a simple configuration, solves problems in mass production, and does not impair high frequency characteristics.
発明の構成
本発明忙よる混成集積回路基板は、基板裏面に接地導体
膜を有し、この接地導体膜に絶縁体の露出する部分をス
リット状に設けたものであシ、この構成とすることによ
シ裏面接地導体膜の温度上昇時の膨張はスリット部分で
分散され、混成集積回路基板の反りは生じなくなる〇
実施例の説明
以下、本発明の一実施例を図面を参照して説明する。第
３図に示すように絶縁体よシなる基板７の裏面に設けら
れた接地導体膜８を加工し、絶縁体の露出した部分９を
スリット状に設けることによシ、スリットによシ分断さ
れた導体片は、混成集積回路基板が構成された基板７が
昇温時の熱膨張を生じても、基板７との熱膨張係数差に
よる延びをこのスリットにより吸収し、裏面接地導体膜
８の総体として基板７に反りを生じるようなストレスを
生じさせることはない。ここで、第４図に示すように絶
縁体の露出した部分１０を格子状のスリットとすること
によっても同様な目的は達せられる。Composition of the Invention The hybrid integrated circuit board according to the present invention has a ground conductor film on the back surface of the board, and the ground conductor film has a slit-like portion where an insulator is exposed. The expansion of the back ground conductor film when the temperature rises is dispersed in the slit portion, and the hybrid integrated circuit board no longer warps.Description of an EmbodimentHereinafter, an embodiment of the present invention will be described with reference to the drawings. . As shown in FIG. 3, the ground conductor film 8 provided on the back surface of the substrate 7 made of an insulator is processed, and the exposed portion 9 of the insulator is provided in a slit shape. Even if the substrate 7 on which the hybrid integrated circuit board is formed undergoes thermal expansion when the temperature rises, the slit absorbs the elongation due to the difference in coefficient of thermal expansion with the substrate 7, and the back ground conductor film 8 As a whole, stress that would cause the substrate 7 to warp is not generated. Here, the same purpose can also be achieved by forming the exposed portion 10 of the insulator into a grid-like slit as shown in FIG.
発明の効果
以上のように本発明は高周波を扱う混成集積回路基板に
おいて、裏面接地導体膜による寄生インダクタンスや寄
生抵抗の発生を減殺する効果を損うことなく、駿特性の
改善に寄与し、且つ混成集積回路基板のハンダリフロー
による組み立て時の裏面接地導体膜の熱膨張に起因する
基板の反シをなくした大量生産性に寄与すること大なる
、実用上きわめて有利なものである。Effects of the Invention As described above, the present invention contributes to improving the speed characteristics of a hybrid integrated circuit board that handles high frequencies without impairing the effect of reducing the generation of parasitic inductance and parasitic resistance due to the back ground conductor film. This is extremely advantageous in practice, as it contributes to mass productivity by eliminating board warping caused by thermal expansion of the back ground conductor film during assembly of hybrid integrated circuit boards by solder reflow.
第１図は従来例の基板を用いた構成による混成集積回路
の断面図、第２図は第１図の構成によるハンダリフロ一
時の基板の反りの状態を示す断面図、第３図は本発明に
よる混成集積回路用基板の一実施例を示す下面図、第４
図は本発明の他の実施例を示す下面図である。
７・・・・・・基板、８・・・・・・接地導体膜、９，
１０・・・・・・絶縁体の露出した部分。
代理人の氏名 弁理士 中 尾、敏 男 ほか１名第１
図
第３図
第４図Fig. 1 is a cross-sectional view of a hybrid integrated circuit constructed using a conventional substrate, Fig. 2 is a cross-sectional view showing the state of warpage of the board during solder reflow using the structure shown in Fig. 1, and Fig. 3 is a cross-sectional view according to the present invention. A fourth bottom view showing an embodiment of the hybrid integrated circuit board.
The figure is a bottom view showing another embodiment of the present invention. 7...Substrate, 8...Grounding conductor film, 9,
10...Exposed part of the insulator. Name of agent: Patent attorney Nakao, Toshio, and 1 other person 1st
Figure 3 Figure 4
Claims (1)
地導体膜に絶縁体の露出する部分をスリット状を設けた
ことを特徴とする混成集積回路基板。1. A hybrid integrated circuit board comprising a ground conductor film on the back surface of a substrate made of an insulator, and a slit-shaped portion of the ground conductor film where the insulator is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14804384A JPS6126284A (en) | 1984-07-16 | 1984-07-16 | Hybrid integrated circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14804384A JPS6126284A (en) | 1984-07-16 | 1984-07-16 | Hybrid integrated circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6126284A true JPS6126284A (en) | 1986-02-05 |
Family
ID=15443848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14804384A Pending JPS6126284A (en) | 1984-07-16 | 1984-07-16 | Hybrid integrated circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6126284A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63139589U (en) * | 1987-03-05 | 1988-09-14 | ||
| JP2008112862A (en) * | 2006-10-30 | 2008-05-15 | Nec Saitama Ltd | Double-side printed wiring circuit board, electronic device, and method of manufacturing the double-side printed wiring circuit board |
| JP2009094168A (en) * | 2007-10-04 | 2009-04-30 | Denso Corp | Circuit board |
| JP2009206262A (en) * | 2008-02-27 | 2009-09-10 | Rohm Co Ltd | Semiconductor integrated circuit |
| JP2012527185A (en) * | 2009-05-15 | 2012-11-01 | シーティーエス・コーポレーション | High performance RFRx module |
| JP2012253988A (en) * | 2011-06-07 | 2012-12-20 | Denso Corp | Power conversion device |
| JP2017054990A (en) * | 2015-09-10 | 2017-03-16 | パナソニックＩｐマネジメント株式会社 | Light emitting device |
| WO2017068917A1 (en) * | 2015-10-21 | 2017-04-27 | シャープ株式会社 | Glass wired substrate and power module |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4119947Y1 (en) * | 1964-01-18 | 1966-09-20 |
-
1984
- 1984-07-16 JP JP14804384A patent/JPS6126284A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4119947Y1 (en) * | 1964-01-18 | 1966-09-20 |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63139589U (en) * | 1987-03-05 | 1988-09-14 | ||
| JP2008112862A (en) * | 2006-10-30 | 2008-05-15 | Nec Saitama Ltd | Double-side printed wiring circuit board, electronic device, and method of manufacturing the double-side printed wiring circuit board |
| JP2009094168A (en) * | 2007-10-04 | 2009-04-30 | Denso Corp | Circuit board |
| JP2009206262A (en) * | 2008-02-27 | 2009-09-10 | Rohm Co Ltd | Semiconductor integrated circuit |
| JP2012527185A (en) * | 2009-05-15 | 2012-11-01 | シーティーエス・コーポレーション | High performance RFRx module |
| JP2012253988A (en) * | 2011-06-07 | 2012-12-20 | Denso Corp | Power conversion device |
| JP2017054990A (en) * | 2015-09-10 | 2017-03-16 | パナソニックＩｐマネジメント株式会社 | Light emitting device |
| WO2017068917A1 (en) * | 2015-10-21 | 2017-04-27 | シャープ株式会社 | Glass wired substrate and power module |
| JPWO2017068917A1 (en) * | 2015-10-21 | 2018-06-28 | シャープ株式会社 | Glass wiring board and power module |
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