JP2606316B2 - Manufacturing method of integrated circuit package - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an integrated circuit package mounted on a computer or the like, and particularly to a multi-pin PGA for surface mounting.
(Pin grid array).

[Conventional technology]

Conventionally, a method of manufacturing an integrated circuit package of this kind is to form a ceramic substrate having a wiring layer inside, then solder a plurality of I / O pins to one surface of the ceramic substrate, and perform a manufacturing process in this state. Had been terminated.

[Problems to be solved by the invention]

In the conventional method for manufacturing an integrated circuit package described above,
As shown in FIG. 4, in the completed integrated circuit package, the plurality of I / O pins 2 soldered to the ceramic substrate 1 are all exposed, so that the I / O pins 2 are easily bent by external force. However, there is a drawback that buckling easily occurs.

Further, the height of the tips of the plurality of I / O pins 2 is dominant in the mounting accuracy of the I / O pins 2 in the brazing process, so that the variation is large and the flatness of the tips of the I / O pins 2 is poor. . Furthermore, I
If the number of / O pins 2 is more than 100 pins or the package size is more than 30mm ^□ , the package itself will warp, or the printed circuit board on which the integrated circuit package is mounted, and the thermal expansion of both. When soldering the I / O pins 2 to a printed circuit board due to the influence of thermal stress or the like caused by the difference in the coefficients, unsoldering, disconnection, and the like occur, which makes it difficult to perform normal soldering.

[Means for solving the problem]

The method for manufacturing an integrated circuit package according to the present invention includes the step of: mounting the plurality of I / O pins on a surface of the ceramic substrate on which the plurality of I / O pins are fixed.
A step of applying an organic resin layer so as to cover all the pins,
A step of polishing the surface of the organic resin layer until the tip of the I / O pin is exposed; and a step of etching the surface of the polished organic resin.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are sectional views showing an embodiment of the present invention in the order of steps, FIG. 2 is a perspective view of an integrated circuit package manufactured by the embodiment shown in FIG. 1, and FIG. FIG. 3 is a cross-sectional view when the integrated circuit package of the embodiment is mounted on a printed circuit board 4.

In this embodiment, first, I / O pins 2 are soldered to a ceramic substrate 1 as in the conventional manufacturing method (FIG. 1A). In this step, there is no pin bending yet. Next, as shown in FIG. 1 (b), an organic resin layer 3 is applied so that all the I / O pins 2 are covered on the entire surface of the ceramic substrate 1 on which the plurality of I / O pins 2 are formed. . As a material of the organic resin layer 3, for example, polyimide is used in terms of heat resistance, workability, and the like. Next, as shown in FIG.
The surface of the organic resin layer 3 is polished and flattened until the tip of the I / O pin 2 is exposed.

Next, as shown in FIG. 1 (d), the surface of the flattened organic resin layer 3 is chemically etched with a hydrazine hydrate-based solvent or physically or chemically etched with O ₂ plasma or the like. Thus, the surface of the organic resin layer 3 is etched to a designed depth. in this case,
The etching depth is generally about 1 to 3 mm. I / O
Since the pin 2 (made of KOVAR or 42Alloy) is not etched, about 1 to 3 mm of the tip of the I / O pin 2 is exposed.

In this embodiment, since the flatness of the tips of the plurality of I / O pins 2 is good due to the polishing process, the I / O pins 2 are as shown in FIG.
When the pins 2 are soldered to the printed circuit board 4, the occurrence of unsoldering can be prevented. Furthermore, since the solder wicking is completely stopped by the organic resin 3, the solder fillet can be formed almost as designed. Third
This is shown in the figure.

〔The invention's effect〕

As described above, the present invention covers an I / O pin of an integrated circuit PGA package by covering a plurality of I / O pins with an organic resin layer, polishing the tip, and then etching the surface of the organic resin layer, thereby providing an I / O by external force. While preventing the bending of the pin,
There is an effect that high quality and reliable soldering without solder wicking can be performed.

[Brief description of the drawings]

1 (a) to 1 (d) are sectional views showing an embodiment of the present invention in the order of steps, FIG. 2 is a perspective view of an integrated circuit package manufactured by the embodiment shown in FIG. 1, and FIG. Sectional view when the integrated circuit package of the embodiment is mounted on a printed circuit board 4;
FIG. 4 is a side view of an integrated circuit package manufactured by a conventional manufacturing method. 1. Ceramic substrate, 2. I / O pins, 3. Organic resin layer, 4. Printed circuit board.

Claims (1)

(57) [Claims] A step of applying an organic resin layer on the surface of the ceramic substrate on which the plurality of I / O pins are fixed, so as to cover all of the plurality of I / O pins; A method for manufacturing an integrated circuit package, comprising: a step of polishing the surface of the organic resin layer until the surface is exposed; and a step of etching the surface of the polished organic resin.