JPS6126238B2 - - Google Patents

Info

Publication number
JPS6126238B2
JPS6126238B2 JP51127526A JP12752676A JPS6126238B2 JP S6126238 B2 JPS6126238 B2 JP S6126238B2 JP 51127526 A JP51127526 A JP 51127526A JP 12752676 A JP12752676 A JP 12752676A JP S6126238 B2 JPS6126238 B2 JP S6126238B2
Authority
JP
Japan
Prior art keywords
mesa
oxide film
gaas
forming
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51127526A
Other languages
Japanese (ja)
Other versions
JPS5352063A (en
Inventor
Takeshi Suzuki
Mikio Nishihata
Michihiro Ito
Hironobu Hatakeyama
Hidejiro Miki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12752676A priority Critical patent/JPS5352063A/en
Publication of JPS5352063A publication Critical patent/JPS5352063A/en
Publication of JPS6126238B2 publication Critical patent/JPS6126238B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H—ELECTRICITY
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    • H01L2924/01028—Nickel [Ni]
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    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
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    • H01L2924/1025—Semiconducting materials
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    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 この発明は、pn接合半導体装置の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a pn junction semiconductor device.

GaAs半導体材料を用いたpn接合変調用ダイオ
ードは、Si半導体材料を用いた場合、300〓付近
でSiの移動度が1500cm2/V・S程度であるのに対
し、GaAsのそれは8000cm2/V・S程度とかなり大き
く、高周波領域では優れた特性を示すため、重要
な半導体装置となつている。しかし、この優れた
特性に反して製造方法は難しく、Si半導体材料を
用いた場合に比べ特性のバラツキ、歩留りはかな
り低くなつている。 In a pn junction modulation diode using GaAs semiconductor material, when Si semiconductor material is used, the mobility of Si is about 1500cm 2 /V・S near 300〓, whereas that of GaAs is 8000cm 2 /V・It is quite large, on the order of S, and exhibits excellent characteristics in the high frequency range, making it an important semiconductor device. However, despite these excellent characteristics, the manufacturing method is difficult, and the characteristics vary and the yield is considerably lower than when Si semiconductor materials are used.

以下に一般に行われているこの種の半導体装置
の製造方法について説明する。 A commonly used method for manufacturing this type of semiconductor device will be described below.

第１図ａ，ｂ，ｃは従来のpn接合変調用ダイ
オードの製造方法の工程を示す断面図で、まず、
第１図ａのように不純物濃度が約１×1018cm-3の
n+GaAs基板１と不純物濃度が約１〜３×1016cm
-3のn-層２からなるGaAsウエハを封管法あるい
は開管法により、ｐ形の不純物をドープしｐ層３
を形成した後、ｐ形のオーミツク電極４を、例え
ばAu−Niをメツキあるいは蒸着により形成し、
pn接合形GaAsウエハを構成する。 Figures 1a, b, and c are cross-sectional views showing the steps of a conventional pn junction modulation diode manufacturing method.
As shown in Figure 1a, the impurity concentration is approximately 1×10 18 cm -3.
n + GaAs substrate 1 and impurity concentration approximately 1~3×10 16 cm
A GaAs wafer consisting of -3 n -layer 2 is doped with p-type impurities by a sealed tube method or an open tube method, and the p-layer 3 is doped with p-type impurities.
After forming the p-type ohmic electrode 4, for example, by plating or vapor depositing Au-Ni,
Construct a pn junction type GaAs wafer.

次いで、第１図ｂのように写真製版技術を用い
て所望の大きさのリード電極５を、例えばAuを
メツキあるいは蒸着等により形成し、その後、第
１図ｃのようにGaAs用エツチング液を用いてメ
サ形にエツチングを施し、これを第２図のように
ペレツト状にダイシングしてこれにワイヤ６をボ
ンデイングしてペレツトを構成していた。 Next, as shown in FIG. 1b, a lead electrode 5 of a desired size is formed by plating or vapor-depositing Au, for example, using photolithography, and then, as shown in FIG. 1c, an etching solution for GaAs is applied. The pellets were etched into a mesa shape, diced into pellets as shown in FIG. 2, and wires 6 were bonded to the pellets to form pellets.

上記従来の方法で何種類もの異なつた容量のダ
イオードを得るには、各容量毎に第１図に示した
工程により、その容量に応じてメサ部の大きさの
異なつたものを形成するか、一枚のウエハ内に何
種頼かの大きさのメサパターンを形成する方法が
考えられる。しかし、前者は時間がかゝるととも
に何枚ものウエハを取り扱うことにより、破損あ
るいはエツチングの失敗等により歩留りを低下さ
せる。また後者は一度に異なつた大きさのパター
ンをエツチングするため、パターンによりサイド
エツチングのされかたが異なることが多いため、
容量調整が難しくなり、さらに不必要な容量のも
のができるために不経済となる。また第２図に示
すようにエツチングの際にサイドエツチングされ
るため、リード電極５はカサ状にあり、電極面積
が小さくなるとネイルヘツドボンデイングあるい
はウエツジボンデイングした際、ワイヤ６の球状
部によつて押されリード電極５のエツジ部はn-
層２あるいはn+GaAs基板１等のGaAs面に接触
する場合が多く、不良の原因となる等の欠点があ
つた。 In order to obtain diodes with a number of different capacitances using the conventional method described above, one can form diodes with different mesa sizes depending on the capacitance by the process shown in FIG. 1 for each capacitance. One possible method is to form mesa patterns of various sizes within a single wafer. However, the former method is time-consuming and involves handling a large number of wafers, resulting in a decrease in yield due to breakage or etching failure. In addition, since the latter etches patterns of different sizes at once, the side etching method often differs depending on the pattern.
It becomes difficult to adjust the capacity, and it becomes uneconomical because unnecessary capacity is created. In addition, as shown in FIG. 2, the lead electrode 5 is side-etched during etching, so the lead electrode 5 has an umbrella-like shape, and when the electrode area is small, the spherical part of the wire 6 is used when performing nail head bonding or wedge bonding. The edge part of the pressed lead electrode 5 is n -
It often comes into contact with the GaAs surface of the layer 2 or the n + GaAs substrate 1, which has the disadvantage of causing defects.

この発明は、上記欠点を除去するためになされ
たもので、メサエツチングされたpn接合半導体
にあらかじめ酸化膜を施し、メサ部のみをリード
電極およびメサ間導電路用として所望の大きさに
穴あけしてから、リード電極形成と同時に所望の
数のメサを導電するための導電路を形成した後、
ダイシングしてGaAsペレツトとし、ワイヤボン
デイングした後に、前記酸化膜を除去するように
したものである。以下この発明について説明す
る。 This invention was made to eliminate the above-mentioned drawbacks, and involves applying an oxide film in advance to a mesa-etched pn junction semiconductor, and drilling holes of a desired size only in the mesa portion for use as lead electrodes and inter-mesa conductive paths. After forming lead electrodes and forming conductive paths to conduct electricity through the desired number of mesas,
After dicing into GaAs pellets and wire bonding, the oxide film is removed. This invention will be explained below.

第３図はこの発明の製造方法の一実施例を示す
工程図であり、図中第１図と同一符号は同一部分
を示す。第１図の従来例との相違点はメサ部形成
後に酸化膜７を施し、リード電極５および導電路
形成後に前記酸化膜７を除去するようにしたこと
である。 FIG. 3 is a process diagram showing an embodiment of the manufacturing method of the present invention, in which the same reference numerals as in FIG. 1 indicate the same parts. The difference from the conventional example shown in FIG. 1 is that the oxide film 7 is applied after the mesa portion is formed, and the oxide film 7 is removed after the lead electrode 5 and the conductive path are formed.

次にこの発明の製造工程について説明する。ま
ず、第３図ａのように第１図と同様の工程でメサ
部を形成した後、酸化膜７をＣ・Ｖ・Ｄあるいは
スパツタリングによつて前記メサエツチングされ
たメサ部に施し、次いで写真製版技術によりメサ
部に施された酸化膜７を所望の大きさに穴あけを
行う。 Next, the manufacturing process of this invention will be explained. First, as shown in FIG. 3a, a mesa portion is formed in the same process as in FIG. 1, and then an oxide film 7 is applied to the etched mesa portion by CVD or sputtering. A hole is formed to a desired size in the oxide film 7 formed on the mesa portion using a technique.

次に第３図ｂのように上記GaAsウエハにリー
ド電極５およびメサ間を橋絡する導電路５′を形
成するため全面、すなわち、酸化膜７および酸化
膜７が除去されたメサ部に蒸着等で金属膜を形成
し、その後写真製版技術で所望形状の導電路を形
成し、さらにメツキ等で金属膜を厚膜にした後、
第３図ｃのように酸化膜７を条去してGaAsウエ
ハを構成したものである。このGaAsウエハをダ
イシングすることによりメサ形のGaAsペレツト
を得ることができる。 Next, as shown in FIG. 3b, vapor deposition is performed on the entire surface of the GaAs wafer, that is, on the oxide film 7 and the mesa part from which the oxide film 7 has been removed, in order to form a lead electrode 5 and a conductive path 5' bridging between the mesas. After forming a metal film using photolithography, etc., forming a conductive path in the desired shape using photolithography, and making the metal film thicker using plating, etc.,
As shown in FIG. 3c, the oxide film 7 is removed to form a GaAs wafer. By dicing this GaAs wafer, mesa-shaped GaAs pellets can be obtained.

第４図は４個のメサ部を導電路５′により橋絡
したGaAsペレツトの例を示したものである。 FIG. 4 shows an example of a GaAs pellet in which four mesas are bridged by conductive paths 5'.

この発明による製造工程を用いると種々の容量
のものが得られる。例えば第３図ａにおいて、接
合容量0.2PF、0.3PF、0.5PFになるようにメサ部
面積を形成した３種類のGaAsウエハあるいは
0.1PF程度のものを１種類作成しておけば、必要
に応じて無駄なく種々の容量のダイオードが得ら
れることが分る。また組立に際し、第３図ｂの構
成のGaAsウエハをダイシングによりペレツトに
しておき、ワイヤボンデイングを行い、その後に
酸化膜７を除去する工程を用いるならば従来方法
により製造されたペレツトで生じたリード電極５
とGaAs面との接触はなくなり、さらに酸化膜７
が圧力に対する緩衝物となるためメサ部エツジで
の歪みも減少される。 Various capacities can be obtained using the manufacturing process according to the invention. For example, in Figure 3a, three types of GaAs wafers or
It can be seen that by making one type of diodes of about 0.1PF, diodes with various capacities can be obtained as needed without wasting any waste. Furthermore, if the process of assembling a GaAs wafer with the configuration shown in FIG. 3b is diced into pellets, wire bonding is performed, and then the oxide film 7 is removed, the leads generated in the pellets produced by the conventional method are used. Electrode 5
The contact with the GaAs surface disappears, and the oxide film 7
The distortion at the mesa edge is also reduced because it acts as a pressure buffer.

以上詳細に説明したように、この発明はメサエ
ツチングに酸化膜を施し、その後メサ部間を金属
膜で橋絡するようにしたので、一枚のGaAsウエ
ハから種々の容量のダイオードが無駄なく得ら
れ、またワイヤボンデイング後に酸化膜を取り除
くようにすることにより、リード電極とGaAs面
との接触はなくなり、従つてその際生じる不良を
激減することができる。さらにワイヤボンデイン
グ時に酸化膜が存在することでメサ部で歪みの発
生を少なくし、これによる不良も少なくすること
ができ、歩留りの向上および作業能率の向上が実
現できる。 As explained in detail above, in this invention, an oxide film is applied to the mesa etching, and then the mesa parts are bridged with a metal film, so diodes of various capacities can be obtained from a single GaAs wafer without waste. Furthermore, by removing the oxide film after wire bonding, there is no contact between the lead electrode and the GaAs surface, and therefore, defects that occur during this process can be drastically reduced. Furthermore, the presence of the oxide film during wire bonding reduces the occurrence of distortion in the mesa portion, which reduces the number of defects caused by this, and improves yield and work efficiency.

かようにこの発明は従来の欠点を簡単な構成で
解決した工業的価値の高いものである。 As described above, this invention solves the conventional drawbacks with a simple structure and is of high industrial value.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ，ｂ，ｃは従来のGaAsウエハの製造
工程を示す断面図、第２図は第１図の従来の製造
工程により作成されたペレツトの断面図、第３図
ａ，ｂ，ｃはこの発明の製造方法の一実施例の製
造工程を示す断面図、第４図はこの発明により作
成されたpn接合半導体装置の構成斜視図であ
る。 図中、１はn+GaAs基板、２はn-層、３はｐ
層、４はオーミツク電極、５はリード電極、５′
は導電絡、６はワイヤ、７は酸化膜である。なお
図中の同一符号は同一または相当部分を示。 Figures 1a, b, and c are cross-sectional views showing the conventional manufacturing process for GaAs wafers; Figure 2 is a cross-sectional view of pellets produced by the conventional manufacturing process shown in Figure 1; Figures 3a, b, and c 4 is a cross-sectional view showing the manufacturing process of an embodiment of the manufacturing method of the present invention, and FIG. 4 is a perspective view of the configuration of a pn junction semiconductor device manufactured according to the present invention. In the figure, 1 is an n + GaAs substrate, 2 is an n - layer, and 3 is a p
layer, 4 is an ohmic electrode, 5 is a lead electrode, 5'
6 is a conductive circuit, 6 is a wire, and 7 is an oxide film. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] １ n+−ｎ−pGaAs半導体ウエハのｐ層側にオ
ーミツク電極を形成し、前記半導体にメサエチチ
ングにより所望の形状のメサ部を複数個形成した
後、前記オーミツク電極を除く全面に酸化膜を施
し、次いで前記酸化膜の前記各メサ部分を所望の
大きさに除去した後、全面に金属膜を形成し、そ
の後リード電極および前記各々のメサ部間を橋絡
させる導電路を前記金属膜に写真製版技術により
形成した後、前記リード電極および導電路を厚膜
とし、次いでダイシングしてメサ形のGaAsペレ
ツトとした後、ワイヤボンデイングを施し、その
後、残りの酸化膜を除去することを特徴とする
pn接合半導体装置の製造方法。1. Forming an ohmic electrode on the p-layer side of a n + -n-p GaAs semiconductor wafer, forming a plurality of mesa portions of a desired shape on the semiconductor by mesa etching, and then applying an oxide film to the entire surface except for the ohmic electrode, Next, after removing each of the mesa portions of the oxide film to a desired size, a metal film is formed on the entire surface, and then a lead electrode and a conductive path bridging between the mesa portions are formed on the metal film by photolithography. The method is characterized in that after forming the lead electrodes and conductive paths using a thick film, the lead electrodes and conductive paths are formed into a thick film, which is then diced into mesa-shaped GaAs pellets, which are then subjected to wire bonding, and then the remaining oxide film is removed.
A method for manufacturing a pn junction semiconductor device.
JP12752676A 1976-10-22 1976-10-22 Production of pn junction semiconductor unit Granted JPS5352063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12752676A JPS5352063A (en) 1976-10-22 1976-10-22 Production of pn junction semiconductor unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12752676A JPS5352063A (en) 1976-10-22 1976-10-22 Production of pn junction semiconductor unit

Publications (2)

Publication Number Publication Date
JPS5352063A JPS5352063A (en) 1978-05-12
JPS6126238B2 true JPS6126238B2 (en) 1986-06-19

Family

ID=14962189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12752676A Granted JPS5352063A (en) 1976-10-22 1976-10-22 Production of pn junction semiconductor unit

Country Status (1)

Country Link
JP (1) JPS5352063A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58168256A (en) * 1982-03-30 1983-10-04 Fujitsu Ltd Semiconductor device
US4745446A (en) * 1985-02-11 1988-05-17 American Telephone And Telegraph Company, At&T Bell Laboratories Photodetector and amplifier integration

Also Published As

Publication number Publication date
JPS5352063A (en) 1978-05-12

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