JPH0645644A - Si light-emitting device and its manufacture - Google Patents

Abstract

PURPOSE:To realize an Si light-emitting device which is provided with a new constitution by a method wherein a porous Si region as well as an n-type region and a p-type region which sandwich it are formed on an Si layer on an SOI substrate. CONSTITUTION:A p-type Si layer 3 is arranged on an Si support substrate 1 via an SiO2 film 2, an SOI substrate 4 is constituted, the Si support substrate 1 and the Si layer 3 are provided respectively with a (100) plane, silicon nitride is deposited on the whole surface, a stripe-shaped opening part 5 is formed in a prescribed position, and the SOI substrate 4 is immersed in an aqueous HF solution. Then, the p-type Si layer 3 is exposed in the opening part 5, Au is sputtered from the rear side of the Si support substrate 1, a back contact electrode 6 is formed, an anodic oxidation operation is executed, and a porous Si region 8 is formed. Then, a CVD Si or CVD SiC layer 10 is deposited on it, impurities are ion-implanted into regions on both sides of the porous Si region 8, an n-type region 12 and a p-type region 13 are formed, and, thereby, a pin diode structure provided with a light-emitting region can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a silicon light emitting device. In recent years, attempts have been made to artificially process silicon having an indirect transition type band structure to realize a pseudo direct transition type band structure and obtain light emission in the visible region. As a method of changing the band structure of silicon, a method of using a Si / Ge superlattice structure, a method of ultrafine processing of silicon to a size at which a quantum effect appears, and the like have been proposed.

In particular, as a simple method for miniaturizing silicon, a silicon layer is anodized to increase the porosity, thereby forming a porous Si region having a quantum wire structure and emitting light from the porous Si region. The method has been reported.

[0003]

2. Description of the Related Art When silicon is made into a quantum wire and its photoluminescence is measured, visible light emission is obtained at room temperature. The wavelength of visible light varies depending on the size of the quantum wire, and the emission from the green visible region to the near infrared region can be measured.

This phenomenon is considered to be due to the fact that by limiting the size of the silicon region, subbands are formed in the silicon region and a pseudo direct transition occurs between the bands.

[0005] The well width of the potential is a, band spacing E for performing recombination _{^{transition, (h 2 / 4m e *}} d 2
+ According to the _{^{h 2 / 4m h * d 2}} ). If the well width d is narrowed, the emission wavelength is shortened. Here, h is Planck's constant, and m _e ^* and m _h ^* are effective masses of electrons and holes, respectively. When the silicon region is miniaturized to a size of about 5 nm or less, such a quantum effect causes a light emission phenomenon.

As a method of making the silicon region ultra-fine, there is also a method of making the powder fine, but since the fine powder is accompanied by processing strain, the luminous efficiency becomes low. Further, it is difficult to inject the carrier into the fine powder.

As a method for making the silicon region ultra-fine,
There is a method to make the silicon region porous by anodic oxidation as announced by Kanham (LTCanham, Appl.Phy.
S. Lett., 57 (10), (1990) 1046).

The anodic oxidation is carried out by immersing a Si wafer having an electrode on the back surface in an HF aqueous solution, and connecting a DC power supply between the Si wafer and the counter metal electrode which is similarly immersed in the HF aqueous solution.

At this time, if the Si wafer serves as an anode and the counter metal electrode serves as a cathode, anodization occurs on the surface of the Si wafer. The oxide film immediately dissolves in the HF aqueous solution. The presence of holes is necessary for this anodization. Therefore, p-type Si is used or the Si wafer is irradiated with light to generate electron-hole pairs.

The surface of the Si wafer is etched by anodic oxidation in an HF aqueous solution, and fine pits are locally generated where the etching rate is high. Once the depression is generated, the electric field is concentrated in this region, so that holes are supplied from the inside of the bulk, and the etching selectively progresses. Since the electric field concentrates on the bottom portion of the recess having a large curvature, the etching hole does not spread so much in the side surface direction but progresses almost in the depth direction.

In this way, a porous region is formed on the surface of the Si wafer. The porosity is determined by the HF concentration in the HF aqueous solution, the energization amount, the carrier concentration, and the like. If the porosity exceeds 50%, the holes will be connected to each other,
A fine line-shaped Si fine column group is generated. In this way, a Si quantum wire having a diameter of 5 nm or less, which exhibits a quantum effect, can be obtained.

The area of the Si quantum wire region formed by such a method can be easily controlled by the area of the anode electrode. Therefore, compared to a Si / Ge superlattice structure or the like, the Si quantum wire region can be easily created.

[0013]

DISCLOSURE OF THE INVENTION The present inventors first found that S
We proposed a Si light-emitting device utilizing the i-quantum wire region (Japanese Patent Application No. 4-138074).

In order to satisfy various conditions required for the light emitting device, various types of Si light emitting devices are desired. For example, a Si light emitting device capable of integrating a plurality of electrically separated Si light emitting elements on the same substrate is desired.

The object of the present invention is to provide Si having a novel structure.
A light emitting device is provided.

[0016]

A Si light emitting device of the present invention is an SOI substrate in which a Si layer, an insulating layer and a supporting substrate are laminated, and an opening is formed in the supporting substrate and the insulating layer on a predetermined region of the Si layer. An SOI substrate in which the Si layer is formed, a porous Si region formed in a predetermined region of the Si layer, an n-type region formed adjacent to the predetermined region of the Si layer, and a predetermined region of the Si layer. And includes a p-type region formed opposite to the n-type region.

[0017]

Function: A porous Si region is formed on the Si layer of the SOI substrate.
Since the n-type region and the p-type region sandwiching this porous Si region are formed, a lateral type diode structure is formed. Both the anode and cathode regions of the diode are exposed.

This lateral diode structure is
If separated on the substrate, an electrically isolated Si light emitting element can be obtained.

[0019]

EXAMPLE FIG. 1 shows main steps of a method for manufacturing a Si light emitting device according to an example of the present invention. First, as shown in FIG. 1A, an SOI substrate is prepared. The p-type Si layer 3 is arranged on the Si support substrate 1 with the SiO ₂ film 2 interposed therebetween,
The SOI substrate 4 is configured.

The Si support substrate 1 has, for example, a thickness of 500 to
It is a normal Si wafer having a thickness of about 700 μm, and the SiO ₂ film 2 is a thermal oxide film having a thickness of, for example, about 1 μm. The p-type Si layer 3 is, for example, a layer having a thickness of about 2 μm.

Such an SOI substrate can be manufactured by the following method. Two Si wafers are prepared, and at least one surface thereof is subjected to thermal oxidation to remove S.
An iO ₂ film is formed. Overlay two Si wafers,
When kept at a high temperature of 900 to 1000 ° C, two S
The i-wafer is bonded.

If pressure or voltage is applied between the two Si wafers while maintaining the temperature at high temperature, the adhesiveness is further improved. A CVD oxide film may be used instead of the thermal oxide film. If PSG or BPSG is used, the bonding temperature can be further lowered.

It should be noted that after the bonding, S for forming a semiconductor element should be formed.
The i-wafer is preferably polished to the desired thickness.
For example, when an epitaxial layer having a low impurity concentration is formed on a Si substrate heavily doped with impurities and another Si wafer is bonded to this epitaxial layer, etching is controlled by the difference in the impurity concentration and only the epitaxial layer is formed. You can leave.

In addition, various known techniques such as chemical etching and mechanical polishing can be used. Note that Si
Both the support substrate 1 and the Si layer 3 have a (100) plane.

Silicon nitride is deposited on the entire surface of the p-type Si layer 3 and the Si supporting substrate 1. A photoresist film is applied on the silicon nitride film on the Si support substrate 1, and a stripe shape (or a rectangle) is formed at a predetermined position by using photolithography.
Forming an opening. Using the remaining photoresist film as a mask, stripe-shaped openings are formed in the silicon nitride film.

The SOI substrate is dipped in a KOH aqueous solution and anisotropically etched to form an opening 5 in the Si supporting substrate 1 as shown in FIG. 1 (B). In addition, K
The etching rate by the OH aqueous solution is large in the <100> direction, and the etching proceeds until the SiO ₂ film 2 is exposed.

Next, when the SOI substrate 4 is immersed in an HF aqueous solution, the silicon nitride film on the surface and the exposed SiO 2 are exposed.
_{2 The} film 2 is etched and removed. Therefore, the p-type Si layer is exposed at the opening 5.

Next, Au is sputtered from the back side of the Si support substrate 1 to form the back contact electrode 6 on the surface including the opening 5. This state is shown in FIG. The mask size is set so that the width of the stripe region where the back contact electrode 6 contacts the p-type Si layer is, for example, about 1 μm.

Next, the back contact electrode 6 is connected to the anode of the DC power source, the electrode of platinum, gold or the like is connected to the cathode of the DC power source, and anodization is performed in a hydrofluoric acid aqueous solution. For example,
When the SOI substrate 4 is immersed in a 40% HF aqueous solution and anodized at a current density of 20 to 100 mA / cm ² , the opposite surface of the p-type Si layer 3 in contact with the back contact electrode 6 is anodized. Is etched.

In this etching, when irregularities are generated on the surface, the etching selectively proceeds in the concave portions, and p-type Si
A large number of holes are formed on the surface of the layer 3. When the adjacent holes are connected to each other, the remaining Si region has a thin line shape. Diameter 5
A thin line region having a thickness of 10 nm and a depth of about 1.5 μm is formed and anodic oxidation is completed.

In this way, the porous Si region 8 is formed on the surface of the p-type Si layer 3. In addition, the anodic oxidation is as shown in FIG.
It may be performed halfway through the p-type Si layer 3 as shown in (C), or until it reaches the SiO ₂ film 2. Figure 2
Shows an enlarged schematic view of the portion of the porous Si region 8.

Next, the SOI substrate 4 is washed and dried, and
Dry oxidation is performed in ₂ atmospheres to form a Si oxide film 9 of about 2 to 5 nm on the surface as shown in FIG. Next, SO
The I substrate 4 is placed in a low pressure vapor deposition (LPCVD) apparatus, and Si source gas such as SiH ₄ or Si ₂ H ₆ and H
₂ Gas is flowed, and the Si oxide film 9
Amorphous or polycrystalline Si is deposited thereon to form a CVD Si layer 10.

The gaps in the porous Si region are at least partially backfilled by this CVD Si layer 10, and the porous Si region increases the physical strength. CVD
CVDSiC may be used instead of Si.

FIGS. 1C and 2 show a state in which the CVDSi or CVDSiC layer 10 is deposited on the surface of the p-type Si layer 3, but in FIG. 1C, the Si oxide film 9 is formed.
Are not shown.

The Si oxide film 9 is formed on the entire surface of the p-type Si layer 3, and the CVD is performed on the Si oxide film 9 including the gaps between the Si thin wires.
A Si or CVD SiC layer 10 is deposited. It should be noted that the gap between the Si thin wires is completely CVDSi or CV.
The state of being backfilled with the DSiC layer 10 is shown.
The Si or CVD SiC layer 10 may partially fill the gaps between the Si thin wires.

Next, as shown in FIG. 1D, impurities are selectively ion-implanted into regions on both sides of the porous Si region 8 to form an n-type region 12 and a p-type region 13. afterwards,
The back contact electrode 6 is removed. In this way
A Si pin diode structure having a light emitting function is formed.

FIG. 3 shows the structure of a Si light emitting device which can be manufactured by using such a manufacturing method. Figure 3
3A shows a cross-sectional view, and FIG. 3B shows a plan view. Similar to the SOI substrate 4 shown in FIG. 1D, an n-type Si region 12 and a p-type Si region 13 are formed on the Si support substrate 1 having the opening 5 formed therein, with the SiO ₂ film 2 interposed therebetween, and the porous region is formed between them. A Si region 8 is formed.

Si layers 8, 12, 13 including these regions
Si oxide film 9, CVDSi or CVDSi on the surface
The C layer 10 is formed, an opening is formed on a predetermined region of the n-type region 12 and the p-type region 13, and an n-side electrode 22,
A p-side electrode 23 is formed. The n-side electrode 22,
A reverse bias DC power supply 26 and a switch 27 are connected between the p-side electrodes 23.

As shown in the plan view of FIG. 3B,
The Si layer in the region surrounding the diode structure is removed and the diode structure is electrically isolated. Although the case where one diode structure is formed on the supporting substrate 1 is illustrated, a desired number of diode structures can be formed on the Si supporting substrate 1.

Such a diode structure has an n-type region 1
2. A large number of Si thin wires are surrounded by the Si oxide film and distributed between the p-type regions 13 to form a pin or pπn diode.

When a reverse bias voltage is applied to such a diode, the applied voltage is mainly applied to the porous Si region 8 which is a high resistance region. If the electric field strength is sufficiently high, avalanche breakdown occurs in the porous Si region 8 and many electron-hole pairs are generated. Of course, light emission is observed even with forward bias.

When these electron-hole pairs are recombined in the Si thin wire, light emission corresponding to the size of the Si thin wire occurs. The effective size of the Si thin wire is determined by the band structure shaped by the oxide film on the surface and the depletion layer adjacent to the oxide film. The quantum effect can be exhibited by the oxide film and the depletion layer without making the dimensions of the thin wire very small.

FIG. 4 shows main steps of a method for manufacturing a Si light emitting device according to another embodiment of the present invention. Similar to the above-described embodiment, the opening 5 is formed in the Si support substrate 1, and the Al back contact electrode 16 formed of Al, which is a metal that is easily oxidized, is formed to cover the opening.

After that, the surface of the p-type Si layer 3 is brought into contact with the aqueous solution of hydrofluoric acid 15 in a state where the Al back contact electrode 16 is isolated, and anodization is performed. P-type Si layer 3 in a region in contact with the Al back contact electrode 16 by anodic oxidation
A porous Si region 8 is formed on the surface. In the case of this embodiment, the anodization is stopped before the anodization hole penetrates the p-type Si layer 3.

After that, as shown in FIG. 4B, p-type S
The surface of the i layer 3 is oxidized, and at the same time, the Al back contact electrode 16 formed on the opening surface of the support substrate 1 is oxidized to be converted into an alumina layer 16a. At least in the opening, the alumina layer 16a reaches the p-type Si layer 3 completely.

After that, as in the above-mentioned embodiment, the Si oxide film 9 is formed.
CVDSi or C is formed on the surface of the p-type Si layer 3 on which
The VDSiC layer 10 is deposited and the pores of the porous Si region 8 are backfilled. According to this structure, it is not necessary to remove the back contact electrode converted into the alumina layer 16a.

A metal electrode may be formed on the surface of the alumina layer 16a and used as a control electrode. Also,
After anodizing the p-type Si layer 3, the Si oxide film 9 and CVD
It is also possible to form the diode structure as it is without forming the Si or CVD SiC layer 10 and cause the porous Si region 8 to emit light.

As an SOI substrate, S is formed on a Si wafer.
The case of using the one having the Si layer sandwiched between the iO ₂ films has been described, but the SOI substrate may have another structure as long as it has the Si layer on the insulator. It is also possible to use a conductive material other than Si for the n-type region and the p-type region.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various changes, improvements, combinations and the like can be made.

[0050]

As described above, according to the present invention,
A Si diode structure having a light emitting function can be formed laterally on the support substrate.

Therefore, it is easy to form a large number of lateral light emitting Si diodes on the same supporting substrate in an electrically separated state.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing main steps of a method for manufacturing a Si light emitting device according to an embodiment of the present invention.

FIG. 2 is a partially enlarged cross-sectional view of the configuration shown in FIG.

FIG. 3 is a diagram showing a Si light emitting device according to an embodiment of the present invention. 3A is a cross-sectional view and FIG. 3B is a plan view.

FIG. 4 is a cross-sectional view showing the main steps of a method for manufacturing a Si light emitting device according to another embodiment of the present invention.

[Explanation of symbols]

1 Si supporting substrate 2 SiO ₂ film 3 p-type Si layer 4 SOI substrate 5 opening 6 back contact electrode 8 porous Si region (Si thin line) 9 Si oxide film 10 CVDSi layer 12 n-type region 13 p-type region 15 hydrofluoric acid solution 16 Al back contact electrode 16a Alumina layer 26 Reverse bias power supply 27 Switch

Claims (7)

[Claims] 1. An SOI substrate in which a Si layer (3), an insulating layer (2), and a supporting substrate (1) are laminated, and an opening is formed in the supporting substrate and the insulating layer on a predetermined region of the Si layer (3). An SOI substrate (4) having (5) formed therein, a porous Si region (8) formed in a predetermined region of the Si layer, and an n-type region (adjacent to the predetermined region of the Si layer ( 12) and adjacent to the predetermined region of the Si layer, the n-type region (1
S including a p-type region (13) formed opposite to 2)
i light emitting device. 2. The Si according to claim 1, further comprising a Si oxide film (9) formed on the surface of the porous Si region and a CVD Si or CVD SiC layer (10) formed on the Si oxide film. Light emitting device. 3. The Si light emitting device according to claim 1, further comprising a metal oxide layer (16a) formed on the opening (5) of the SOI substrate (4). 4. An SOI substrate (4) in which a Si layer (3), an insulating layer (2) and a supporting substrate (1) are laminated is prepared, and an opening (5) reaching the Si layer from the supporting substrate (1) side. Forming a back contact electrode (6, 16) on the opening (5)
And a step of forming a porous Si layer by anodizing the Si layer in an aqueous solution of hydrofluoric acid.
Forming a region (8), and n-type region (1
2) and a method for manufacturing a Si light emitting device, which includes the step of forming a p-type region (13). 5. Further, after the step of forming the porous Si region, a step of thermally oxidizing the surface of the Si layer (3) to form a Si oxide film (9), and Si on the Si oxide film (9). 5. The method for manufacturing a Si light emitting device according to claim 4, further comprising the step of: 6. The back contact electrode (6) is a metal that withstands a hydrofluoric acid aqueous solution, and the porous Si region forming step is performed by immersing the SOI substrate (4) in a hydrofluoric acid aqueous solution to reduce the pressure of the Si. The method for manufacturing a Si light emitting device according to claim 5, further comprising a step of removing the back contact electrode (6) after the vapor deposition step. 7. The back contact electrode (16) is a metal that is easily oxidized, and the back contact electrode (16) is formed by a hydrofluoric acid solution (1) in the step of forming the porous Si region.
5) without touching the insulating layer (16a) by oxidizing the back contact electrode (16) after the step of forming the porous Si region.
The method for manufacturing a Si light-emitting device according to claim 5, including a step of converting into Si.