JPH0834171B2 - Method for manufacturing semiconductor device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device obtained by directly adhering two semiconductor substrates.

[Technical background of the invention and its problems]

The present inventors have made it possible to directly bond two semiconductor substrates to one
We have previously proposed a technology for obtaining a single semiconductor wafer. When the polished surfaces of two mirror-polished semiconductor substrates are brought into contact with each other in a clean atmosphere with virtually no foreign matter present, they strongly adhere and are extremely strong when heat-treated at 200 ° C, preferably 1000 ° C or higher. The semiconductor wafer integrated with the above is obtained. With this direct bonding technology,
A wafer having an excellent bonded portion equivalent to that of a conventional epitaxial wafer or a wafer that cannot be obtained by the epitaxial method can be obtained very easily. In fact, the present inventors have confirmed that this technique can be applied to various semiconductor devices to obtain great results.

[Object of the Invention]

The present invention is a development of the direct bonding technique described above,
It is an object of the present invention to provide a method for manufacturing a semiconductor device that enables new device applications.

[Outline of Invention]

A method of manufacturing a semiconductor device according to the present invention is based on the above-described direct bonding technique, and is characterized in that mirror-polished surfaces to be bonded are intentionally bonded in a crystal lattice mismatched state.

In the method of manufacturing a semiconductor device according to the present invention, a very thin amorphous layer is formed at the bonding interface. This is the first time that the present inventors have found this time, and the present invention intends to positively apply a wafer in which an amorphous layer is interposed as described above to a device.

〔The invention's effect〕

According to the present invention, for example, one of the semiconductor substrates to be integrated is p-type, the other is n-type, and the amorphous layer at the bonding interface of the obtained wafer is used as a tunnel insulating film to realize carrier injection characteristics similar to those of a heterojunction. can do. That is, the tunnel probability of the insulating film is determined by the height and thickness of the barrier, but as is well known, the tunnel probability differs between electrons and holes. Therefore, when a p-type substrate and an n-type substrate are integrated and a tunnel insulating film is provided at the interface, the hole injection efficiency from the p-type layer to the n-type layer and the electron injection efficiency from the n-type layer to the p-type layer are different. It becomes a value. If a bipolar transistor is formed by using this pn junction as an emitter-base junction, for example, a high current amplification factor can be obtained by the same principle as that of the heterojunction transistor. Since the heterojunction is a junction of heterogeneous semiconductors, it is very difficult to form an ideal heterojunction without defects and the like even with the progress of crystal growth technology. A bonded wafer having the same function as bonding can be obtained.

Further, the method for manufacturing a semiconductor device according to the present invention can be applied to various elements by utilizing the amorphous layer formed at the bonding interface for impurity gettering.

Example of Invention

 Examples of the present invention will be described below.

1 (a) to 1 (c) are sectional views of manufacturing steps of an embodiment in which the present invention is applied to a transistor. As shown in (a), the first Si substrate 1 having the plane orientation (100) and the plane orientation (111)
The second Si substrate 2 is prepared. The first Si substrate 1 is an n ⁺ type layer
1 _1, n ^- a three-layer structure type layer 1 _2, p-type layer 1 _3, second Si substrate 2 is a n ⁺ -type layer. The surfaces to be bonded of these two substrates are mirror-polished to have a surface roughness of 50 Å or less.
The polished surface is cleaned by degreasing with trichlene → surface treatment with a mixed solution of hydrogen peroxide and sulfuric acid → aqua regia treatment and water washing → natural oxide film removal by dipping in dilute hydrofluoric acid → water washing and drying. The polishing surfaces are brought into contact with each other in a clean atmosphere of class 2 or less without substantially interposing foreign matter, and heat-treated at 1100 ° C. for 1 hour to be integrated as shown in (b). 30 Å on the bonding interface 3 between the two substrates, as will be described later.
An amorphous layer is formed to some extent. Using the npn wafer thus obtained, for example, the thickness of the second substrate 2 side is adjusted by lapping or the like and processed into a predetermined pattern, and then the emitter electrode 4 and the base electrode 5 are formed as shown in (c).
And the collector electrode 6 is formed to complete the transistor.

In the transistor according to this embodiment, an extremely thin amorphous layer is formed on the bonding interface 3 which becomes the emitter-base junction. This amorphous layer is semi-insulating,
Since it is extremely thin, it can be almost ignored as a resistance component, and it works as a tunnel insulating film. That is, the efficiency of electron injection from the emitter to the base is higher than the efficiency of hole injection from the base to the emitter. Therefore, a high current amplification factor can be obtained by the same principle as that of the heterojunction transistor.

FIG. 2 is a transmission electron micrograph of the bonding interface of the integrated wafer of FIG. 1 (b). As is clear from this photograph, it is clear that an amorphous layer of about 30Å is formed at the adhesive interface.

FIGS. 3A to 3C are cross-sectional views showing a transistor manufacturing process of another embodiment. The basic method is the same as that of the previous embodiment. Therefore, the parts corresponding to those in FIG. 1 are designated by the same reference numerals as those in FIG. 1 and their detailed description is omitted. In this embodiment, the recess 7 is formed in advance on the mirror-polished surface of the second substrate 2 in order to facilitate the extraction of the base electrode. Using such a substrate, an integrated wafer is formed as shown in (b) in the same process as in the previous embodiment, and the integrated wafer is lapped to selectively form the substrate 2 in the emitter region as shown in (c). leaving only to expose the p-type layer 1 ₃ as a base. Then, predetermined electrodes are formed to complete the transistor.

Also in this embodiment, the same effect as the previous embodiment can be obtained.

The present invention is not limited to the above embodiment. In the above embodiment,
A combination of a (100) plane Si substrate and a (111) plane Si substrate,
An amorphous layer was formed at the bonding interface by bonding two substrates with different plane orientations. The point is that if mirror-polished surfaces are bonded together in a crystal lattice mismatched state, a similar interface state can be obtained. To be For example, even if the two substrates have the same plane orientation, the same interface state can be obtained by adhering them in a state in which the corresponding crystal axis orientations are deviated from each other. In the embodiment, two substrates having different conductivity types are used and applied to an element that utilizes the difference in tunnel probability between electrons and holes in the tunnel insulating film. Also, the present invention is effective. In that case, the amorphous layer formed at the bonding interface is effectively used as a layer for performing impurity gettering, for example. Further, although the Si substrate is used in the embodiment, the present invention can be similarly applied to the case of using another semiconductor substrate such as GaAs and InP.

[Brief description of drawings]

1 (a) to 1 (c) are views showing a transistor manufacturing process of one embodiment of the present invention, FIG. 2 is a transmission electron micrograph showing a crystal structure of a wafer bonding interface portion, and FIG. 3 (a). )
8A to 8C are diagrams showing a transistor manufacturing process of another embodiment. 1 …… (100) Si substrate, 2 …… (111) Si substrate, 3 …… adhesive interface.

Claims (4)

[Claims] 1. A mirror-polished surface of two semiconductor substrates is intentionally brought into contact with each other in a state of crystal lattice mismatching under a clean atmosphere and heat-treated to be integrated to form an adhesive interface between the mirror-polished surfaces. A method of manufacturing a semiconductor device, which comprises forming an extremely thin layer in an amorphous state. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the mirror-polished surfaces of the two semiconductor substrates are made different in plane orientation to obtain a crystal lattice mismatch state. 3. A crystal lattice mismatch state is obtained by making the mirror-polished surfaces of the two semiconductor substrates have the same plane orientation and shifting the corresponding crystal axis orientations in the planes so as to overlap each other. A method of manufacturing a semiconductor device according to claim 1. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the two semiconductor substrates are different in at least the conductivity type of a bonding portion.