JPS61259550A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPS61259550A
JPS61259550A JP60100575A JP10057585A JPS61259550A JP S61259550 A JPS61259550 A JP S61259550A JP 60100575 A JP60100575 A JP 60100575A JP 10057585 A JP10057585 A JP 10057585A JP S61259550 A JPS61259550 A JP S61259550A
Authority
JP
Japan
Prior art keywords
resin
metal plate
lead frame
plate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60100575A
Other languages
Japanese (ja)
Inventor
Takao Emoto
江本 孝朗
Hiroshi Matsumoto
博 松本
Toshihiro Kato
加藤 俊博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60100575A priority Critical patent/JPS61259550A/en
Publication of JPS61259550A publication Critical patent/JPS61259550A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Abstract

PURPOSE:To average thermal characteristics by uniformly maintaining the thickness of a sealing resin layer between a lead frame and a metal plate. CONSTITUTION:Only one surface of a metal plate 6 is bent to obtain the prescribed curvature by pressing step of differentiate the thicknesses of the center and the ends. A lead frame 1 associated with a semiconductor element 5 and a metal plate 6 finished for the bending step are integrated by a transferring step. To increase thermal conductivity, the element 5 is sealed with resin by the thermal curing reaction of the silicone resin added with a filler. In this case, the straight surface 9 of the plate 6 is bent in the same direction as the frame 1. As a result, the bent surface 8 of the plate 6 is straightened. Thus, the thickness of sealing resin 7 disposed between the frame 1 and the bent surface of the plate 6 is formed substantially the same to average the thermal characteristics.

Description

【発明の詳細な説明】 (発明の技術分野〕 本発明はヒートシンクをもったアイソレイション型樹脂
封止半導体装置に係り、特にパワトランジスタ等の電力
用素子で作られる複合素子に好適する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an isolation type resin-sealed semiconductor device having a heat sink, and is particularly suitable for a composite element made of power elements such as a power transistor.

〔発明の技術的背景〕[Technical background of the invention]

従来から個別半導体素子例えばパワトランジスタ等の電
力用素子ではそのコレクタ端子を共通にする方式と、複
数のコレクタ端子を別個に利用する方式に大別され、こ
の後者をアイソレイション型と呼ばれている。
Conventionally, individual semiconductor devices, such as power transistors and other power devices, have been roughly divided into two types: those that use a common collector terminal, and those that use multiple collector terminals separately, the latter being called the isolation type. .

その断面構造図を第4図(A)に示すと、パワトランジ
スタ等が形成された半導体素子(11)はリードフレー
ム(12)O図示しないベット部にPb−5n系半田セ
固着後、この半導体素子(11)に設けた電極とリード
フレームの外部端子とをワイヤボンディング工程により
電気的に導通可能にする。これらの組立体を一般にヒー
トシンクと呼ばれる金属板(13)に固定しこれらを封
止樹脂層(14)で被覆するが、この金属板(13)と
リードフレーム(12)間に封止樹脂層(14)を設け
てアイソレイション型樹脂封止半導体装置を製造してき
た。前述のワイヤボンディング工程は導電性金属細線を
所定の部品間に橋絡して完了するが、この細線にゲル状
又はゴム状の樹脂を被覆して汚染乃至歪除去を図る場合
もある。
The cross-sectional structural diagram is shown in FIG. 4(A). After the semiconductor element (11) on which the power transistor etc. are formed is fixed to the bed part (not shown) of the lead frame (12) with Pb-5n solder, the semiconductor The electrode provided on the element (11) and the external terminal of the lead frame are made electrically conductive by a wire bonding process. These assemblies are fixed to a metal plate (13) generally called a heat sink and covered with a sealing resin layer (14). 14) to manufacture isolation type resin-sealed semiconductor devices. The wire bonding process described above is completed by bridging a conductive metal thin wire between predetermined parts, but this thin wire may be coated with a gel-like or rubber-like resin to remove contamination or distortion.

このような構造にあっては金属板(13)と成形樹脂(
1・4)の熱膨張係数(α)の相違や、樹脂の成形収縮
率等により製品に反りが発生する。この反り量(W)は
略 Wω(α□−α2)AT   T:温度で表わされ、α
は樹脂20〜25 X 10−’℃−1に対しCu 1
6.5 X 10−’℃−1,Fe 11.8X10−
6℃−1123,6x io−’℃−1であり、更に樹
脂(14)の成形収縮率は約0.5〜0.9%である。
In such a structure, the metal plate (13) and the molded resin (
Warpage occurs in the product due to differences in thermal expansion coefficients (α) (1 and 4), molding shrinkage rate of the resin, etc. This amount of warpage (W) is approximately Wω(α□−α2)AT T: temperature, α
is Cu 1 for resin 20-25 x 10-'℃-1
6.5 X 10-'℃-1, Fe 11.8X10-
6°C-1123,6x io-'°C-1, and the molding shrinkage rate of the resin (14) is about 0.5-0.9%.

金属板(13)は通常1又は1合金が使用され、半導体
装置全体の寸法が60 X 20xt6mn[この白金
属板(13)の厚さは2mm)の反り量は約0.15m
nとなる。しかし、パワトランジスタでは放熱部品へ孔
(16)を利用したビス止め(M310kg/an)に
より樹脂クランクや剥れを起して実用に到らなかった。
The metal plate (13) is usually made of 1 or 1 alloy, and the overall dimensions of the semiconductor device are 60 x 20 x 6 mm [the thickness of this white metal plate (13) is 2 mm], and the amount of warpage is approximately 0.15 m.
It becomes n. However, in the case of power transistors, the use of screws (M310 kg/an) using holes (16) for heat dissipating components caused resin cranking and peeling, and it could not be put to practical use.

そこで、この欠点を補うために考えられたのが、第4図
(b)に示した方式である。即ち、金属板(13)を反
り量に合せて、予めその反り方向と反対方向に弯曲させ
る方法であるが、これによると反り量が最大0.03m
nに抑えられ樹脂クラック等も起らず実用に供し得る製
品が得られた。
Therefore, the method shown in FIG. 4(b) was devised to compensate for this drawback. That is, the metal plate (13) is curved in advance in a direction opposite to the warp direction according to the amount of warp, but according to this method, the amount of warp is at most 0.03 m.
A product which could be used for practical purposes was obtained, with n being kept in check and no resin cracks occurring.

一方、金属板(13)の弯曲工程と同一の曲率半径でリ
ードフレーム(12)を弯曲させる手法も考えられるが
、その実施時期がダイボンディング工程前ではこれが困
難となり、この工程後では固着した半導体素子やワイヤ
ポンディングされた導電性金属細線を破損する恐れがあ
り何れも実用的でない。
On the other hand, a method of bending the lead frame (12) with the same curvature radius as the bending process of the metal plate (13) may be considered, but this would be difficult if carried out before the die bonding process; Both methods are impractical because they may damage the device or wire-bonded conductive thin metal wire.

〔背景技術の問題点〕[Problems with background technology]

ところで、樹脂封止型半導体装置の飽和熱抵抗[Rth
(j−c))は半導体素子(11)、リードフレーム(
12)、封止樹脂(14)、金属板(13)に至るまで
の熱伝導系各々の熱抵抗の和であり、熱伝導率(λ)は
シリコン〜0.2.半田〜0.08. Cu層0.94
゜樹脂〜1〜6xlO−”、AQ〜0.27(単位Ca
(1/cn−sec・’C)であり、アイソレイション
型樹脂封止半導体装置の熱抵抗は金属板(13)とリー
ドフレーム(12)間に位置する封止樹脂の厚さによっ
て決まる。
By the way, the saturated thermal resistance [Rth
(j-c)) is a semiconductor element (11), a lead frame (
12) is the sum of the thermal resistances of each of the thermal conductive systems up to the sealing resin (14) and the metal plate (13), and the thermal conductivity (λ) is from silicon to 0.2. Solder~0.08. Cu layer 0.94
゜Resin~1~6xlO-'', AQ~0.27 (unit Ca
(1/cn-sec·'C), and the thermal resistance of the isolation type resin-sealed semiconductor device is determined by the thickness of the sealing resin located between the metal plate (13) and the lead frame (12).

前記アイソレイション型樹脂封止半導体素子は、第4図
(b)に示すようにリードフレーム(12)と金属板(
13)間に位置する樹脂層(14)の厚みが部分的に異
なるために熱抵抗特性に差があることが判明した。この
装置では金属板(13)に反り対策のためElfロブ加
工が施されており、より薄い厚さをもつリードフレーム
(12)が反り、その端から中央部分に向って漸次樹脂
層(14)が薄くなる。
As shown in FIG. 4(b), the isolation type resin-sealed semiconductor element includes a lead frame (12) and a metal plate (
13) It has been found that there are differences in heat resistance characteristics because the thickness of the resin layer (14) located between the two is partially different. In this device, the metal plate (13) is subjected to Elf lobe processing to prevent warping, and the thinner lead frame (12) is warped, and the resin layer (14) is gradually formed from the edge toward the center. becomes thinner.

[発明の目的] 本発明は上記欠点を除去した新規なアイソレイション型
樹脂封止半導体装置を提供するもので。
[Object of the Invention] The present invention provides a novel isolation type resin-sealed semiconductor device that eliminates the above-mentioned drawbacks.

特にリードフレームと金属板間に配置する封止樹脂層の
厚さを均一に維持すると共に、金属板露出表面の平坦度
を保持して熱特性を平均化することを目的とする。
In particular, the purpose is to maintain a uniform thickness of the sealing resin layer disposed between the lead frame and the metal plate, and to maintain the flatness of the exposed surface of the metal plate to even out the thermal characteristics.

〔発明の概要〕[Summary of the invention]

この目的を達成するため、本発明に係るアイソレイショ
ン型樹脂封止半導体装置では金属板の樹脂接触面だけに
樹脂成型時に発生する反り量に見合う一率半径を持って
弯曲させて、より薄いリードフレーム面と平行関係を保
たせ両部品間に位置する封止樹脂厚さを一定とする手法
を採用した。
In order to achieve this objective, in the isolation type resin-sealed semiconductor device according to the present invention, only the resin contacting surface of the metal plate is curved with a uniform radius commensurate with the amount of warpage that occurs during resin molding, thereby making the leads thinner. A method was adopted in which the thickness of the sealing resin located between both parts was kept constant while maintaining parallel relationship with the frame surface.

〔発明の実施例〕[Embodiments of the invention]

第1図(A) (B)により本発明を詳述する。 The present invention will be explained in detail with reference to FIGS. 1(A) and 1(B).

Fe、 FeNi合金、Aρ又は最外層にCu層をもつ
り−ドフレームを準備する。このリードフレーム中は例
えば第2図にその要部が示されるように、トランジスタ
の3電極に対応する端子を形成するため端部に膨大部■
・・・■・・・を形成する金属細条(イ)・・・を規則
正く林立し、共通端子0をこれらの膨大部■・・・■・
・・を囲むように配置し、更に金属細条(イ)・・・を
いわゆるタイバーで連結する。この膨大部■・・・には
パワトランジスタ等の半導体素子0をPb −Sn系半
田で固着する。一方Afi製金属板0はその一表面だけ
をプレス工程により一定の曲率が得られるように弯曲さ
せて、その中央部分の厚さと端部の厚さの相違を約0.
1mm とし、このAQM金属金属板後述の樹脂封止工
程を施す際にはこの弯曲面■を怖止樹脂と非接触即ち外
側とし、これの反対側を占める真直ぐな面0をリードフ
レームと対向させる。
A suspended frame made of Fe, FeNi alloy, Aρ, or a Cu layer as the outermost layer is prepared. As shown in FIG. 2, for example, this lead frame has a large part at the end to form terminals corresponding to the three electrodes of the transistor.
The metal strips (A) that form...■... are arranged in a regular forest, and the common terminal 0 is connected to a huge part of these ■...■...
... are arranged so as to surround them, and the metal strips (A) ... are further connected with so-called tie bars. A semiconductor element 0 such as a power transistor is fixed to this enlarged portion (1) using Pb--Sn solder. On the other hand, only one surface of the Afi metal plate 0 is curved to obtain a constant curvature through the pressing process, and the difference between the thickness of the center portion and the thickness of the end portions is approximately 0.
1 mm, and when this AQM metal plate is subjected to the resin sealing process described later, this curved surface (■) will not be in contact with the safety resin, that is, it will be on the outside, and the straight surface (0) occupying the opposite side of this will face the lead frame. .

次に半導体素子■を組立てたリードフレーム■とこの弯
曲工程を終た金属板0をトランスファ工程によって一体
化するために樹脂封止するが、この封止用樹脂としては
その熱伝導性を増すためにフィラーを添加したシリコン
樹脂を適用し、その手法は公知のトランスファモールド
工程を採用しこのシリコン樹脂溶融体を型に注入して実
施する。
Next, the lead frame ■ on which the semiconductor element ■ has been assembled and the metal plate 0 that has undergone this bending process are sealed with a resin in order to integrate them through a transfer process. A silicone resin to which a filler has been added is applied, and the process is carried out by employing a known transfer molding process and injecting this silicone resin melt into a mold.

このシリコン樹脂は熱硬化反応によって半導体素子0を
樹脂封止するが、この半導体素子0側の金属板0の真直
ぐな面0はこの樹脂封止工程でより薄い厚さをもつリー
ドフレーム■と同一方向に弯曲する。この結果、金属板
0の弯曲面(8)は真直ぐになる。
This silicone resin seals the semiconductor element 0 with the resin through a thermosetting reaction, but the straight surface 0 of the metal plate 0 on the side of the semiconductor element 0 is the same as the lead frame ■, which has a thinner thickness during this resin sealing process. curve in the direction As a result, the curved surface (8) of the metal plate 0 becomes straight.

この樹脂封止工程時の弯曲程度と前記プレス工程での弯
曲の程度とを同一にするのが最良であるが、はゾ同一に
することは可能であり、リードフレーム■と金属板■は
同心円状の円弧が最終的に得られる。
It is best to make the degree of curvature during this resin sealing process the same as the degree of curvature during the pressing process, but it is possible to make them the same, and the lead frame (■) and the metal plate (■) may be concentric circles. Finally, an arc of the shape is obtained.

この結果、リードフレーム■と金属板0の弯曲面間に位
置する封止樹脂ωの厚さははゾ同一に成形され、次に孔
0を利用したビス止めを10 kg /■のトルクによ
って実施してアイソレイション型樹脂封止半導体装置を
得た。
As a result, the thickness of the sealing resin ω located between the curved surface of the lead frame ■ and the metal plate 0 is molded to be the same, and then screws are secured using the hole 0 with a torque of 10 kg/■. An isolation type resin-sealed semiconductor device was obtained.

〔発明の効果〕〔Effect of the invention〕

このようなアイソレイション型樹脂封止半導体板の厚さ
は2W11)である従来例と同様に反り量最大0.03
mn以内に保持され、熱抵抗値の分布は第2図に示す結
果が得られた。
The thickness of such an isolation type resin-sealed semiconductor board is 2W11), and the maximum amount of warpage is 0.03 as in the conventional example.
The thermal resistance was maintained within 100 mn, and the distribution of thermal resistance values was as shown in FIG.

即ち、縦軸に熱抵抗(℃/W)を採り、横軸に第1.3
図に示した金属板の所定位置ABCDを採り、測定値分
布状態を示した。この内X印は従来のアイソレイション
型樹脂封止半導体装置を、0印は本発明に係るアイソレ
イション型樹脂封止半導体装置を示す。
In other words, the vertical axis shows the thermal resistance (°C/W), and the horizontal axis shows the 1.3
Predetermined positions ABCD of the metal plate shown in the figure were taken, and the measured value distribution state is shown. Among them, the X mark indicates a conventional isolation type resin-sealed semiconductor device, and the 0 mark indicates an isolation type resin-sealed semiconductor device according to the present invention.

この図から明確に判るように、本発明では各測定位置に
よる相違がみられないのに対して従来例では明らかな変
化が示されており理論的な考察を裏付ける結果を得た。
As clearly seen from this figure, in the present invention, no difference is observed depending on the measurement position, whereas in the conventional example, a clear change is shown, and the results support the theoretical consideration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)は本発明に係る実施例の要部断面図、第1
図(B)はその主要部の断面図、第2図はその上面図、
第3図はリードフレームの各部分における熱抵抗値を示
す特性図、第4図は従来装置の要部 8一 部所面図である。 1:リードフレーム  5:半導体素子6:金属板  
    7=封止樹脂 8:弯曲面
FIG. 1(A) is a sectional view of a main part of an embodiment according to the present invention;
Figure (B) is a sectional view of its main parts, Figure 2 is its top view,
FIG. 3 is a characteristic diagram showing the thermal resistance value in each part of the lead frame, and FIG. 4 is a partial sectional view of a main part 8 of the conventional device. 1: Lead frame 5: Semiconductor element 6: Metal plate
7 = Sealing resin 8: Curved surface

Claims (1)

【特許請求の範囲】[Claims] 板状リードフレームに半導体素子を固着する組立体周囲
を被覆する樹脂層をこのリードフレームより厚い金属板
に封止する半導体装置において、前記半導体素子側の前
記金属板表面のみを弯曲し、これに沿って配置する前記
リードフレーム間の樹脂厚をほゞ同一にすることを特徴
とする樹脂封止型半導体装置。
In a semiconductor device in which a resin layer covering the periphery of an assembly in which a semiconductor element is fixed to a plate-shaped lead frame is sealed in a metal plate thicker than the lead frame, only the surface of the metal plate on the side of the semiconductor element is curved; A resin-sealed semiconductor device characterized in that the resin thicknesses between the lead frames arranged along the lead frames are substantially the same.
JP60100575A 1985-05-14 1985-05-14 Resin-sealed semiconductor device Pending JPS61259550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60100575A JPS61259550A (en) 1985-05-14 1985-05-14 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60100575A JPS61259550A (en) 1985-05-14 1985-05-14 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS61259550A true JPS61259550A (en) 1986-11-17

Family

ID=14277694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60100575A Pending JPS61259550A (en) 1985-05-14 1985-05-14 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS61259550A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049977A (en) * 1989-07-18 1991-09-17 Kabushiki Kaisha Toshiba Plastic molded type semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049977A (en) * 1989-07-18 1991-09-17 Kabushiki Kaisha Toshiba Plastic molded type semiconductor device

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