JPS61259467A - Jumper chip - Google Patents
Jumper chipInfo
- Publication number
- JPS61259467A JPS61259467A JP10068785A JP10068785A JPS61259467A JP S61259467 A JPS61259467 A JP S61259467A JP 10068785 A JP10068785 A JP 10068785A JP 10068785 A JP10068785 A JP 10068785A JP S61259467 A JPS61259467 A JP S61259467A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- pattern
- insulator
- jumper chip
- jumper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概要〕
回路基板の立体交叉するパターン部分に使用するジャン
パーチップであって、絶縁体内に内部導体と外部導体と
を設けて同軸構造にすることにより、交叉するパターン
とシールド可能とする。[Detailed Description of the Invention] [Summary] A jumper chip used for the three-dimensionally intersecting pattern portion of a circuit board, which has an inner conductor and an outer conductor inside an insulator to form a coaxial structure. Enables shielding.
本発明は、立体交叉するパターン部分に使用す、るジャ
ンパーチップの改良に関する。The present invention relates to improvements in jumper chips used in pattern portions that intersect in three dimensions.
ジャンパーチップは、セラミック等の基板の表面に形成
した導体パターンを立体交叉させるのに使用されている
。Jumper chips are used to three-dimensionally intersect conductor patterns formed on the surface of a ceramic substrate or the like.
この際、導体パターンに高周波信号が流れる場合ニハ、
パターンが交叉することによりノイズが乗らないよう留
意しなければならない。At this time, if a high frequency signal flows through the conductor pattern,
Care must be taken not to introduce noise due to intersecting patterns.
第４図は従来のジャンパーチップの斜視図であって、セ
ラミック基板１の表面には、パターン３と、パターン３
とは立体交叉するパターン２とが形成されている。FIG. 4 is a perspective view of a conventional jumper chip, in which a pattern 3 and a pattern 3 are formed on the surface of a ceramic substrate 1.
A pattern 2 that intersects with the pattern 2 in a three-dimensional manner is formed.
パターン２はパターン３の両側で、切断されその対向す
る端末には、それぞれバットを設けである。Pattern 2 is cut on both sides of pattern 3, and each opposing end is provided with a butt.
ジャンパーチップ４は、直方体状の絶縁体く例えばセラ
ミックよりなる）５に、パターン２の両端末を接続する
導体が所望に形成されている。The jumper chip 4 includes a rectangular parallelepiped insulator (eg, made of ceramic) 5 on which a conductor connecting both ends of the pattern 2 is formed as desired.
即ち、絶縁体５の上部表面に長手方向に帯状の導体パタ
ーン６を形成しである。そして絶縁体５の対向する垂直
の端面部分は、導体パターン６に接続する如くにメタラ
イズを施し、このメタライズされた表面に例えば半田層
を形成して、有底箱形の導体膜７を設けである。That is, a strip-shaped conductor pattern 6 is formed on the upper surface of the insulator 5 in the longitudinal direction. The opposing vertical end surfaces of the insulator 5 are metalized so as to be connected to the conductor pattern 6, and a bottomed box-shaped conductor film 7 is provided by forming, for example, a solder layer on the metalized surface. be.
このようなジャンバーチツマ４をセラミック基板ｌに実
装するには、パターン２の端末部に導体膜７の底面を位
置合わせしてジャンパーチップ４を載せ、加熱し半田を
溶融し接着する。In order to mount such a jumper chip 4 on a ceramic substrate 1, the bottom surface of the conductor film 7 is aligned with the end portion of the pattern 2, the jumper chip 4 is mounted, and the jumper chip 4 is heated to melt the solder and bond.
このようにジャンパーチップ４を使用することにより、
パターン２の端末間を、パターン３の上部を架橋した導
体パターン６を介して接続することができる。即ち、パ
ターン２とパターン３を立体交叉させることが容易であ
る。By using jumper chip 4 in this way,
The terminals of the pattern 2 can be connected via the conductor pattern 6 which bridges the upper part of the pattern 3. That is, it is easy to make pattern 2 and pattern 3 three-dimensionally intersect.
なお、セラミック基板１に他の回路部品を実装する工程
と同時に、ジャンパーチップ４を実装することができる
というメリットがある。Note that there is an advantage that the jumper chip 4 can be mounted at the same time as the process of mounting other circuit components on the ceramic substrate 1.
しかしながら上記従来のジャンパーチップは、導体パタ
ーン６が裸出しておりシールドされていない。したがっ
て、パターン２，３に高周波信号が流れる場合には、ノ
イズが乗るという問題点がある。However, in the conventional jumper chip described above, the conductor pattern 6 is exposed and is not shielded. Therefore, when a high frequency signal flows through patterns 2 and 3, there is a problem that noise is added.
上記従来の問題点を解決するため本発明は、第１図の実
施例に示すように、ジャンパーチップ１゜を、直方体状
の絶縁体１１の中心を貫通する内部導体１２と、
絶縁体１１の対向する端面部分に内部導体１２に連結し
て有底箱形に形成され、セラミック基板１の表面に設け
たパターン２の対向する端末部に接続する導体膜１３と
、
筒状の本体部の軸心を内部導体１２が貫通する如くに、
絶縁体１１内に埋設され、鍔が絶縁°体１１の外周面の
所望の個所に露出した外部導体１４と、外部導体１４に
接続する如くに絶縁体１１の外周面にバンド状に形成さ
れ、セラミック基板１のアースパターン９に接続する導
体膜１５とを備えた構成にし、同軸構造としたものであ
る。In order to solve the above-mentioned conventional problems, the present invention, as shown in the embodiment of FIG. A conductor film 13 connected to the internal conductor 12 on the opposing end surface portions and formed in a box shape with a bottom, and connected to the opposing end portions of the pattern 2 provided on the surface of the ceramic substrate 1; and an axis of the cylindrical main body portion. Just as the inner conductor 12 penetrates the heart,
An external conductor 14 is embedded in the insulator 11 and has a collar exposed at a desired location on the outer circumferential surface of the insulator 11, and is formed in a band shape on the outer circumferential surface of the insulator 11 so as to be connected to the outer conductor 14. A conductor film 15 connected to the earth pattern 9 of the ceramic substrate 1 is provided, and a coaxial structure is provided.
上記本発明の手段によれば、ジャンバーチツマ。 According to the above means of the present invention, there is a jumper chitsuma.
１０は同軸構造であり、且つ外部導体１４は絶縁体１１
内に埋設されている。したがって、交叉するパターン３
とは絶縁された状態でジャンパーチップ１０をセラミッ
ク基板１に実装することができる。10 has a coaxial structure, and the outer conductor 14 is an insulator 11.
It is buried inside. Therefore, intersecting pattern 3
The jumper chip 10 can be mounted on the ceramic substrate 1 while being insulated from the ceramic substrate 1.
よって、パターン２，３間をシールドすることができる
。Therefore, the space between patterns 2 and 3 can be shielded.
以下図示実施例により、本発明を具体的に説明する。な
お、企図を通じて同一符号は同一対象物を示す。The present invention will be specifically explained below with reference to illustrated examples. Note that the same reference numerals refer to the same objects throughout the plan.
第１図は本発明の１実施例の断面図、第２図は斜視図で
あり、第３図は第１図の鎖線Ａ−Ａ部分の断面図である
。FIG. 1 is a sectional view of one embodiment of the present invention, FIG. 2 is a perspective view, and FIG. 3 is a sectional view taken along the chain line AA in FIG.
第１図〜第３図において、１１は、半田付は温度に耐え
る合成樹脂、例えば弗素系樹脂が直方体状にモールド成
形されてなる絶縁体である。In FIGS. 1 to 3, numeral 11 is an insulator made of a temperature-resistant synthetic resin, such as a fluorine-based resin, molded into a rectangular parallelepiped shape.
例えば銅系金属よりなる内部導体１２は、絶縁体１１の
中ＩＣｓ、を貫通する如くインサート成形され、絶縁体
１１の対向する端面部分には、内部導体１２に連結して
有底箱形にメタライズを施し、このメタライズ層の表面
を、例えば半田メッキ等して導体膜１３を形成しである
。For example, the internal conductor 12 made of copper-based metal is insert-molded so as to penetrate through the ICs in the insulator 11, and the opposing end face portions of the insulator 11 are metalized in a bottomed box shape connected to the internal conductor 12. The surface of this metallized layer is then plated with solder, for example, to form a conductive film 13.
例えば銅系金属よりなる本体部が円筒状の外部導体１４
は、長さが絶縁体１１の長さよりも所望に短く形成され
ている。そして、゛この本体部の両端には、絶縁体１１
の断面形状にほぼ等しい鍔を半田付け等して設けである
。なお、このように鍔を半田付けせず、外部導体１４の
両端部を所望に切り込み、外側に直角に拡開して鍔を設
けても良い＝このような外部導体１４の本体部の筒の内
外に、絶縁体が充填され、且つ軸心を内部導体１２が絶
縁され貫通するように、外部導体１４と内部導体１２と
は同時にインサート成形されている。For example, the outer conductor 14 has a cylindrical main body made of copper-based metal.
is formed to have a length shorter than the length of the insulator 11 as desired. ``Insulators 11 are provided at both ends of this main body.
A flange having a cross-sectional shape approximately equal to that of is provided by soldering or the like. In addition, without soldering the flange in this way, the flange may be provided by cutting both ends of the outer conductor 14 as desired and widening it at right angles to the outside. The outer conductor 14 and the inner conductor 12 are simultaneously insert-molded so that an insulator is filled inside and outside, and the inner conductor 12 is insulated and penetrates the axis.
外部導体１４の鍔が絶縁体１１の表面に裸出した部分は
、外部導体１４の鍔に接続する如くに絶縁体１１の外周
面をバンド状にメタライズを施し、このメタライズ層の
表面を、例えば半田メッキ等して導体膜１５を形成しで
ある。The part where the collar of the outer conductor 14 is exposed on the surface of the insulator 11 is metalized on the outer peripheral surface of the insulator 11 in a band shape so as to be connected to the collar of the outer conductor 14, and the surface of this metallized layer is, for example, A conductor film 15 is formed by solder plating or the like.
上述のようなジャンパーチップ１０を、導体膜１３の底
面をパターン２の端末部のそれぞれに、導体膜１５の底
面をアースパターン９のそれぞれに位置合わせし、パタ
ーン３に架橋するようにセラミック基Ｍｉｔに載せる。The jumper chip 10 as described above is aligned with the bottom surface of the conductor film 13 on each of the terminal parts of the pattern 2, and the bottom surface of the conductor film 15 on each of the ground patterns 9, and a ceramic substrate Mit is placed so as to bridge the pattern 3. I'll put it on.
そして、それぞれの導体膜１３゜１５を、対応するパタ
ーンに、半田接着法、２ＪＥ電性電性樹脂性等所望の接
着法により接着する。Then, each of the conductive films 13 and 15 is bonded to the corresponding pattern by a desired bonding method such as solder bonding, 2JE conductive resin, or the like.
このような同軸構造のジャンバーチ、プ１０を使用する
ことにより、パターン２の端末間を、内部導体１２を介
して接続することができる。即ち、パターン２とパター
ン３とはシールドされた状態で、立体交叉させることが
できる。By using the jumper birch 10 having such a coaxial structure, the terminals of the pattern 2 can be connected via the internal conductor 12. That is, pattern 2 and pattern 3 can be intersected three-dimensionally in a shielded state.
なお、外部導体の本体部の形状は円筒に限らず、例えば
角筒でも良いことは勿論である。また、セラミック以外
の回路基板にも実施し得ることも同様である。Note that the shape of the main body portion of the outer conductor is not limited to a cylinder, and it goes without saying that it may be a rectangular tube, for example. Similarly, the present invention can also be applied to circuit boards other than ceramics.
以上説明したように本発明は、ジャンパーチップを同軸
構造としたことにより、立体交叉するパターン間のシー
ルドが可能となり、ノイズの発生を阻止できるという実
用上で優れた効果がある。As explained above, the present invention has an excellent practical effect in that the jumper chip has a coaxial structure, which enables shielding between three-dimensionally intersecting patterns, and prevents the generation of noise.
第１図は本発明の１実施例の断面図、
第２図は斜視図、
第３図は第１図の鎖線Ａ−Ａ部分の断面図、第４図は従
来のジャンパーチップの斜視図である。
図において、
１はセラミック基板、 ２．３はパターン、４．１０
はジャンパーチップ、
５．１１は絶縁体、 ６は導体パターン、７．１
３．１５は導体膜、 ９はアースパターン、１２は
内部導体、 １４は外部導体を示す。Fig. 1 is a sectional view of one embodiment of the present invention, Fig. 2 is a perspective view, Fig. 3 is a sectional view taken along the chain line A-A in Fig. 1, and Fig. 4 is a perspective view of a conventional jumper chip. be. In the figure, 1 is a ceramic substrate, 2.3 is a pattern, 4.10
is a jumper chip, 5.11 is an insulator, 6 is a conductor pattern, 7.1
3.15 is a conductor film, 9 is a ground pattern, 12 is an internal conductor, and 14 is an external conductor.
Claims (1)
（１２）と、 該絶縁体（１１）の対向する端面部分に該内部導体（１
２）に連結して形成され、基板（１）の表面に設けたパ
ターン（２）の対向する端末部に接続する導体膜（１３
）と、 筒状の本体部の軸心を該内部導体（１２）が貫通する如
くに、該絶縁体（１１）内に埋設され、鍔が該絶縁体の
外周面の所望の個所に露出した外部導体（１４）と、 該外部導体（１４）に接続する如くに該絶縁体（１１）
の外周面にバンド状に形成され、該基板（１）のアース
パターン（９）に接続する導体膜（１５）とを、備えた
ことを特徴とするジャンパーチップ。[Claims] An internal conductor (12) penetrating the center of a rectangular parallelepiped insulator (11), and an internal conductor (12) at opposing end surfaces of the insulator (11).
A conductor film (13) is formed to connect to the opposite end portion of the pattern (2) provided on the surface of the substrate (1).
), and the inner conductor (12) is embedded in the insulator (11) so as to pass through the axis of the cylindrical main body, and the collar is exposed at a desired location on the outer circumferential surface of the insulator. an outer conductor (14); and an insulator (11) connected to the outer conductor (14).
1. A jumper chip comprising: a conductive film (15) formed in a band shape on the outer peripheral surface of the substrate (1) and connected to a ground pattern (9) of the substrate (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10068785A JPS61259467A (en) | 1985-05-13 | 1985-05-13 | Jumper chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10068785A JPS61259467A (en) | 1985-05-13 | 1985-05-13 | Jumper chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61259467A true JPS61259467A (en) | 1986-11-17 |
Family
ID=14280642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10068785A Pending JPS61259467A (en) | 1985-05-13 | 1985-05-13 | Jumper chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61259467A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0362459U (en) * | 1989-10-20 | 1991-06-19 | ||
| JPH03179681A (en) * | 1989-12-08 | 1991-08-05 | Kenwood Corp | Structure of chip jumper |
| JPH0462770A (en) * | 1990-06-30 | 1992-02-27 | Taiyo Yuden Co Ltd | Chip type jumper parts having jumper shaft member made of hard cupper and manufacture thereof |
| WO2010116469A1 (en) * | 2009-03-30 | 2010-10-14 | 富士通株式会社 | Differential path replacement component, printed board, and electronic device |
| JPWO2021084601A1 (en) * | 2019-10-29 | 2021-05-06 | ||
| WO2021095163A1 (en) * | 2019-11-13 | 2021-05-20 | 日本電信電話株式会社 | High-frequency line structure, subassembly, line card, and manufacturing method for high-frequency line structure |
-
1985
- 1985-05-13 JP JP10068785A patent/JPS61259467A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0362459U (en) * | 1989-10-20 | 1991-06-19 | ||
| JPH03179681A (en) * | 1989-12-08 | 1991-08-05 | Kenwood Corp | Structure of chip jumper |
| JPH0462770A (en) * | 1990-06-30 | 1992-02-27 | Taiyo Yuden Co Ltd | Chip type jumper parts having jumper shaft member made of hard cupper and manufacture thereof |
| WO2010116469A1 (en) * | 2009-03-30 | 2010-10-14 | 富士通株式会社 | Differential path replacement component, printed board, and electronic device |
| JP5083460B2 (en) * | 2009-03-30 | 2012-11-28 | 富士通株式会社 | Differential path replacement parts, printed circuit boards, and electronic devices |
| US8933339B2 (en) | 2009-03-30 | 2015-01-13 | Fujitsu Limited | Differential path replacement component, printed board, and electronic device |
| JPWO2021084601A1 (en) * | 2019-10-29 | 2021-05-06 | ||
| WO2021084601A1 (en) * | 2019-10-29 | 2021-05-06 | 日本電信電話株式会社 | High-frequency line connection structure |
| CN114631226A (en) * | 2019-10-29 | 2022-06-14 | 日本电信电话株式会社 | High-frequency line connection structure |
| CN114631226B (en) * | 2019-10-29 | 2024-01-16 | 日本电信电话株式会社 | High-frequency circuit connection structure |
| WO2021095163A1 (en) * | 2019-11-13 | 2021-05-20 | 日本電信電話株式会社 | High-frequency line structure, subassembly, line card, and manufacturing method for high-frequency line structure |
| JPWO2021095163A1 (en) * | 2019-11-13 | 2021-05-20 | ||
| CN114730980A (en) * | 2019-11-13 | 2022-07-08 | 日本电信电话株式会社 | High-frequency circuit structure, subassembly, line card, and method for manufacturing high-frequency circuit structure |
| CN114730980B (en) * | 2019-11-13 | 2024-03-19 | 日本电信电话株式会社 | High-frequency circuit structure, subassembly, circuit card, and method for manufacturing high-frequency circuit structure |
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