JPS6125234Y2 - - Google Patents
Info
- Publication number
- JPS6125234Y2 JPS6125234Y2 JP1978158043U JP15804378U JPS6125234Y2 JP S6125234 Y2 JPS6125234 Y2 JP S6125234Y2 JP 1978158043 U JP1978158043 U JP 1978158043U JP 15804378 U JP15804378 U JP 15804378U JP S6125234 Y2 JPS6125234 Y2 JP S6125234Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- electrodes
- shaped circuit
- external terminal
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000463 material Substances 0.000 claims description 14
- 239000011521 glass Substances 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 4
- 229920003002 synthetic resin Polymers 0.000 claims description 4
- 239000000057 synthetic resin Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 description 23
- 239000010410 layer Substances 0.000 description 23
- 239000000919 ceramic Substances 0.000 description 13
- 239000003985 ceramic capacitor Substances 0.000 description 7
- 230000010355 oscillation Effects 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052573 porcelain Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000595 mu-metal Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920003217 poly(methylsilsesquioxane) Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【考案の詳細な説明】
本考案は外部端子電極を有するチツプ状回路素
子に関し、チツプ状回路素子をプリント配線板に
半田付装着した後に、当該チツプ状回路素子とク
ロスする導体パターンと、チツプ状回路素子の電
極との間に生ずるストレーキヤパシテイーによる
電子回路装置への悪影響を解消できるようにした
ものである。[Detailed Description of the Invention] The present invention relates to a chip-shaped circuit element having external terminal electrodes, and after the chip-shaped circuit element is soldered and attached to a printed wiring board, a conductor pattern that crosses the chip-shaped circuit element and a chip-shaped This is designed to eliminate the adverse effect on the electronic circuit device due to the stray capacitance that occurs between the electrodes of the circuit element.
最近、超薄形ラジオ、超小型トランシーバー、
水晶発振式電子腕時計等の超小型薄形高密度実装
化に伴い、抵抗器、コンデンサなどの回路素子は
小型リードレスタイプのチツプ状回路素子をプリ
ント配線板のプリントパターン間に直接半田装着
する回路モジユールの組立が急速に普及してい
る。このようなチツプ状回路素子をプリント配線
板の導体パターン間に半田付装着した場合、第１
図、第２図に示されるような実装構造となること
がある。図において、１はコンデンサ、抵抗器等
のチツプ状回路素子であり、平板状に形成された
素体の長さ方向に沿つて、素体の厚み方向の表面
と略平行となるように電極７を形成すると共に、
素体の長さ方向の両端に、電極７を接続させる外
部端子電極２，２′を形成した構造となつてい
る。この例では、チツプ状回路素子１は積層磁器
コンデンサでなり、平板状の磁器誘電体素体の厚
み方向に、磁器誘電体層を介して、複数の内部電
極７を層状に埋設し、これらの内部電極７を、そ
の隔一が並列接続となる関係で、外部端子電極
２，２′にそれぞれ接続させてある。 Recently, ultra-thin radios, ultra-compact transceivers,
With the trend toward ultra-compact, thin, and high-density packaging of crystal oscillation electronic watches, etc., circuit elements such as resistors and capacitors are circuits in which small leadless chip-shaped circuit elements are directly soldered between printed patterns on printed wiring boards. Modular assembly is rapidly becoming popular. When such a chip-shaped circuit element is soldered between the conductor patterns of a printed wiring board, the first
The mounting structure may be as shown in FIGS. In the figure, reference numeral 1 indicates a chip-shaped circuit element such as a capacitor or a resistor, and an electrode 7 is placed along the length direction of the element body formed in a flat plate shape so as to be approximately parallel to the surface in the thickness direction of the element body. Along with forming the
It has a structure in which external terminal electrodes 2, 2' to which electrodes 7 are connected are formed at both ends in the length direction of the element body. In this example, the chip-shaped circuit element 1 is a multilayer ceramic capacitor, in which a plurality of internal electrodes 7 are embedded in layers in the thickness direction of a flat ceramic dielectric element through a ceramic dielectric layer. The internal electrodes 7 are connected to the external terminal electrodes 2 and 2', respectively, in such a way that the internal electrodes 7 are connected in parallel.
３はアルミナ基板、ガラスエポキシ基板等から
なるプリント配線板、４及び４′はチツプ状回路
素子１を半田付けする導体パターン、５はクロス
導体パターンである。クロス導体パターン５は電
子腕時計、超薄形ラジオ等の回路モジユール等の
高密度実装化に伴い配線実装効率を上げる為に設
けられたものである。 3 is a printed wiring board made of an alumina substrate, a glass epoxy substrate, etc., 4 and 4' are conductor patterns to which the chip-shaped circuit elements 1 are soldered, and 5 is a cross conductor pattern. The cross conductor pattern 5 is provided to increase wiring mounting efficiency as circuit modules for electronic wristwatches, ultra-thin radios, etc. become more densely packaged.
チツプ状回路素子１は、第２図に示すように、
クロス導体パターン５を跨いで、導体パターン
４，４′に外部端子電極２，２′を半田６によつて
固着してある。 The chip-shaped circuit element 1, as shown in FIG.
External terminal electrodes 2, 2' are fixed to the conductor patterns 4, 4' by solder 6, straddling the cross conductor pattern 5.
ところが第２図に示すような固着構造をとる場
合、チツプ状回路素子１と、クロス導体パターン
５との間に比較的大きなストレーキヤパシテイー
Csが生ずる欠点がある。 However, when using the fixing structure as shown in FIG.
There is a drawback that Cs occurs.
つまり、内部電極７と、クロス導体パターン５
との間に高誘電率の磁器誘電体が介在し、内部電
極７とクロス導体パターン５が電極として働くた
めに、導体パターン４′と、クロス導体パターン
５との間に回路設計上定量的に考慮不可能なキヤ
パシテイーCsが発生するのである。 In other words, the internal electrode 7 and the cross conductor pattern 5
Since a ceramic dielectric material with a high dielectric constant is interposed between the inner electrode 7 and the cross conductor pattern 5, and the internal electrode 7 and the cross conductor pattern 5 act as electrodes, there is a quantitative difference between the conductor pattern 4' and the cross conductor pattern 5 in terms of circuit design. This results in a capacity Cs that cannot be considered.
第２図の場合、内部電極７とクロス導体パター
ン５との間に、比誘電率εｓで厚さt1の高誘電率
磁器誘電体と、厚さt2の空気層が介在することに
なるので、内部電極７及びクロス導体パターン５
の重なり面積をＳとすると、ストレーキヤパシテ
イーCsは次式で求められ
Cs＝εｓ．εｏ．Ｓ／ｔ１＋εｓ．ｔ２となる。 In the case of FIG. 2, a high permittivity ceramic dielectric material with a relative dielectric constant εs and a thickness t 1 and an air layer with a thickness t 2 are interposed between the internal electrode 7 and the cross conductor pattern 5. Therefore, the internal electrode 7 and cross conductor pattern 5
Let S be the overlapping area of Cs, the strain capacity Cs is calculated by the following formula: Cs=εs. εo. S/t 1 +εs. It becomes t2 .
上式においてεｏ、εｓ、t1、Ｓは既知である
が、空気層厚みt2は、一般に、プリント配線板３
が湾曲したり、或いは、半田付け時の半田溶融に
よつて、チツプ状回路素子１が移動したときに生
ずる微小の空隙の変化に伴なつて変動する。空気
層厚みt2は、各回路モジユールにより大きく異な
るが、空気層厚みt2が十分大であればストレーキ
ヤパシテイーCsは比較的小さくなる。 In the above equation, εo, εs, t 1 and S are known, but the air layer thickness t 2 is generally
It changes with the change in minute gaps that occur when the chip-shaped circuit element 1 moves due to bending or melting of solder during soldering. The air layer thickness t 2 varies greatly depending on each circuit module, but if the air layer thickness t 2 is sufficiently large, the strain capacity Cs will be relatively small.
しかしながら、第３図のごとくプリント配線板
がわずかに湾曲していて、磁器誘電体素体の表面
がクロス導体パターン５に接触して取付けられた
場合、t2＝Ｏであるから、
Cs＝εs.εo.S／t1となり、非常に大きなストレ
ーキヤパシテイーCsが導体パターン４とクロス
導体パターン５との間に発生し、ストレーキヤパ
シテイーCsによる容量結合が生ずることにな
る。このため、伝送周波数特性の高域における悪
化、発振周波数及び同調周波数の設計値からのズ
レ及び異常発振等の不都合が生ずる。 However, if the printed wiring board is slightly curved as shown in Fig. 3 and the surface of the ceramic dielectric element is mounted in contact with the cross conductor pattern 5, then t 2 =O, so Cs = εs .εo.S/t 1 , a very large strain capacitance Cs occurs between the conductor pattern 4 and the cross conductor pattern 5, and capacitive coupling due to the strain capacitance Cs occurs. This causes problems such as deterioration of the transmission frequency characteristics in the high range, deviation of the oscillation frequency and tuning frequency from the designed values, and abnormal oscillation.
更に、前述したように、プリント配線板３のわ
ずかな湾曲、半田付時の半田溶融時の移動による
微小な空隙により、空気層厚みt2がバラつく。つ
まりストレーキヤパシテイーCsが大きくバラつ
くことになるので、前述の周波数のズレ、異常発
振が生ずる。このため、ストレーキヤパシテイー
Csの低減及びバラつきの均一化等の改善が望ま
れてあつた。 Furthermore, as described above, the air layer thickness t 2 varies due to the slight curvature of the printed wiring board 3 and minute voids caused by movement during solder melting during soldering. In other words, the strain capacity Cs will vary greatly, resulting in the aforementioned frequency shift and abnormal oscillation. For this reason, the strain capacity
Improvements such as reduction of Cs and uniformity of variation have been desired.
本考案はこれ等の問題点を解消した高信頼性の
チツプ状回路素子を提供するものであり、以下実
施例に従つて詳細に詳述する。 The present invention provides a highly reliable chip-shaped circuit element that solves these problems, and will be described in detail below with reference to embodiments.
第４図は本考案に係るチツプ状回路素子の一実
施例における断面図、第５図は本考案に係るチツ
プ状回路素子をプリント配線板に実装した状態を
示す図である。図において、２１はチツプ状回路
素子である。この実施例では積層型磁気コンデン
サを示し、チタン酸バリウム、酸化チタン等を主
成分として、平板状に形成された磁器誘電体素体
の長さ方向に沿つて、磁器誘電体素体の厚み方向
の表面と略平向となるように、磁器誘電体層を介
して対向する複数の内部電極２２を層状に埋設す
ると共に、磁器誘電体素体の長さ方向の両端に、
外部端子電極２３，２３′を形成し、前記内部電
極２２を、その隔一が並列接続となる関係で、外
部端子電極２３，２３′にそれぞれ接続させてあ
る。 FIG. 4 is a sectional view of one embodiment of the chip-shaped circuit element according to the present invention, and FIG. 5 is a diagram showing the state in which the chip-shaped circuit element according to the present invention is mounted on a printed wiring board. In the figure, 21 is a chip-shaped circuit element. In this example, a multilayer magnetic capacitor is shown, in which the main components are barium titanate, titanium oxide, etc., and the porcelain dielectric element is formed into a flat plate along the length direction of the porcelain dielectric element. A plurality of internal electrodes 22 are embedded in a layered manner so as to be substantially parallel to the surface of the ceramic dielectric body, and at both ends of the ceramic dielectric body in the longitudinal direction,
External terminal electrodes 23, 23' are formed, and the internal electrodes 22 are connected to the external terminal electrodes 23, 23', respectively, in a parallel connection.
また、外部端子電極２３，２３′を除く誘電体
磁器素体の厚み方向の両面または片面には、ガラ
ス、合成樹脂等でなる低誘電率物質層２４，２
４′を被着させてある。低誘電率物質層２４，２
４′は、表面が外部端子電極２３，２３′の電極端
より高くなるように層状に形成してある。低誘電
率物質２４，２４′は素誘電体磁器素体の片面で
も良いが、片面のみにすると、プリント配線板へ
の装着の際に方向性が出るので、作業能率を上げ
るためには両面に形成するのがよい。また両面に
形成した場合には、耐湿性及び絶縁コートとして
も有効である。 In addition, low dielectric constant material layers 24, 2 made of glass, synthetic resin, etc. are provided on both sides or one side in the thickness direction of the dielectric ceramic body except for the external terminal electrodes 23, 23'.
4' is applied. Low dielectric constant material layer 24, 2
4' is formed in a layered manner so that its surface is higher than the electrode ends of the external terminal electrodes 23, 23'. The low dielectric constant material 24, 24' may be applied to one side of the dielectric ceramic body, but if it is applied only to one side, the directionality will appear when it is attached to the printed wiring board, so in order to increase work efficiency, it is necessary to apply it to both sides. It is better to form. Furthermore, when it is formed on both sides, it is effective as a moisture-resistant and insulating coat.
上述の積層磁器コンデンサを得るには、チタン
酸バリウム、酸化チタン等の原料を50〜100μの
厚さの可塑性を持つフイルム状にし、このフイル
ムに内部電極２２となる白金、パラジウム等の貴
金属ペーストを塗布し、このフイルムを必要な枚
数だけ重畳し、約1350℃の高温焼成した後、長さ
方向の両端部に、Ag−Pd系ペイントを塗布焼付
して外部端子電極２３，２３′を形成する。この
実施例では、積層磁器コンデンサとなつているの
で、内部電極２２は、その隔一が並列接続となる
関係で、外部端子電極２３，２３′にそれぞれ接
続させる。 To obtain the above-mentioned multilayer ceramic capacitor, raw materials such as barium titanate and titanium oxide are made into a plastic film with a thickness of 50 to 100 μm, and noble metal paste such as platinum or palladium, which will become the internal electrode 22, is applied to this film. After overlapping the required number of films and firing at a high temperature of about 1350°C, Ag-Pd paint is applied and baked on both lengthwise ends to form external terminal electrodes 23, 23'. . In this embodiment, since it is a multilayer ceramic capacitor, the internal electrodes 22 are connected to the external terminal electrodes 23 and 23', respectively, in a parallel connection.
この後、外部端子電極２３，２３′を残すよう
に、磁器誘電体素体の厚み方向における両側また
は片面に、低誘電率物質２４，２４′として、フ
リツトガラス等の低誘電率ガラスペーストをスク
リーン印刷法により印刷塗布して焼付けることに
より完成する。 After this, a low dielectric constant glass paste such as fritted glass is screen printed as a low dielectric constant material 24, 24' on both sides or one side in the thickness direction of the ceramic dielectric body so as to leave the external terminal electrodes 23, 23'. It is completed by printing and coating using a method and baking.
本考案に係るチツプ状回路素子は、低誘電率物
質２４，２４′の表面が外部端子電極２３，２
３′の電極端より高くなるように形成されている
ため、プリント配線板に実装するに当り、第５図
に示すように、クロス導体パターン２６を跨い
で、外部端子電極２３，２３′を導体パターン２
５，２５′に半田した場合、低誘電率物質層２
４，２４′の表面がクロス導体パターン２６に接
触する。従つて、内部電極２２とクロス導体パタ
ーン２６との間には、比誘電率εｓ、厚みt1の高
誘電率磁器誘電体層、及び、比誘電率εＧ、厚み
t2の低誘電率物質層２４′が介在し、内部電極２
２とクロス導体パターン２６との間には空気層が
介在しなくなる。 In the chip-shaped circuit element according to the present invention, the surfaces of the low dielectric constant materials 24 and 24' are the external terminal electrodes 23 and 2.
Since the external terminal electrodes 23 and 23' are formed to be higher than the electrode ends 3', when mounting on a printed wiring board, as shown in FIG. pattern 2
5, 25', the low dielectric constant material layer 2
4 and 24' are in contact with the cross conductor pattern 26. Therefore, between the internal electrode 22 and the cross conductor pattern 26, there is a high permittivity ceramic dielectric layer with a relative permittivity εs and a thickness t1 , and a high permittivity ceramic dielectric layer with a relative permittivity εG and a thickness t1.
A low dielectric constant material layer 24' of t 2 is interposed, and the internal electrode 2
There is no air layer between 2 and the cross conductor pattern 26.
従つて、内部電極２２とクロス導体パターン２
６との間に発生するストレーキヤパシテイーCs
は、次のようになる。 Therefore, the internal electrode 22 and the cross conductor pattern 2
Stray capacity Cs that occurs between 6 and
becomes as follows.
低誘電率物質層２４′がガラスの場合、εＧは
５〜７程度であり、低誘電率物質層２４′の厚み
t2を、最外側にある誘電体磁器層の厚みt1のεＧ
倍以上に選ぶことにより、ストレーキヤパシテイ
ーCsを小さくすることが出来るので、第３図に
示したような湾曲したプリント配線基板の場合で
も、ストレーキヤパシテイーのバラツキが改善で
きる。従つて、本考案のチツプ状回路素子を用い
た回路設計においては、ストレーキヤパシテイー
Csを見込んだ設計が出来る等の利点が出て来
る。 When the low dielectric constant material layer 24' is made of glass, εG is about 5 to 7, and the thickness of the low dielectric constant material layer 24'
t 2 is the thickness t 1 of the outermost dielectric ceramic layer εG
By selecting at least twice the value, the strain capacity Cs can be made small, so even in the case of a curved printed wiring board as shown in FIG. 3, the variation in the strain capacity can be improved. Therefore, in the circuit design using the chip-shaped circuit element of the present invention, the stray capacitance is
There are advantages such as being able to design with Cs in mind.
上記実施例では、多数の内部電極２２を有する
チツプ状積層型磁器コンデンサを示したが、２つ
の内部電極を有するチツプ状単層型磁器コンデン
サや、電極を素体の表面に設けたチツプ状単板型
磁器コンデンサ、更には、チツプ状抵抗器等の他
のチツプ状回路素子にも適用できる。 In the above embodiment, a chip-like multilayer ceramic capacitor having a large number of internal electrodes 22 was shown, but a chip-like single-layer ceramic capacitor having two internal electrodes and a chip-like single-layer ceramic capacitor having electrodes on the surface of the element body are also available. It can also be applied to plate-type ceramic capacitors and other chip-shaped circuit elements such as chip-shaped resistors.
以上述べたように、本考案は、平板状に形成さ
れた素体の長さ方向に沿つて、前記素体の厚み方
向の表面と略平行になるように電極を形成し、前
記素体の長さ方向の両端に、前記電極を接続させ
る外部端子電極を形成したチツプ状回路素子にお
いて、前記外部端子電極を除く前記素体の厚み方
向における表面の片面または両面、表面が前記外
部端子電極の電極端より高くなるように、ガラ
ス、合成樹脂等でなる低誘電率物質の層を被着さ
せたことを特徴とするから、次のような効果が得
られる。 As described above, in the present invention, electrodes are formed along the length direction of an element body formed into a flat plate so as to be substantially parallel to the surface of the element body in the thickness direction, and In a chip-shaped circuit element in which external terminal electrodes to which the electrodes are connected are formed at both ends in the length direction, one or both surfaces of the element body in the thickness direction excluding the external terminal electrodes, the surface of which is connected to the external terminal electrodes. Since it is characterized in that a layer of a low dielectric constant material made of glass, synthetic resin, etc. is deposited so as to be higher than the electrode end, the following effects can be obtained.
(1) チツプ状回路素子とクロス導体パターンとの
間に発生するストレーキヤパシテイーを大幅に
低減できるので、伝送周波数特性の高域におけ
る悪化、発振周波数及び同調周波数の設計値か
らのズレ及び異常発振等を防止できる。(1) Stray capacitance that occurs between the chip-shaped circuit element and the cross conductor pattern can be significantly reduced, thereby preventing deterioration of transmission frequency characteristics in the high range, deviation of the oscillation frequency and tuning frequency from the designed values, and abnormal oscillation. etc. can be prevented.
(2) クロス導体パターンと高誘電率電体との接触
がなく、空気層も無視できるので、ストレーキ
ヤパシテイーのバラツキが極めて小さくなり、
周波数特性のバラツキのない、高精度、高信頼
性の回路モジユールが得られる。(2) Since there is no contact between the cross conductor pattern and the high dielectric constant electric material, and the air layer can be ignored, the variation in the strain capacitance is extremely small.
A highly accurate, highly reliable circuit module with no variation in frequency characteristics can be obtained.
(3) 低誘電率物質層は、安価なフリツトガラスま
たは合成樹脂を従来のスクリーン印刷法によつ
て塗布することにより、容易に形成できるの
で、大量生産が可能であり、工数、価格の大幅
な低減が計れる。(3) The low dielectric constant material layer can be easily formed by applying inexpensive fritted glass or synthetic resin using the conventional screen printing method, making mass production possible and significantly reducing man-hours and costs. can be measured.
(4) 低誘電物質層をガラスで形成することによ
り、半田付後の洗浄液に対する耐薬品性に優れ
たものが得られる。また、ガラスは熱膨張係数
がチツプ状回路素子を構成する磁気誘電体素子
と近似するので、密着強度が高くなる。(4) By forming the low dielectric material layer with glass, it is possible to obtain a product with excellent chemical resistance to cleaning fluids after soldering. Further, since glass has a coefficient of thermal expansion similar to that of the magnetic dielectric element constituting the chip-shaped circuit element, the adhesion strength is increased.
(5) 従来のチツプ状回路素子は、外部端子電極以
外、裸の状態であるが、本考案に係るチツプ状
回路素子は、低誘電率物質層を被覆コートした
構造となるために、耐湿性、絶縁性が向上し、
信頼性が高くなる。(5) Conventional chip-shaped circuit elements are bare except for external terminal electrodes, but the chip-shaped circuit element according to the present invention has a structure coated with a low dielectric constant material layer, so it has moisture resistance. , insulation is improved,
Increased reliability.
第１図は従来のチツプ状回路素子をプリント配
線板に実装するときの状態を示す斜視図、第２図
は同じく半田付装着された状態での断面図、第３
図は同じくその問題点を説明する断面図、第４図
は本考案に係るチツプ状回路素子の断面図、第５
図は本考案に係るチツプ状回路素子をプリント配
線板に実装した状態での断面図である。
２２……内部電極、２３，２３′……外部端子
電極、２４，２４′……低誘電率物質層。
Fig. 1 is a perspective view showing a state in which a conventional chip-shaped circuit element is mounted on a printed wiring board, Fig. 2 is a cross-sectional view showing the same state in which it is soldered and attached, and Fig. 3
FIG. 4 is a sectional view of the chip-shaped circuit element according to the present invention, and FIG.
The figure is a sectional view of a chip-shaped circuit element according to the present invention mounted on a printed wiring board. 22... Internal electrode, 23, 23'... External terminal electrode, 24, 24'... Low dielectric constant material layer.
Claims (1)
て、前記素体の厚み方向の表面と略平行となる
ように電極を形成し、前記素体の長さ方向の両
端に、前記電極を接続させる外部端子電極を形
成したチツプ状回路素子において、前記外部端
子電極を除く前記素体の厚み方向における表面
の片面または両面に、表面が前記外部端子電極
の電極端より高くなるように、ガラス、合成樹
脂等でなる低誘電率物質の層を被着させたこと
を特徴とするチツプ状回路素子。 (2) 前記素体は誘電体でなり、前記電極は誘電体
層を介して前記素体の厚み方向に層状に埋設さ
れた複数の内部電極でなり、これらの内部電極
は、その隔一が並列接続となる関係で、前記外
部端子電極にそれぞれ接続させたことを特徴と
する実用新案登録請求の範囲第１項に記載のチ
ツプ状回路素子。[Claims for Utility Model Registration] (1) Electrodes are formed along the length direction of an element body formed in a flat plate shape so as to be substantially parallel to the surface of the element body in the thickness direction, and In a chip-shaped circuit element in which external terminal electrodes to which the electrodes are connected are formed at both longitudinal ends of the element body, one or both surfaces of the element body in the thickness direction, excluding the external terminal electrodes, have the external terminal electrodes on one or both surfaces of the element body in the thickness direction. A chip-shaped circuit element characterized in that a layer of a low dielectric constant material made of glass, synthetic resin, etc. is deposited so as to be higher than the end of the electrode. (2) The element body is made of a dielectric material, and the electrodes are a plurality of internal electrodes embedded in a layered manner in the thickness direction of the element body through a dielectric layer, and these internal electrodes are separated from each other. The chip-shaped circuit element according to claim 1, wherein the chip-shaped circuit element is connected to each of the external terminal electrodes in a parallel connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1978158043U JPS6125234Y2 (en) | 1978-11-17 | 1978-11-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1978158043U JPS6125234Y2 (en) | 1978-11-17 | 1978-11-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5575139U JPS5575139U (en) | 1980-05-23 |
| JPS6125234Y2 true JPS6125234Y2 (en) | 1986-07-29 |
Family
ID=29149527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1978158043U Expired JPS6125234Y2 (en) | 1978-11-17 | 1978-11-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6125234Y2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0543462Y2 (en) * | 1986-10-28 | 1993-11-02 | ||
| JP2008060214A (en) * | 2006-08-30 | 2008-03-13 | Murata Mfg Co Ltd | Mounting structure of laminated ceramic electronic component |
| JP6428764B2 (en) * | 2014-04-02 | 2018-11-28 | 株式会社村田製作所 | Chip-type electronic components |
| KR101862466B1 (en) * | 2016-08-24 | 2018-06-29 | 삼성전기주식회사 | Inductor and package having the same |
| JP7061708B2 (en) * | 2021-03-03 | 2022-04-28 | 太陽誘電株式会社 | Multilayer ceramic capacitors |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5148155A (en) * | 1974-10-22 | 1976-04-24 | Matsushita Electric Ind Co Ltd | Chokogatateikososhi nyoru shusekikairono seizoho |
| JPS5313231B2 (en) * | 1973-11-26 | 1978-05-09 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5019651Y2 (en) * | 1971-02-03 | 1975-06-14 | ||
| JPS5086665U (en) * | 1973-12-13 | 1975-07-23 | ||
| JPS5726350Y2 (en) * | 1974-04-06 | 1982-06-08 | ||
| JPS5260758U (en) * | 1975-10-31 | 1977-05-04 | ||
| JPS52170258U (en) * | 1976-06-18 | 1977-12-24 | ||
| JPS5313231U (en) * | 1976-07-16 | 1978-02-03 |
-
1978
- 1978-11-17 JP JP1978158043U patent/JPS6125234Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5313231B2 (en) * | 1973-11-26 | 1978-05-09 | ||
| JPS5148155A (en) * | 1974-10-22 | 1976-04-24 | Matsushita Electric Ind Co Ltd | Chokogatateikososhi nyoru shusekikairono seizoho |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5575139U (en) | 1980-05-23 |
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