JP3209304B2 - Laminated electronic component and method of manufacturing the same - Google Patents

Laminated electronic component and method of manufacturing the same

Info

Publication number
JP3209304B2
JP3209304B2 JP30396893A JP30396893A JP3209304B2 JP 3209304 B2 JP3209304 B2 JP 3209304B2 JP 30396893 A JP30396893 A JP 30396893A JP 30396893 A JP30396893 A JP 30396893A JP 3209304 B2 JP3209304 B2 JP 3209304B2
Authority
JP
Japan
Prior art keywords
conductor
adhesive
electronic component
thickness
fired ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30396893A
Other languages
Japanese (ja)
Other versions
JPH07161583A (en
Inventor
圭司郎 天谷
友紀 広瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP30396893A priority Critical patent/JP3209304B2/en
Publication of JPH07161583A publication Critical patent/JPH07161583A/en
Application granted granted Critical
Publication of JP3209304B2 publication Critical patent/JP3209304B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、種々の電子回路を構成
するために使用されるLC複合部品、インダクタ、コン
デンサ等の積層型電子部品及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer electronic component such as an LC composite component, an inductor, a capacitor and the like used for forming various electronic circuits, and a method of manufacturing the same .

【0002】[0002]

【従来の技術と課題】従来の積層型電子部品は、グリー
ンシートに導体を印刷し、このシートを積み重ねて一体
的に焼成することにより製作されていた。しかしなが
ら、この製法では、焼成時のシート収縮のばらつきによ
って導体の寸法がばらつき、所定の電気特性を有する電
子部品を安定して量産することが困難であるという問題
があった。
2. Description of the Related Art Conventional multilayer electronic components have been manufactured by printing a conductor on a green sheet, stacking the sheets and integrally firing the sheets. However, this manufacturing method has a problem that conductor dimensions vary due to variations in sheet shrinkage during firing, and it is difficult to stably mass-produce electronic components having predetermined electrical characteristics.

【0003】そこで、この問題を解決する製法として、
フォトリソグラフを利用する製法が提案された。すなわ
ち、表面を鏡面研磨した焼成済み基板の表面に、フォト
リソグラフにより高精度の導体を形成した後、接着剤を
塗布する。次に、この基板に、別の焼成済み基板を積み
重ね、真空加熱圧着を行って一体化し、製品とする。こ
の製法では、焼成済み基板の表面に導体を形成するた
め、焼成時のシート収縮のばらつきの心配がなくなり、
導体の寸法が高精度になる。
[0003] Therefore, as a manufacturing method to solve this problem,
A manufacturing method using photolithography has been proposed. That is, a high-precision conductor is formed by photolithography on the surface of a fired substrate whose surface is mirror-polished, and then an adhesive is applied. Next, another fired substrate is stacked on the substrate, and vacuum-heat-compression bonding is performed to be integrated to obtain a product. In this manufacturing method, since the conductor is formed on the surface of the fired substrate, there is no need to worry about variations in sheet shrinkage during firing,
The dimensions of the conductor become highly accurate.

【0004】ところが、この製法においては、基板相互
間の接着強度がばらつき、接着強度不足が発生し易いと
いう新たな問題が起きる。そこで、本発明の課題は、基
板相互間の接着強度のばらつきが小さく、かつ、接着強
度の信頼性がアップした積層型電子部品及びその製造方
を提供することにある。
However, in this manufacturing method, a new problem arises in that the bonding strength between the substrates varies, and the bonding strength tends to be insufficient. Accordingly, an object of the present invention is to provide a multilayer electronic component having a small variation in adhesive strength between substrates and improved reliability of adhesive strength, and a method of manufacturing the same.
Is to provide a law .

【0005】[0005]

【課題を解決するための手段と作用】以上の課題を解決
するため、本発明に係る積層型電子部品は、上下面が±
2μmの平滑度を有している複数の焼成済みセラミック
ス基板と、前記複数の焼成済みセラミックス基板の間に
配設された導体とを備え、前記導体を間に挟んだ焼成済
みセラミックス基板が、真空加熱圧着の手段により前記
導体厚の2倍以上の厚さを有する高耐熱性接着剤を介し
て接合していることを特徴とする。セラミックス基板の
材料としては、誘電体、磁性体、半導体のセラミック
ス、あるいはガラスセラミックスが使用される。高耐熱
性接着剤の材料としては、ポリイミド樹脂及びポリアミ
ド樹脂のいずれか一つが使用される。導体としては、例
えば、ストリップ線路がある。また、本発明に係る積層
型電子部品の製造方法は、上下面が±2μmの平滑度を
有している複数の焼成済みセラミックス基板の間に導体
を配設し、前記導体を間に挟んだ焼成済みセラミックス
基板を、前記導体厚の2倍以上の厚さを有するポリイミ
ド接着剤及びポリアミド接着剤のいずれか一つの高耐熱
性接着剤を介して、真空加熱圧着の手段により接合する
ことを特徴とする。高耐熱性接着剤は、スピンコータに
て焼成済みセラミックス基板表面に塗布される。
In order to solve the above problems, a laminated electronic component according to the present invention has a structure in which the upper and lower surfaces are ±
A plurality of fired ceramic substrates having a smoothness of 2 μm, and a conductor disposed between the plurality of fired ceramic substrates, wherein the fired ceramic substrate sandwiching the conductor is a vacuum. It is characterized in that bonding is performed by means of thermocompression bonding via a high heat resistant adhesive having a thickness of at least twice the conductor thickness. As a material for the ceramic substrate, a dielectric, a magnetic, a semiconductor ceramic, or a glass ceramic is used. As a material of the high heat resistant adhesive, any one of a polyimide resin and a polyamide resin is used. As the conductor, for example, there is a strip line. In the method for manufacturing a multilayer electronic component according to the present invention, a conductor is disposed between a plurality of fired ceramic substrates having upper and lower surfaces having a smoothness of ± 2 μm, and the conductor is sandwiched between the substrates. The baked ceramic substrate is bonded by means of vacuum heat compression through one of a polyimide adhesive and a polyamide adhesive having a heat resistance of at least twice the conductor thickness. And The high heat resistant adhesive is applied to the surface of the fired ceramic substrate by a spin coater.

【0006】以上の構成において、高耐熱性接着剤の厚
みを導体の厚みの2倍以上に設定したことにより接着面
の凹凸が小さくなる。従って、接着界面に形成される隙
間が小さくなり、真空加熱圧着の際における接着剤の塑
性変形量が少なくても、充分その隙間が接着剤によって
埋められることになり、接着不具合が減少する。
[0006] In the above configuration, by setting the thickness of the high heat resistant adhesive to be at least twice the thickness of the conductor, the unevenness of the bonding surface is reduced. Therefore, the gap formed at the bonding interface is small, and even if the amount of plastic deformation of the adhesive during the vacuum heating and pressure bonding is small, the gap is sufficiently filled with the adhesive, thereby reducing bonding defects.

【0007】[0007]

【実施例】以下、本発明に係る積層型電子部品及びその
製造方法の一実施例について添付図面を参照して説明す
る。本実施例では、ストリップラインフィルタを例にし
て説明する。図1に示すように、ストリップラインフィ
ルタ15は2枚の焼成済みセラミックス基板1,6を接
着して構成されるものである。セラミックス基板1,6
は、絶縁体粉末とバインダーを混練したものを成形した
後、焼成したものである。セラミックス基板1,6は、
その上下面が鏡面研磨されており、板厚が0.6mm、
上下面が±2μmの平滑度を有している。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer electronic component according to the present invention and the same will be described.
One embodiment of the manufacturing method will be described with reference to the accompanying drawings. In the present embodiment, a strip line filter will be described as an example. As shown in FIG. 1, the strip line filter 15 is formed by bonding two fired ceramic substrates 1 and 6. Ceramic substrates 1, 6
Is obtained by kneading an insulator powder and a binder, molding the mixture, and firing the mixture. The ceramic substrates 1 and 6
The upper and lower surfaces are mirror polished, the plate thickness is 0.6 mm,
The upper and lower surfaces have a smoothness of ± 2 μm.

【0008】セラミックス基板1の上下面にはフォトリ
ソグラフ技術により、それぞれ一対のストリップ線路
2,3及びグランド導体4が形成されている。なお、フ
ォトリソグラフ技術は周知の技術である。ストリップ線
路2の引出し部2aはセラミックス基板1の左側縁部に
露出し、引出し部2bは基板1の手前側縁部の左寄りの
位置に露出している。ストリップ線路3の引出し部3a
はセラミックス基板1の右側縁部に露出し、引出し部3
bはセラミックス基板1の手前側縁部の右寄りの位置に
露出している。グランド導体4はセラミックス基板1の
全面に形成されている。これらストリップ線路2,3及
びグランド導体4は、Ag,Ag−Pd,Cu等からな
る。
A pair of strip lines 2 and 3 and a ground conductor 4 are formed on the upper and lower surfaces of the ceramic substrate 1 by photolithography. The photolithographic technique is a known technique. The lead portion 2a of the strip line 2 is exposed at the left edge of the ceramic substrate 1, and the lead portion 2b is exposed at a position on the left side of the front edge of the substrate 1. Leader 3a of strip line 3
Is exposed on the right side edge of the ceramic substrate 1 and the drawer 3
b is exposed at a position on the right side of the front edge of the ceramic substrate 1. The ground conductor 4 is formed on the entire surface of the ceramic substrate 1. The strip lines 2 and 3 and the ground conductor 4 are made of Ag, Ag-Pd, Cu, or the like.

【0009】以上の2枚のセラミックス基板1,6は以
下に説明する手順により接着される。スピンコータにて
セラミックス基板1の上面に溶融状態の高耐熱性かつ熱
可塑性ポリイミド接着剤を均一に塗布する。同様にし
て、セラミックス基板6の下面にもポリイミド接着剤を
均一に塗布する。このとき、セラミックス基板1,6に
塗布されるポリイミド接着剤の厚みは、セラミックス基
板1と6を接着した後のポリイミド接着剤層14(図2
及び図3参照)の厚みがストリップ線路2,3の厚みの
2倍以上になるように設定される。従って、ポリイミド
接着剤は比較的厚めに塗布されることになる。
The above-mentioned two ceramic substrates 1 and 6 are bonded by the procedure described below. A high heat-resistant and thermoplastic polyimide adhesive in a molten state is uniformly applied to the upper surface of the ceramic substrate 1 by a spin coater. Similarly, the polyimide adhesive is uniformly applied to the lower surface of the ceramic substrate 6. At this time, the thickness of the polyimide adhesive applied to the ceramic substrates 1 and 6 is determined by the polyimide adhesive layer 14 (FIG. 2) after the ceramic substrates 1 and 6 are bonded.
And FIG. 3) is set to be twice or more the thickness of the strip lines 2 and 3. Therefore, the polyimide adhesive is applied relatively thickly.

【0010】ポリイミド接着剤を塗布されたセラミック
ス基板1,6は150℃の温度で1時間予備乾燥され、
ポリイミド接着剤の溶媒成分を除去する。セラミックス
基板1に塗布されたポリイミド接着剤の表面は凹凸が小
さい。これは、厚めに塗布されたポリイミド接着剤がセ
ラミックス基板1の上面に設けたストリップ線路2,3
による段差を殆んど吸収するからである。一方、セラミ
ックス基板6に塗布されたポリイミド接着剤の表面は、
殆んど凹凸がない。
The ceramic substrates 1 and 6 coated with the polyimide adhesive are pre-dried at a temperature of 150 ° C. for one hour.
The solvent component of the polyimide adhesive is removed. The surface of the polyimide adhesive applied to the ceramic substrate 1 has small irregularities. This is because the thicker polyimide adhesive is applied to the strip lines 2 and 3 provided on the upper surface of the ceramic substrate 1.
This is because most of the steps due to the above are absorbed. On the other hand, the surface of the polyimide adhesive applied to the ceramic substrate 6 is
Almost no irregularities.

【0011】次に、セラミックス基板1,6を、ストリ
ップ線路2,3が間に配設されるように、ポリイミド接
着剤を塗布した面を合わせて積み重ね、真空加熱圧着す
る。セラミックス基板1,6に塗布されたポリイミド接
着剤の表面は凹凸があっても小さいので、接着界面に形
成される隙間が小さくなり、真空加熱圧着の際における
接着剤の塑性変形量が少なくても、充分その隙間が接着
剤によって埋められることになり、図2及び図3に示す
ように、接着不具合のないポリイミド接着剤層14が形
成される。こうして、セラミックス基板1,6がポリイ
ミド接着剤層14を介して接合した構造のストリップラ
インフィルタ15が得られる。このストリップラインフ
ィルタ15の左側端面部には、ストリップ線路2の引出
し部2aに電気的に接続された状態で入出力電極7が設
けられている。同様に、右側端面部には、ストリップ線
路3の引出し部3aに電気的に接続された状態で入出力
電極8が設けられている。手前側の端面部にはグランド
電極9,10,11が設けられている。
Next, the ceramic substrates 1 and 6 are stacked together with their surfaces coated with a polyimide adhesive so that the strip lines 2 and 3 are disposed therebetween, and are vacuum-heat-pressed. Since the surface of the polyimide adhesive applied to the ceramic substrates 1 and 6 is small even if it has irregularities, the gap formed at the bonding interface is small, and even if the amount of plastic deformation of the adhesive during vacuum heating and pressure bonding is small, Then, the gap is sufficiently filled with the adhesive, and as shown in FIGS. 2 and 3, the polyimide adhesive layer 14 having no adhesion failure is formed. Thus, a strip line filter 15 having a structure in which the ceramic substrates 1 and 6 are joined via the polyimide adhesive layer 14 is obtained. An input / output electrode 7 is provided on the left end surface of the strip line filter 15 in a state of being electrically connected to the lead portion 2a of the strip line 2. Similarly, an input / output electrode 8 is provided on the right end face portion while being electrically connected to the lead portion 3a of the strip line 3. Ground electrodes 9, 10, and 11 are provided on the end face on the near side.

【0012】図4はストリップラインフィルタ15の等
価電気回路図である。ストリップ線路2が有するインダ
クタンスL1及びストリップ線路2とグランド導体4の
間に形成されるキャパシタンスC1が一方の共振回路を
構成し、ストリップ線路3が有するインダクタンスL2
及びストリップ線路3とグランド導体4の間に形成され
るキャパシタンスC2が他方の共振回路を構成してい
る。二つの共振回路は相互インダクタンスMにて電気的
に結合している。
FIG. 4 is an equivalent electric circuit diagram of the strip line filter 15. The inductance L1 of the strip line 2 and the capacitance C1 formed between the strip line 2 and the ground conductor 4 constitute one resonance circuit, and the inductance L2 of the strip line 3
The capacitance C2 formed between the strip line 3 and the ground conductor 4 constitutes the other resonance circuit. The two resonance circuits are electrically coupled by a mutual inductance M.

【0013】さらに、セラミックス基板1,6に塗布さ
れるポリイミド接着剤の厚みを種々に変えて製作したサ
ンプルの接着強度試験及びヒートサイクル試験の結果に
ついて説明する。この試験において、真空加熱圧着の条
件は、真空度を10-2Torr、加熱温度を350℃、
圧力を10kg/cm2に設定した。また、ストリップ
線路2,3の厚みは、7μmである。ヒートサイクル試
験は、−55℃の温度に30分間放置した後、125℃
の温度に30分間放置することを1サイクルとし、これ
を100サイクル繰り返した。接着後のポリイミド接着
剤層14の厚みが2〜13μmの範囲では、接着強度が
1kg/mm2以下であった。そして、ストリップ線路
2,3の周辺部を切り出して顕微鏡観察すると、図5に
示すように、接着界面に隙間17a,17bが発生して
いた。また、ヒートサイクル試験後のサンプルには接着
界面に剥れが観察された。
Further, the results of an adhesive strength test and a heat cycle test of samples manufactured by varying the thickness of the polyimide adhesive applied to the ceramic substrates 1 and 6 will be described. In this test, the conditions of the vacuum heating and compression bonding were as follows: the degree of vacuum was 10 −2 Torr, the heating temperature was 350 ° C.,
The pressure was set at 10 kg / cm 2 . The thickness of the strip lines 2 and 3 is 7 μm. The heat cycle test was carried out at a temperature of −55 ° C. for 30 minutes and then at 125 ° C.
Letting it stand at this temperature for 30 minutes was defined as one cycle, and this was repeated 100 cycles. When the thickness of the polyimide adhesive layer 14 after bonding was in the range of 2 to 13 μm, the bonding strength was 1 kg / mm 2 or less. Then, when the peripheral portions of the strip lines 2 and 3 were cut out and observed with a microscope, gaps 17a and 17b were generated at the bonding interface as shown in FIG. Further, in the sample after the heat cycle test, peeling was observed at the bonding interface.

【0014】一方、接着後のポリイミド接着剤層14の
厚みが14〜24μmの範囲では、接着強度が1kg/
mm2以上あり、ストリップ線路2,3の周辺部を切り
出して顕微鏡観察をしても、図6に示すように、接着界
面には隙間は見られなかった。また、ヒートサイクル試
験後のサンプルにも何ら異常は認められなかった。な
お、本発明に係る積層型電子部品及びその製造方法は前
記実施例に限定されるものではなく、その要旨の範囲内
で種々に変形することができる。
On the other hand, when the thickness of the polyimide adhesive layer 14 after bonding is in the range of 14 to 24 μm, the bonding strength is 1 kg / kg.
mm 2 or more, and even when the peripheral portions of the strip lines 2 and 3 were cut out and observed with a microscope, no gap was observed at the bonding interface as shown in FIG. No abnormality was observed in the sample after the heat cycle test. The multilayer electronic component and the method of manufacturing the same according to the present invention are not limited to the above-described embodiment, but can be variously modified within the scope of the invention.

【0015】溶融状態の高耐熱性接着剤を必ずしも使用
する必要はなく、シート状の高耐熱性接着剤を2枚の基
板の間に挟み、真空加熱圧着することにより、基板を接
着するものであってもよい。材質もポリアミド接着剤で
あってもよい。また、前記実施例はストリップラインフ
ィルタについて説明しているが、必ずしもこれに限定さ
れるものではなく、インダクタ、コンデンサ、LCフィ
ルタ等の積層型電子部品であってもよい。
It is not necessary to use a high-heat-resistant adhesive in a molten state, and a sheet-like high-heat-resistant adhesive is sandwiched between two substrates, and the substrates are bonded by vacuum heating and pressure bonding. There may be. The material may be a polyamide adhesive. Further, although the above-described embodiment describes a stripline filter, the present invention is not limited to this, and may be a laminated electronic component such as an inductor, a capacitor, or an LC filter.

【0016】[0016]

【発明の効果】以上の説明で明らかなように、本発明に
よれば、高耐熱性接着剤の厚みを導体の厚みの2倍以上
に設定したので、接着面の凹凸が小さくなり、接着界面
に形成される隙間が小さくなる。従って、真空加熱圧着
の際における接着剤の塑性変形量が少なくても、充分そ
の隙間が接着剤によって埋められることになり、接着不
具合が減少して接着強度の信頼性が向上する。また、外
気に含まれている水分やフラックス等のガスが接着面か
ら部品内部に侵入しにくくなるため、導体が水分やフラ
ックスによる侵食から保護される。
As is apparent from the above description, according to the present invention, since the thickness of the high heat resistant adhesive is set to be twice or more the thickness of the conductor, the unevenness of the bonding surface is reduced. Thus, the gap formed at the bonding interface becomes smaller. Therefore, even if the amount of plastic deformation of the adhesive during the vacuum heating and pressure bonding is small, the gap is sufficiently filled with the adhesive, thereby reducing bonding defects and improving the reliability of the bonding strength. In addition, since it is difficult for gas such as moisture or flux contained in the outside air to enter the inside of the component from the bonding surface, the conductor is protected from erosion by moisture or flux.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る積層型電子部品の一実施例を示す
組立て斜視図。
FIG. 1 is an assembled perspective view showing one embodiment of a multilayer electronic component according to the present invention.

【図2】図1に示したストリップラインフィルタの外観
を示す斜視図。
FIG. 2 is a perspective view showing an appearance of the strip line filter shown in FIG.

【図3】図2のIII−III断面図。FIG. 3 is a sectional view taken along the line III-III of FIG. 2;

【図4】図2に示したストリップラインフィルタの等価
電気回路図。
FIG. 4 is an equivalent electric circuit diagram of the strip line filter shown in FIG. 2;

【図5】試験サンプルのストリップ線路周辺部の拡大断
面図。
FIG. 5 is an enlarged cross-sectional view around a strip line of a test sample.

【図6】試験サンプルのストリップ線路周辺部の拡大断
面図。
FIG. 6 is an enlarged cross-sectional view around a strip line of a test sample.

【符号の説明】[Explanation of symbols]

1…セラミックス基板 2,3…ストリップ線路 6…セラミックス基板 14…高耐熱性接着剤層 15…ストリップラインフィルタ DESCRIPTION OF SYMBOLS 1 ... Ceramic substrate 2, 3 ... Strip line 6 ... Ceramic substrate 14 ... High heat resistant adhesive layer 15 ... Strip line filter

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭54−104555(JP,A) 特開 昭55−65280(JP,A) 特開 昭58−204521(JP,A) 特開 平4−111304(JP,A) 特開 平5−14101(JP,A) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-54-104555 (JP, A) JP-A-55-65280 (JP, A) JP-A-58-204521 (JP, A) JP-A-4- 111304 (JP, A) JP-A-5-14101 (JP, A)

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 上下面が±2μmの平滑度を有している
複数の焼成済みセラミックス基板と、前記複数の焼成済
みセラミックス基板の間に配設された導体とを備え、前
記導体を間に挟んだ焼成済みセラミックス基板が、真空
加熱圧着の手段により前記導体厚の2倍以上の厚さを有
するポリイミド接着剤及びポリアミド接着剤のいずれか
一つの高耐熱性接着剤を介して接合していることを特徴
とする積層型電子部品。
A plurality of fired ceramic substrates having upper and lower surfaces having a smoothness of ± 2 μm; and a conductor disposed between the plurality of fired ceramic substrates. The sandwiched and fired ceramic substrate is joined by means of vacuum heating and pressure bonding via a high heat resistant adhesive of one of a polyimide adhesive and a polyamide adhesive having a thickness of at least twice the conductor thickness. A laminated electronic component characterized by the above-mentioned.
【請求項2】 前記導体がストリップ線路であることを
特徴とする請求項1記載の積層型電子部品。
2. The multilayer electronic component according to claim 1, wherein said conductor is a strip line.
【請求項3】 上下面が±2μmの平滑度を有している
複数の焼成済みセラミックス基板の間に導体を配設し、
前記導体を間に挟んだ焼成済みセラミックス基板を、ス
ピンコータにて前記焼成済みセラミックス基板表面に塗
布されてなる前記導体厚の2倍以上の厚さを有するポリ
イミド接着剤及びポリアミド接着剤のいずれか一つの高
耐熱性接着剤を介して、真空加熱圧着の手段により接合
することを特徴とする積層型電子部品の製造方法。
3. A conductor is provided between a plurality of fired ceramic substrates whose upper and lower surfaces have a smoothness of ± 2 μm,
Any one of a polyimide adhesive and a polyamide adhesive having a thickness of at least twice the conductor thickness obtained by coating the fired ceramic substrate with the conductor interposed therebetween on a surface of the fired ceramic substrate by a spin coater. A method of manufacturing a laminated electronic component, comprising joining the two electronic components by means of vacuum heat compression through two high heat resistant adhesives.
JP30396893A 1993-12-03 1993-12-03 Laminated electronic component and method of manufacturing the same Expired - Fee Related JP3209304B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30396893A JP3209304B2 (en) 1993-12-03 1993-12-03 Laminated electronic component and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30396893A JP3209304B2 (en) 1993-12-03 1993-12-03 Laminated electronic component and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH07161583A JPH07161583A (en) 1995-06-23
JP3209304B2 true JP3209304B2 (en) 2001-09-17

Family

ID=17927452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30396893A Expired - Fee Related JP3209304B2 (en) 1993-12-03 1993-12-03 Laminated electronic component and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3209304B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002204072A (en) 2000-12-28 2002-07-19 Sanyo Electric Co Ltd Composite laminated ceramic board and manufacturing method thereof
US6987307B2 (en) * 2002-06-26 2006-01-17 Georgia Tech Research Corporation Stand-alone organic-based passive devices
US7489914B2 (en) 2003-03-28 2009-02-10 Georgia Tech Research Corporation Multi-band RF transceiver with passive reuse in organic substrates
WO2019013585A1 (en) * 2017-07-14 2019-01-17 주식회사 아모텍 Multifunctional element and electronic device comprising same
JP6874601B2 (en) * 2017-08-28 2021-05-19 Tdk株式会社 Coil parts and their manufacturing methods

Also Published As

Publication number Publication date
JPH07161583A (en) 1995-06-23

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