JPS61251950A - Interface unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention provides a host computer that includes a first data bus, an address bus, and a first control/signal line; The present invention relates to an interface device that controls the transmission of commands and data to and from a disk control device, which includes second, third, and fourth control-signal lines.

BACKGROUND OF THE INVENTION A common means of storing large amounts of data is a disk storage device and/or a floppy disk accessed by a disk controller. Such disk controllers (e.g. Data Technology's DTC510A)
510B) has a data bus and a control signal line, but does not have an address bus. therefore,
The transmission of commands and data between a host computer, which has a data bus, an address bus, and control and signal lines, and a disk controller of the type described above is not possible due to the lack of addressability.

[Problems to be Solved by the Invention] An object of the present invention is to solve the problem caused by the lack of addressability and to provide an interface device that can control the transmission of such instructions and data. do.

[Means for solving the problem] The object comprises a first internal bus and a second internal bus, which are connected for a first transmission direction via a first controllable buffer. , connected via a second controllable buffer for the second transmission direction, the first check bit generator and the second check bit generator being coupled to the first internal bus; one data bus is connected to a second internal bus through a third controllable buffer, the second data bus is connected to the first internal bus through a fourth controllable buffer, and the second data bus is connected to the first internal bus through a fourth controllable buffer; The bus and the first, second and third control-signal lines are connected to the interface controller, and the third and fourth control-signal lines and the output of the second check bit generator are connected to the disk controller. an error signal line serving to transmit a status word indicating each state of the check bit is connected to the second internal bus via a fifth controllable buffer; A sixth controllable buffer is coupled to the disk controller by a line, and the interface control is accomplished by an interface unit connected to each controllable buffer by an internal control and signal line.

Further advantageous embodiments of the invention are described in the subclaims.

[Embodiment] An interface device according to an embodiment of the present invention shown in FIG. 1 includes a first data bus PDAT00-07,
A host computer connected to the interface device by an address bus P A D R00-07 and a first control/signal line 5SL1, a second data bus W D A T 00-07 and a second, third and Fourth control/signal line 5SL2.5SL3.

5SL4 to control the transmission of commands and data between the disk controller DC and the disk controller DC connected to the interface device. This disk control device controls access to the device and/or the floppy disk from a disk (not shown).

The interface device of FIG. 1 comprises a first internal bus A and a second internal bus B, which are connected in the 10-1 transmission direction via a first controllable buffer 'DI' and in the second are connected to each other in the transmission direction via a second controllable buffer D1.

Further, a first check bit generator D8 and a second check bit generator D9 are coupled to the first internal bus A.

A first data bus PDATOO-07 (the bus coming from the host computer DMCP) is connected to the second internal bus B via a third controllable buffer D3, and a second data bus WDATOO-07 (the bus coming from the disk controller The bus coming from DC) is connected to the first internal bus A via a fourth controllable buffer D4.

Address bus PADROO-07, first control and signal line 5SLI for transmitting address and control signals
(both coming from the host computer DMCP) and the second and third control/signal lines 5SL2.8SL3
(both coming from the disk controller DC) are connected to the interface control wJ device DCr. This interface controller DCI is connected to a controllable buffer by internal control and signal lines.

For transmission of a status word (STATUS BYTE) indicating the respective status of the disk controller DC
A fourth control/signal line 5SL3-5SL4 and an error signal line FPAR are connected to the second internal bus B via a fifth controllable buffer D5. The error signal line FPAR is connected to the output of the second check pit generator D9.

The first and second check pit generators D8°D9 are also coupled to a sixth controllable buffer D6, which is connected to the check pit line WPA.
It is connected to the disk controller DC by R.

A seventh controllable buffer D7 is connected to a fixed potential and to the least significant bit line DBO of the first internal bus. By means of an additional internal control and signal line EN3, the seventh controllable buffer D7 is controlled such that the least significant bit line DBO is connected to a logic level providing a fixed potential.

In the embodiment described here, the first control/signal line 5SL
1 consists of the following:

Write enable signal line PWR Read enable signal line PRD First selection signal line PSEL Interrupt signal line PINTO First request signal line PREQ1 First reset signal line PRES The second control/signal line 5SL2 is composed of the following: ing.

Second selection signal line WSEL Second reset signal line WR8T Acceptance signal line WACK The third control/signal line 5SL3 is composed of the following.

Busy signal line WBUSY Command acceptance signal line WMSG The fourth control/signal 1!5SL4 is composed of the following.

Input/output signal line WI10 Command/data signal line WC/D Second request signal line WREQ As shown in the block diagram of FIG. 2, the interface control device DCI includes a command decoder CDE, a selection logic device SE,
Interrupt and DMA (Direct Memory Access) Control Unit (hereinafter referred to as DMA unit) IOC and Control Logic Unit C
It is equipped with L.

Instruction decoder CDE is connected to address bus PAD R00
- It is connected to the host computer by 07 and the first selection signal line PSEL, and converts the supplied address into a corresponding command. These instructions are on the first command line RESE
T, second command line 5ETSELECT, third command line R
ESETSELECT1 4th command line SET DBO
, is transmitted on the fifth command line RESET DBO to the selection logic unit SE, and on the sixth command line READSTATUS
BYTE=ENS is transmitted to both the selection logic SE and the control logic CL, and the seventh command line GET
BYTE AND 8TH INSTRUCTION = 13- CONTROL LOGIC UNIT CL AND D ON LINE 5END
It is transmitted to both the MA device and the CC. 6th command line RE
AD 5TATUS BYTE=EN5 and 7th
The command lines GET BYTE overlap internal control and signal lines connected to the fifth controllable buffer D5 and the second controllable buffer D2, respectively.

The first command line RESET is not directly connected to the selection logic device SE, but is coupled together with the first reset signal line PRES and the internal reset circuit GA3 to a logic gate D16, which receives the reset signal one at a time. It is passed to the control logic unit SE.

The selection logic device SE also has a second reset signal line WR8T.
and is connected to the disk controller i&DC by a second selection signal line WSEL. The output of the selection logic SE is coupled back to the input of the selection logic SE via a ninth command line PWR. 10th command line EN3
connects the other output of the selection logic device SE to the control logic device CL,
and a seventh controllable buffer D7 as an additional internal control/signal line.

The DMA device IOC is connected to the host computer DMCP by a first request line PREQ1, an interrupt signal line PINTO and a first reset signal line PRES, and a second request signal line WREQ, an input/output signal line WI10 and an instruction/data line. It is connected to the disk controller flDc by a signal line WC/D. The second check pit generator D9 is connected to the DMA device IOC by an error signal line FPAR.

The control logic device CL has a write enable signal line PWR.
, are connected to the host computer DMCP by a read enable signal line PRD.

The output of the control logic CL is coupled back to the input of the control logic OL via an eleventh command line EN1. 12th command line CACK and 13th command line WRE
Via Q+ the control logic unit OL is connected to the DMA unit IOC. The eleventh instruction 11Etl and the first, second, third, fourth, and fifth logic signal lines EN4. D.I.
R4゜EN7. DIR7 and WRIST are connected to the outputs of control logic CL. 11th command line EN1
and a fifth logic signal line WRIST are connected to the first controllable buffer D1, and the first and second logic signal lines EN4. DIR4 is the third controllable buffer D3
are connected to the third and fourth logic signal lines EN7. D.I.
R7 is connected to a fourth controllable buffer D4 and a sixth controllable buffer D6.

The control of command and data transmission by the interface device according to the invention will be explained by the following functions.

・Resetting the disk controller DC ・Occupying the disk controller @DC ・Status word (S
Transmission of commands/data between the host computer DMCP and the disk controller DC By addressing the address bus PADROO-07, the host computer DMCP reads the command decoder CD
E decodes the reset command, which is transmitted on the first command line RESET through the logic gate [ ) 16 to the selection logic SE.

Furthermore, the reset command can be transmitted from the host computer DMCP on the first reset signal line PRES or from the internal reset circuit GA3 to the logic gate D16 and from there to the selection logic device SE. The selection logic device SE is connected to the disk controller 1DC by a second reset signal line WR8T, so that it can be restored to a defined initial state. At the same time, the DMA device IOC connected to the output of logic gate D16 is reset.

In order to occupy the disk controller DC, the following operational steps must be performed. First, the least significant bit line DBO of the second data bus W D AT 00-07
is activated (low level). For this purpose, the host computer DMCP uses an address bus PAD R00-07.
A setting command for the least significant bit line DBO is sent to the command decoder CDE. The instruction decoder CDE transmits the decoded instructions on the fourth instruction line SET_DBO to the selection logic unit SE. The selection logic SE therefore activates the tenth command line EN3 and if the ninth command line P
If WR+ is also energized, it is "low level"), 7th
energizes the least significant bit line DBO of the first internal bus A via the controllable buffer D7.

At the same time, the control logic OL is activated via the tenth command line EN3, so that the third and fourth logic signal lines EN
7. DIR7 is also energized. Accordingly, the fourth controllable buffer D4 is activated and the level supplied from the least significant bit line DBO of the first internal bus A is switched to the second data bus WDATOO-07. The least significant bit line DBO of the second data bus W D AT 00-07 remains energized until reset by the host computer.

In the next step, the second selection signal line WSEL is activated. As in the previous step, the host computer DMCP sends a set command on the address bus to the command decoder CDE, which transmits the decoded command on the second command line SET 5ELECT to the selection logic SE. The selection logic SE energizes the second selection signal line WSEL (low level), thereby occupying the disk controller DC.

As operation continues, a status word (STATUS' BYTE) indicating the status of the disk controller DC is read by the host computer. The latter sends the read command on the address bus PADR'00-'07 to the command decoder CDE, which sends the decoded command to the sixth command line READSTATUS B.
Control logic O by YTE=EN5 (low level)
L and the fifth controllable buffer D5. The status word (STA
TUSBYTE), the following information is input via the signal line connected to this buffer.

Status word Bit O: Busy signal (WBUSY) Bit 1: Input/output signal (WIlo) Bit 2: Command/data signal (WC/D') Bit 3: Command consent signal (WMSG> Bit 4 Factory error signal (FPAR) ) Bit 5: Second request signal (WREQ) Bit 6.7:
The low level of bit 6.7 coupled to the operating low level is the fifth
controllable buffer D5 (in response to an instruction at EN5) and provided on the second internal bus B.

At the same time, the control logic device @CL connects the first and second logic signal lines EN4. A third controllable buffer D by DIR4
3 so that a status word (STATUSBYTE) is applied to the first data bus PDATO'0-07 and transmitted to the host computer DMCP. The host computer DMCP writes the status word (STATUS).
BYTE>, and after receiving a signal indicating that the disk controller DC is occupied (BIT 0=WBUSY), the command decoder C issues a reset command to the second selection signal line WSEL via the address bus PADROO-07.
DE, which command decoder CDE transmits the decoded command via a third command line RESET 5ELECT to the selection logic SE. This selection logic device ft5E
deactivates the second selection signal line WSEL.

The host computer DMCP then sends a reset command to the least significant bit line DBO of the second data bus WDATOO-07 to the address bus PAD R00-07.
to the fifth command line RESET DBO for the command decoder CDE and the selection logic SE. The selection logic device SE resets the tenth command line EN3 and also resets the third and fourth logic signal lines EN7. through the control device CL. U) Reset IR7 and reset the seventh controllable back 7-D7 (responsive to the signal at EN3) and the fourth controllable buffer D4 (EN7
and DIR7) are the first internal bus A and the second data bus W D A T respectively.
The energization of the least significant bit line DBO of 00-07 is stopped.

For the transmission of words (BYTE) between the host computer DMCP and the disk controller DC, each transmission direction must be specified by a command.

In the first transmission direction, the host computer DMCP sends a word write command (SEND BYTE) by the address bus PADROO-07 to the command decoder CDE, which sends the decoded command by the eighth command line (SENDBYTE). DMA device I
OC and control logic CL.

Word transmission is performed by activating the first request signal line PREQI, which is connected to the thirteenth command line WREQ+,
It is set based on the levels of input/output signal line WI10, command/data line WC/D, and error signal line FPAR. The first request signal line PREQ1 remains set until the host computer DMCP has finished performing the read/write operation.

Read enable signal line PWR and eighth command line 5E
When ND BYTE is activated, the 11th command line E
NI is set by the control logic CL. As a result, cylinder 1, third and fourth logic signal lines EN4. EN7 and DIR7 are activated by control logic CL.

When the write enable signal 1i1PWR and the eighth command line 5END BYTE are activated, the control logic CL likewise sets the twelfth command line CACK and therefore the DMA device IOC resets the first request line PREQ1. do.

The word (BYTE) coming from the host computer DMCP
) is transmitted by the first data bus PDATOO-07 to the second internal bus B through a third controllable buffer D3. Fifth logic signal line WRIST (PWR, 5
At the leading edge of the signal END, activated by BYTE) is input into the first controllable buffer D1.

If the eleventh command line EN1 is activated, the stored data word is then transmitted on the first internal bus A to the first check bit generator D8 and also to the fourth controllable through the buffer D4 (energized by EN7.DIR7) to the second data bus WDA.
to T 00-07, hence the disk controller DC
transmitted to.

At the same time, the first check bit generator D8 generates a check bit for the data word and passes it through a sixth controllable buffer D6 (energized by EN7°DIR7) to the disk control on the check pit line WPAR. Sent to device DC.

After the data has been sent to the disk controller DC, this disk controller DC resets the level of the second request signal line WREQ, so that the eleventh command line EN1 and therefore the first, third and fourth logic Signal lines EN4, EN7
, D IR7 is reset by the control logic CL.

In the second direction of transmission, the host computer DM
The CP sends the word read command (GET BYTE) to the command decoder CD via the address bus PADROO-07.
This instruction decoder CDE sends the decoded instruction to DM via the seventh instruction line (GET BYTE).
It is transmitted to both the A device 1-CG and the control logic device CL.

For word transmission, the first request signal line PREQ1 is connected to the thirteenth command line WREQ+, input/output signal line WI10,
It is activated as described above in response to the levels of command/data line WC/D and error signal line FPAR.

Read enable signal line PDR and seventh command line GE
When T BYTE is activated, the first and second logic signal lines EN4 and DIR4 and the third logic signal line EN7 (through WIlo) are set by the control logic OL.

Words coming from the disk controller DC are thus passed by the second data bus W D AT 00-07 through the fourth controllable buffer D4 (energized by EN7) to the first internal bus A. transmitted and stored in a second controllable buffer D2 and a second check pit generator D9. Hello, get the 7th command line
If BYTE is activated, the stored word is then passed on the second internal bus B through the third controllable buffer D3 (activated by EN4°DIR4) to the first data bus P. D A T 00-07 and thus to the host computer DMCP.

At the same time, the second check bit generator D9 generates a check bit and applies it to the error signal line FPAR.

In case of a bit error, the DMA device IOC sends an interrupt command to the host computer DMCP via the interrupt signal line PINTO. The reset command causes the entire operation to be repeated as described above.

Read enable signal line PDR and seventh command line GE
When T BYTE is activated, the control logic CL sets the twelfth command line 0AGK and therefore the DMA device I
OC resets the first request signal line PREQ1.

To ensure accurate transmission between the host computer DMCP and the disk controller 26 DC, a signal is sent to the disk controller DC indicating that each operation has been performed.

Since the write enable signal line PWR or the read enable signal line PRD is activated when the eighth command line 5ENDBYTE or the seventh command line GET BYTE is activated, respectively, the control logic CL converts the grant signal into a grant signal. It is sent to the disk controller DC via the line WACK.

The acceptance signal line WACK remains set until the thirteenth command line WREQ+ is set. Second request signal line W
Activation of REQ allows the acknowledge signal line WACK to be set during the next operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the interface device of the present invention, and FIG. 2 is a detailed block diagram of the interface device shown in FIG. DMCP...Host computer, DC...Disk control device, D1-D7...Controllable buffer, D
8. D9...Check bit generator, DCI...
Interface control device, CDE...instruction decoder, SE...selection logic device, IOC...DMA device,
CL...control logic device, GA3...reset circuit,
[)16...Logic gate.

Claims (10)

[Claims] (1) First data bus, address bus, and first control bus.
control the transmission of instructions and data between a host computer having a signal line and a disk controller having a second data bus and second, third and fourth control/signal lines; The interface device comprises a first internal bus and a second internal bus, which are connected via a first controllable buffer for a first transmission direction and connected for a second transmission direction through a first controllable buffer. a second controllable buffer, the first check bit generator and the second check bit generator are coupled to the first internal bus, and the first data bus is connected to the third internal bus. the second data bus is connected to the first internal bus through a fourth controllable buffer, the address bus and the first, second and a third control-signal line is connected to the interface controller, and a status word is connected to the third and fourth control-signal lines and the output of the second check bit generator to indicate each state of the disk controller. An error signal line serving to transmit the data is connected to the second internal bus via a fifth controllable buffer, and the first and second check bit generators are connected to the disk controller by the check bit line. an interface device connected to a sixth controllable buffer coupled to a sixth controllable buffer, the interface control device being connected to each controllable buffer by an internal control/signal line. (2) the first control/signal line is a write enable signal line, a read enable signal line, and a first selection/signal line;
The interface device according to claim 1, comprising an interrupt signal line, a first request signal line, and a first reset signal line. (3) the second control/signal line is the second selection/signal line;
a second reset signal line and a consent signal line;
The control/signal line includes a busy signal line and a command acceptance signal line, and the fourth control/signal line includes an input/output signal line;
2. The interface device according to claim 1, further comprising a command/data signal line and a second request signal line. (4) the seventh controllable buffer has a fixed potential and the first
connected to the least significant bit line of an internal bus and configured to control additional internal control and signal lines such that the least significant bit line is at a logic level representing a fixed potential. Any one of range 1 to 3
Interface device as described in Section 1. (5) A patent comprising an instruction decoder, a selection logic device, an interrupt and DMA (direct memory access) control device, and a control logic device, which are interconnected by a command line. An interface device according to claim 1. (6) An address bus and a first selection/signal line are connected to an instruction decoder, and the instruction decoded according to the address transmitted from the host computer to the instruction decoder on the address bus is transmitted to the first instruction line; transmitted on a second command line, a third command line, a fourth command line, and a fifth command line to the selection logic, and transmitted on a sixth command line to both the selection logic and the control logic; transmitted on a seventh command line and an eighth command line to both the selection logic unit and the interrupt and DMA control unit, the sixth command line and the seventh command line also forming two internal control signal lines; 6. Interface device according to claim 2 or 5, characterized in that it is connected to a fifth and a second controllable buffer, respectively. (7) a selection logic device is connected to the first reset signal line, the second reset signal line, and the second selection/signal line;
The output of the selection logic is connected to the input of this selection logic via a ninth command line, and the tenth command line connects the selection logic to the control logic and the seventh as an additional control signal line.
An interface device according to claim 3, 4 or 6, characterized in that the interface device is connected to both controllable buffers. (8) The interrupt and DMA control device has a first request signal line, an interrupt signal line, a first reset signal line, a second request signal line, an input/output signal line, an instruction/data signal line, and an error signal line. 8. The interface device according to claim 7, wherein the interface device is connected to the interface device. (9) the output of the control logic unit is coupled to the input of the control logic unit via an eleventh command line, and the control logic unit provides interrupt and DMA control via a twelfth command line and a thirteenth command line; an eleventh command line and a first, second, third, fourth, and 9. The interface device according to claim 8, wherein the five logic signal lines form six internal control signal lines. (10) the first reset signal line, the first command line, and the internal reset circuit are connected to the selection logic device such that the reset signal can be provided to the selection logic device one at a time; Claim 3 characterized by
6. The interface device according to any one of paragraphs 5 and 6.