JPS6125191A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Technical field 1 The present invention relates to improvement and unification of display control devices.

``Background technology'' In the past, compared to CRT, liquid crystal (hereinafter referred to as r
(called LCDJ) was small. For example, a CRT can display 80 characters x 25 lines per screen, but
The LCD could only display 40 characters x 4 lines. For this reason, the display control device for LCD and the display control device for CRT are completely different, and it has been impossible to use one display control device in common with the other display control device.

By the way, in recent years, hand belt computers (hereinafter referred to as r
H) (referred to as CJ) has become popular, and the display device of this H1-IC uses an LCD display device because of the need for low power consumption. In this case, the IcDs are divided into two parts in the upper and lower directions of the screen, and are arranged in close contact with each other to perform parallel display. HHC is becoming more sophisticated and functional, and the display performance of LCD is approaching that of CRT. Therefore, in 1@HC, l-
There is a need for a display control device that can drive CD and CRT image display devices. The reason for this request is that although LCDs and CRTs currently perform completely different display controls, LCDs and CRTs can essentially perform the same display control. This is because there is.

[Problems with the Background Art] However, in reality, first, the display specifications of the LCD are physically fixed (for example, the number of horizontal scanning lines is
Since there is no need for vertical or horizontal retrace lines in the case of LCDs, there is no need for vertical or horizontal retrace lines in the case of LCDs.
A problem with CDs is that, similar to CRTs, it is not possible to perform sufficient display control.

Further, conventionally, since LCD- cannot display WAm (halftone), there is a problem that it cannot display the same as OR'T.

Furthermore, since the display clock speed of L and CD is generally slow, the speed of the display control device is slow, and memory access from the CPU is also slow, resulting in a problem that the performance of the device is lower than in the case of CR7 display. be.

Furthermore, since conventional display control devices do not allow the addition of external registers, there is a problem in that when configuration control is required, a large number of circuits are required for this.

Furthermore, when using conventional software, if the device has expanded functions, there is a problem that the expanded functions cannot be protected when the software is executed.

[Object of the Invention] The present invention has been made by focusing on the above-mentioned conventional problems, and realizes various specifications while completely maintaining software compatibility, and improves gradation in LCD display. The purpose of the present invention is to provide a display control circuit that can perform display, achieve the same level of access as CR7 display, enable configuration control, and provide protection when functions are expanded in conventional software. It is.

[Summary of the Invention] The present invention provides mode selection means for selecting a CRT display mill mode or a liquid crystal display control mode, a means for executing display control of the CRT, and a means for executing display control of the liquid crystal. It has the means to do so.

[Embodiments of the invention] FIG. 1 is a block diagram showing one embodiment of the present invention.

L CD C10 is LS [that controls the display of LCD or CRT. This LCDC 10 includes a CRT controller 11, a driver 12 that amplifies data signals, etc.
Attribute Graphic 13, Alpha 14,
Color selector 15 and color palette 16 for color conversion
, a composite color generator 17 , and a mode collect register 71 . CRT controller 1
No. 1 generates a timing signal based on parameters set. The color selector 15 outputs a 4-pin digital signal specifying a color when a color CR-r is used as the display means 20. ] The digital color generator 17 performs D/A conversion in order to create the Y signal and the 7-digit RGB signal 8, and output signals according to each mode of LCD types 1 to 3. is generated.

cocio also controls the internal control register 18
and the circuit shown in FIG.

As the display means 20, a CRT or a CD is used.

Outside the LCDClO, there is a VRAM (Videt A RAM) 30 made of DRAM or SRAM, and an address latch 31 that latches the address signal from the CPLI.
Data latch 3 latches data from LCDC10
2, a character generator 33 that converts character information into dots based on the signal from the data wrap-32;
An external control register 34 is provided which receives data from the internal control register 18.

Next, an outline of the operation of the above embodiment will be explained.

FIG. 2 is a diagram showing all of the 10 registers provided in the LCDClO. This I10 register has the functions of a plurality of mutually different registers.

Here, in order to display characters on the CRT serving as the display means 20, data signals from the CPU 6s (not shown) are once written into the VRAM via the driver 12. CR
-r C10 is a VRAM in accordance with the synchronization and scanning of CR1.
30 is read repeatedly. This read data is latched into the data latch 32, and the data is converted into dots by the character generator 33 and alpha 14.
It is converted into a color signal by the color selector 15 and sent to the CRT.
sent to. Further, when it is desired to perform color conversion, the color palette 16 is used, and the digital signal is subjected to UD/A conversion by the converter 1 to the color generator 17, and the Y signal is sent to the CRT.

On the other hand, when an LCD is used as the display means 20, the composite color generator 17
/A The display is controlled by another operation without being converted. This operation will be described later. Na J3, L C
When using D, the signal sent to the LCD is:
In FIG. 1, the interface between the LCDC 10 and the display stage 20 is shown enclosed in parentheses.

In this way, the above interface connects CRT and LC.
It is shared with D.

D()IEX is input to the I10 register as an address signal.
) In other words, when rllolJ is sent, the data "P, D6......" will be sent as shown in the table in Figure 2.

DOJ can be written. This data specifies a register that functions as an address for the register bank shown in FIG. Here, the above rPJ is a protect bit which will be described later, but apart from this, [D
6. . . . 7 bits of DOJ are the same as the address shown in FIG. 3, and the correspondence between this address and the functions of each register is also shown in FIG.

For example, [D6.・・・・・・・・・The 7 bits of DOJ are
[If it is 1100101J, the 7-bit data in FIG. 1, which selects the mouse when it reads ``1'' and selects the light pen when it reads ``0'', are stored in SRAM (static RAM) such as VRAM 30 shown in Figure 1. ) or DRAM (dynamic RAM)
- is a bit that selects S.
Select RAM, and when it is 1-0, select DRAM
This is the choice. Bit 5 is a bit for selecting LCD or CRT for the display means 20, and when it is "1", it selects LCD, and when it is rOJ, it selects CRT.

On the other hand, [D6 at address D (HEX) in FIG.
．． ......, the 7 bits of DOJ are "110".
0110'', the 8-bit data in FIG. 3 functions as a register for test h/L CD control/raster adjustment. In this case, bits 5, 4 . ．． 3.2 is a selection pin for LCD types 1 to 3 (each of these types will be described later).
The bits l-1 and 0 are bits for selecting the amount of the vertical display position (raster azirest), which will be explained in FIG.

FIG. 4 is a diagram showing a vertical display position adjustment circuit.

The vertical display position adjustment circuit 40 includes a shift register 41 and a selector 42. The shift register 41 receives a vertical synchronizing signal and a horizontal synchronizing signal of 0.1.・・・・・・、
It outputs signals that avoid 5 and 6, respectively. The output signal having the same timing as the input horizontal synchronization signal becomes the upper frame signal F[M(U). These upper frame signals FL, M(U) are used to remove dimming when scanning the upper liquid crystal 43 (see FIG. 4B) provided above the screen in the vertical direction.

The selector 42 selects the output signal of the shift register 41 and sends it out as the lower frame signal FLY(L). The lower frame signal M (L) is used to take timing when scanning the lower liquid crystal display 44 (see Figure 4B) installed at the bottom of the screen in the vertical direction, and it determines the number of scanning lines on the screen. Accordingly, the display phase of the lower liquid crystal 44 is changed with respect to the display phase of the upper liquid crystal 43. In the case of the embodiment, the display phase of the lower liquid crystal 44 lags behind the display phase of the lower liquid crystal 43. Note that by arranging the upper liquid crystal 43 and the lower liquid crystal 44 in close contact with each other, 'C1
It consists of two screens.

For example, as shown in Figure 4B, a 640x204 L
When using a CD and displaying a 640x200 screen, it is necessary to lower the display section 43d by two scanning lines as the border 43b of the upper liquid crystal 43. , Therefore, the lower frame signal FLM(L) is delayed by two scanning lines. This state is shown in FIG. 4A.

In FIG. 4, the raster adjust 0 signal (indicated by RAJO in FIG. 3) and the raster adjust 1 signal (indicated by RAJl in FIG. 3)
By varying the lower frame signal QFLM
The amount of delay in (U) can be controlled. In other words, raster adjust O@, 5 star adjust 1-1 signals, ro, OJ
, ro, IJ.

For rl, OJ, Il, and IJ, the number of delayed lines is 0, 2, and 4.6 lines, respectively. By appropriately adjusting the number of delays, it is possible to prevent a break in the display portion between the upper liquid crystal 43 and the lower liquid crystal 44.

FIG. 5 is a detailed circuit diagram of the composite color generator 17. This circuit 17 generates a display control signal for displaying a CRT and a display control signal for displaying an LCI. It generates three types of control signals.

The D/Δ converter 17a converts the R', G, and B digital signals received from the color palette 16 into analog signals, and the converted analog signals are used as display control signals for the CRT. be done. The adder 17b receives R, G, and B sent from the color palette 16.
It inputs each digital signal, performs the calculation ('4G+2R+8), weights the result of the calculation, and outputs it as a binary value with a predetermined number of bits. The D/A converter 17c converts the output signal of the adder 17b into an analog signal and outputs it to CR1- as Y(1, number (luminance signal)).

Furthermore, the lff1 pull circuit 17d converts the due cycle of the voltage applied to the LCD for each driver 1, depending on the brightness of the driver 1 to be displayed on the LCD. , determine the output value for each direct scan (thinning)
・It is b. This thinning circuit 17d is composed of a ROM, and its output signal is display control data for LCD type 1 (described later), and this signal is sent to the shift register 52 (see FIG. 5C). It will be done.

The field counter 17e receives the vertical synchronization signal from
The result is output with 3 pins.

The output signals of these three pits and the output of the adder 17b (it
Based on the upper 4 bits of the number, the decimation circuit 176
3, and executes the above thinning operation. .

The series-parallel-1 inverter 17f is a thinning circuit 17d.
This converts the output signal into a 4-bit parallel signal. The output signal of this inverter 17f is a display delay signal for LCD type 2 (described later), and this signal is sent to a shift register 53 (see FIG. 5C).

The latch circuit 1.7g is for latching the upper 4 bits of the output signal of the adder 17d, and is for outputting a bright weight signal for the LCD. This latch circuit 17
The output signal of g is a display data signal for LCD type 3 (described later), and this signal is sent to a shift register 54 (see FIG. 5C).

Referring to FIG. 5C, there is shown a diagram showing how the full registers are arranged in each type of LCD segment driver.

In these figures, shift registers 52, 53, 54
The latches that are present between the two and the liquid crystal 43 are omitted from illustration.

The WCK weight clock circuit exists in the CRT controller 11, and generates the weight clock WCK by counting down the SCK clock according to the EH bits of bits 4 to 0 of address 67 (HEX) in FIG.

The j-th figure △ shows a method b in which the thinning circuit 17d is used to control the application of the voltage R for each vertical scan of the screen in units of one dot. This is L
This is type 1 of CD. That is, the same number of knobs 70 and knobs 52 as the number of dots in the horizontal direction of the liquid crystal 43 (for example, 320 dots) are provided to constitute one serial shift register.

The output signal from the thinning circuit 17d is sequentially applied to this shift register to perform a predetermined display.

The fifth diagram shows 5'-light when 8-step gradation control is performed for LCD types 1 and 2. That is, a predetermined number of fields out of eight fields are thinned out according to the luminance, and when the thinning is performed, no voltage is applied to the dots concerned. This allows the average brightness to be controlled in eight levels.

Here, predetermined fields (e.g. 8 fields)
, and focus on a predetermined dot between the eight fields. Then, the Itogi scale that makes the brightness of that dot the highest applies a voltage to all of the 8 fields to the one-norm flop 52 corresponding to that dot. bit r111
It is shown as J. Increase the brightness to medium high! When this happens, select the flip flop corresponding to that dot.
2 is thinned out by a predetermined number of times (for a predetermined field). This is shown in the fifth diagram, for example, as bit r 100 J. In other words, it is thinned out by 3 fields from the back of 8 fields.

This thinning operation is executed by the thinning circuit 176.

On the other hand, in FIG. 5, the LCD type 1 shown in FIG. One shift register is constructed by a predetermined number of shift registers, that is, a plurality of parallel shift registers are shown. This is type 2 LCD. By doing this, the power consumption of the flip-flop 53 is lower than that of type 1 LCD.

In this case as well, the principle explained in Figure 5 applies. In FIG. 5B, one shift register is composed of 80 flip-flops, and a total of four shift registers (
The following is an example in which there are cases (indicated by ■, ■, ■, ■). The measurement information from the thinning circuit 17d is ■, ■, ■,
The data are stored in the order of (2), and the switching is performed by the clock ECK.

Further, FIG. 5C shows an arrangement in which the application of voltage to the liquid crystal 43 is controlled by giving the minimum unit time of the brightness width to each dot.

This is type 3 LCD. The minimum unit time of the luminance width is, for example, 1/16 of a half cycle of the alternating current signal (the time to drive one dot or the time to drive one line). We use 4 bits to do this, each bit being 1.2, 4. .

It has a meaning of 8 times the weight width, that is, each bit is given a weight. Then, for each dot, the minimum time and weight width are combined in accordance with the 4-bit value to control the voltage application time.

An example of the relationship between the output signal of the latch circuit 17g and the drive waveform of the ICD is shown in FIG. 5E.

That is, within one horizontal scanning time, a voltage is applied to the liquid crystal according to the brightness for an integral multiple of the minimum unit time of the width of the brightness. This allows the average brightness to be controlled in 16 levels. In the case of FIG. 5E, a voltage is applied to the liquid crystal with a predetermined duty waveform in accordance with the alternating current signal having -i-'2.5■, -2,5■, etc.

In the CRT controller 11, pulses WO, W1 . W3 is created. The pulse WO is a pulse corresponding to the minimum unit time of the brightness bite width. Pulses wi, w2, W3 are each 2.4. of pulse WO. a(g).If the output signal of the latch circuit 17g is rllllJ, it is preferable that the alternating current signal be applied for the entire one horizontal scanning time, but there may be some gaps. may exist.

That is, 10n (n is an integer from 0 to 7, and this LDn is sent from the shift register 54) shown in FIG.
(digital information consisting of 4 bits) and the pulses WO, W1, W2 . W
The LCD is controlled based on the signal processed by the logic circuit.Specifically, four AND circuits and one OR circuit are provided, and LDO and WO are connected to the first AND circuit. LDI and Wl are processed in the second AND circuit, 1.D2 and W2 are processed in the third AND circuit, and L, D3 and W3 are processed in the fourth AND circuit. The output signal of the four AND circuits described in 1.1- is processed by O
The output signal is input to the R circuit, and the brightness of the LCD is controlled based on the output signal of this OR circuit.

In this way, a plurality of dot intermediate brightnesses (halftones) can be set.

FIG. 6 is a chart showing display control signals for each display means.

This chart shows display control signals generated for CRT and CD types 1 to 3, respectively. Here, VSYNC is the vertical synchronization signal, and H8YN
C is a horizontal synchronization signal, LC is a clock that takes out the video signal from the shift register to the latch, SCK is the clock that puts the video signal into the shift register, and E
CK is a clock that enables the LCD driver, and WCK is a way l-clock that is a unit of luminance weight. B, G, R, and Y are respectively a blue primary color luminance signal, a green primary color 14 degree signal, a red primary color luminance signal,
This is a monochrome luminance signal. Mat=, cl-1 are color phase signals, and M is an alternating current signal. In addition, LJ, L in the figure
are symbols indicating upper liquid crystal and lower liquid crystal, respectively.

FIG. 7 is a diagram showing the relationship between CPU time slots and display time slots.

FIG. 7(1) shows a CPU time slot and a CRT display time slot, and both time slots occur repeatedly with approximately the same length. On the other hand, FIG. 7(2) shows the CPU time slot and the LCD display time slot, and the length of the CPU time slot is approximately 3 times the length of the CD display time slot.
It is set to double.

Regarding m71i4(2), overall, the total time of the CD display time slot is shortened, and the total time of the CPU time slot is lengthened.

This is because the access speed of L Cl) is closer to that of CRT in general, so there is no problem even if the LCD display time slot is slightly spaced, and the free time created by J2 is used as the CPU time slot. This is to speed up the operation of CP jJ.

FIG. 7A is a diagram showing a memory access speed-up circuit during liquid crystal display.

In this figure, the basic clock from the basic clock circuit 61 is transmitted to the CRT timing signal generation circuit 62 and the LC.
The signal is sent to the D timing signal generation circuit 63. CRT
The nLC timing signal generation circuit 62 sends the CRT row address select signal CRAS and the CRT column address select signal CCAS to the selector 64
) timing signal generation circuit 63 for LCD [1-
The address select signal LRAS and the column address select signal @LCAS for LCD are sent to the selector 64.

Further, the selector 65 selects a CRT/LC display indicating whether to use a CRT or an LCD as the display means 20.
Upon receiving the DvJ detection signal, the CR signal is sent to the selector 64.
Row address select signal CRAS or LCD for T
The row address select signal RAS for CRT is output as the row address select signal RAS, and the column address select signal CCAS for CRT or the column address select signal LCAS for l-CD is output as the column address select signal CAS. .

As a result, the time slot shown in FIG. 7D(1) when using the indicated size CRT and the time slot shown in FIG. 7(2) when using the -i1-CD are switched and used. During one cycle of repeated memory access, in the time slot when CRT is used, there are two CP (J time slots), whereas in the time slot when LCD is used, there are three CPU times CPU processing becomes somewhat faster.In the figure, CPU
U is CPU time slot, (CRT is (CRT time slot, L, CD is 1., CI) time slot 1
-1 ([) indicates an even number, and (0) [ indicates an odd number.

Incidentally, FIG. 7C shows general time slots 1 to 1 when using a CRT. In the figure, ROW indicates a row address signal (Y), and COI- indicates a column address signal.

Figure 7B shows that the CPU address when L, Cl) is displayed is C.
It is a circuit diagram that is slower than CPU access during RT display. 1 In this circuit, when the basic clock is sent as is to the timing signal generation circuit 67, the time slot 1 using rJCRT shown in FIG. After dividing the frequency by 1/2 and sending it to the timing signal generation circuit 67, the time slot state when using a CRT as shown in FIG. 7D(3)' is achieved.

The circuit shown in FIG. 7 allows faster memory access when using an IcD than the circuit shown in FIG. 7B.

FIG. 8 is a circuit diagram showing an external control register.

In the figure, internal ]n 1 to roll register 18 are L
The external register 34, which is provided inside the LCDC 10, is located outside the LCDC 10. Both control registers 18.3/I are connected to each other via a data bus. The gate 35 accepts data when the horizontal synchronization signal is output. Therefore, the external control register 3
4 can receive data from the internal control register 18 when the horizontal synchronization signal is generated.

Various uses of the external control register 34 are conceivable; for example, it may be used to store a signal for selecting between CRT and LCD, or may be used as an external page register. Therefore, that external control register 3
4 has the advantage that the configuration &lJ III is possible.

FIG. 8 is a time chart showing the relationship between the horizontal synchronization signal and the data bus signal. FIG. 8B is a diagram showing display timing and synchronization signal timing. In this figure, the shaded portion is the timing of the synchronization signal.

Note that a vertical synchronization signal may be used instead of the horizontal 1i' and the 1st period IR. These pulses are collectively referred to as sl~1 cop pulses.

By providing the external control register 34 as shown in FIG. 8, there is an advantage that there is no need to increase the number of IC bins and no new peripheral components are required.

FIG. 9 is a circuit diagram for protecting predetermined bits.

In the figure, the mode select register 71 is shown in LCDCl0 in FIG. 1, and receives a write strobe signal from the CPU to address 8 (HFX).
It takes in and outputs eight mode selection signals corresponding to -0 to 7. The write strobe signal is output from port 8 (HEX) of the I10 register shown in FIG. The output terminals of bits 6 and 7 have
AND circuits 72 and 73 are connected to each.

Here, bit 6 has the meaning of extended function 160×200 color mode, and bit 7 has the meaning of standby mode. A N circuit 7
The other end of 2.73 is applied with the signal of the protect bit rPJ, which is the port D()IEX) of the I10 register shown in FIG. 2, that is, pins 1-7 of the register bank address.

That is, when protect bit 1-rPJ is [1], bit 6.7 of mode select register 71 is output as is, and conversely, when protect bit rPJ is "0", mode select register 71 bit 6.7
is not output. That is, if the protect bit is set, the extended bit is ignored.

Therefore, in the past, for example, the above-mentioned pins 1-6 and 7 were not used, so there are software products on the market that can be used without worrying about the pins 1-6 and 7. It is expected that there will be. In other words, in the above example, it is h6. '7 is not defined, so they are '1
'', or 0, but I don't know if there is any (・) However, when functions are expanded, it is generally difficult to maintain compatibility between various programs, but in that case, Even in this case, it is only necessary to set the first bit "P" to rOJ, so there is an advantage that the operation to ensure the compatibility of the software is very easy.

"Effects of the Invention" The present invention is suitable for rough 1~wear! While maintaining complete compatibility, various specifications can be realized, and since gradation display is possible on an LCD display, it can be used to the same extent as a CRT display, and configuration control is possible. ,moreover,
This has the effect that it is possible to protect a conventional software when its functions are expanded.

[Brief explanation of the drawing]

Fig. 1 shows an embodiment of the present invention, Fig. 2 is a functional explanatory diagram of the I10 register, Fig. 3 is an explanatory diagram of a register bank, and Fig. 4 is a circuit diagram showing a vertical display position adjustment circuit. , FIG. 4 is a time chart showing the relationship between the data signal and the frame signal, FIG. 4B is a diagram showing the display state on the LCD, and FIG. 5 is a block diagram showing details of the composite color generator. Figure 5 A, B, and C are diagrams showing how the shift registers are arranged in each type of LCD segment 1 to driver. A diagram showing the relationship between the -L-order 3 bits and the field before conversion, Figure 5F shows the combination of the minimum unit time of luminance, and Figure 6 shows the display control signal for each display means. The diagram shown in Figure 7 is CP
FIG. 7A is a diagram showing the relationship between the U time slot and the display time slot. FIG. 7A is a diagram showing a circuit for accelerating memory access during liquid crystal display. FIG. 7B is a circuit diagram in which memory access is not accelerated during liquid crystal display. Figure 7C is a diagram explaining a general time slot when using a CRT, Figure 7 is a diagram showing one recycle of memory access repetition, and Figure 8 (,1 external double]ton 1-roll register is shown. Figure 8: △ is a time chart of the external register; Figure 8B is a summary diagram of the relationship between the horizontal synchronization signal and the data bus signal; Figure 9 is a diagram showing the protection of specified bits. This is the circuit diagram of No.
17C...O/Δ-]] converter 17d... thinning circuit, 17e... field counter, 17[...
Series-parallel 21 inverter, 18... Internal control register, 19... Address latch/timing generation, 2o... Display means, 30... V RAM, 34
...External control register, 711...Shift register, 42...Selector, 43...Lower liquid crystal,
44...Lower liquid crystal, 52°53.54...Shift register, 71...Mode select register. Figure 5 A Figure 5 C Figure 5 D ° 111 (7) "-1111110 (6) L!-1□□1 (1) L-m-"1-1-j] 8th Figure A Figure 8B Figure 9

Claims (1)

[Scope of Claims] A register having an expanded bit; a register having a protect bit; and means for ignoring the expanded bit when the protect bit is set. A display control device characterized by: