JPS61249163A - Wait cycle generating circuit - Google Patents

Abstract

PURPOSE:To generate the necessary number of weit cycles for each of the special peripheral circuit by providing a ROM and a counter in which the output data of the number of the weit cycle for the address of the peripheral circuit, etc. CONSTITUTION:When a CPU 3 reads and writes a memory or an I/O and a P-ROM 4 fetches the outputted address as the address information of respective peripheral circuits, the number of the weit cycles to be inserted concerning the peripheral circuit is outputted. The number information is preset to a count er 5, and the count value appears at QD-QA. When the high level exists even at one of the output QD-QA, a READY input comes to be a low level, and the weit cycle is inserted. Thus, the CPU 3 temporarily stops the action, and waits until the access can be executed concerning the late memory, the I/O, etc. Thus, since the special peripheral circuit is selected and the necessary number of the weit cycles can be inserted, the unnecessary waiting of the CPU can be eliminated and the action efficiency can be improved.

Description

[Detailed description of the invention] (b) Industrial application fields The present invention is directed to a microprocessor or CPU.

Used in the field of peripheral circuits.

The present invention relates to a wait cycle generation circuit for synchronizing a CPU and an input/output device such as a memory.

(B) Prior Art In microcomputer technology, it is known that the operation of input/output devices such as memory, which is a peripheral circuit thereof, is slower than the operation of a CPU.

Therefore, when inputting and outputting data between these peripheral circuits and the CPU, it is necessary to temporarily delay the operation of the CPU, that is, to make the CPU wait. For this method, 'OJ' is connected to the READY terminal of the CPU.
(L) signal is input, and a wait cycle in which CP and U are in a standby state is inserted into the normal machine cycle.

Conventionally, as a circuit for generating this wait cycle, one has been used that generates the same even number of wait cycles when inputting/outputting to/from all seven peripheral circuits. 3 is a circuit diagram showing one example of such a conventional example. This is for the Intel 8085A CPU, and is quoted from its M manual MC5-85.
This circuit is composed of two D latches 1.2, and a uniform number of wait cycles is determined by the D input.

(c) Problems to be solved by the invention In such conventional examples, wait cycles are generated even for peripheral circuits that do not require wait cycles, and the same number of wait cycles are generated even though fewer wait cycles are required. However, the CPU continues to wait, and therefore the CPU
U's single effort efficiency decreases.

In order to compensate for this drawback of the conventional example, it has been proposed to provide each peripheral circuit with its own wait cycle generation circuit as described above.
This necessitates a complicated circuit configuration such as an increase in control signals between U and peripheral circuits.

An object of the present invention is to solve the above-mentioned problems, and to provide a circuit that generates a necessary number of wait cycles for each specific peripheral circuit.

(d) Means for Solving the Problems The purpose of the present invention is to solve the above-mentioned N points, and to solve the problems described above. ,
Input the CPU clock signal as a count trigger, and when the count matches the ROM output data, the C
This can be achieved by including a circuit that causes the input ready signal to the PU to become H.

In this case, it is preferable that the circuit described above is a presettable counter and that the ROM is a programmable ROM.

(E) Function The ROM according to the present invention receives an address signal corresponding to each peripheral circuit, and a prewritten wait cycle fl! Data is output, and at that time, the CPU's control signal is used as a trigger, and the counter circuit is taken in as a preset input, and the CPU's clock signal is used as a count trigger, and the ROM's output date and count number are When they match, the ready input to the CPU is set to H. Therefore, the CPU is placed in a wait state until the match occurs.

(f) Embodiment A preferred embodiment of the present invention will be explained based on FIG.

Before that, for convenience of explanation, the wait cycle of the CPU will be explained with reference to FIG. Figure 2 shows Intel 8085
2 is a timing example chart of a memory read or I10 read machine cycle in the CPU of FIG.

All signals related to the CPU are processed based on the CPU clock signal. Normally, memory, machining, etc. are slower than the CPU, so if it is necessary to adjust the speed of each single effort, the CPU can control the operation of the CPU by inserting cycles TI&, during the machine cycle. Pause and wait until slow memory, Ilo, etc., becomes accessible.

Cycle T1. , is determined by the CPU.
Use the READY input of When the CPU is in T2, check the state of the READY input on the rising edge of the clock. If the READYri issue is high level (H)
If so, the CPU proceeds to cycle T3 and completes instruction execution.

If the READY signal is low level (L), the CP
U enters cycle TLu and continues to insert cycles T, . . . until the READY signal goes high.

This cycle T, insertion sequence is the same in the memory write or I10 write machine cycle. Note that since addresses A7 to AO and data D7 to DO are input and output from the same pass line in a time-sharing manner, the ALE (address latch enable) signal is set to T to hold addresses A7 to AO.
It is output from the falling edge to the rising edge of the clock in one state. Details are described in the above-mentioned manual.

Therefore, the first F2, which shows a circuit diagram of one embodiment of the present invention, will be explained. 3 is a CPU, 4 is a P-ROM, and 5 is a counter.

When the CPU 3 reads/writes the memory or Ilo, it outputs addresses A15 to AO from the beginning of the machine cycle, as shown in FIG.

When the P-ROM 4 takes in this output as address information for each peripheral circuit, it outputs the number of wait cycles to be inserted for that peripheral circuit as data 04 to 01. When this number information is preset in the counter 5 by the ALE signal, the preset count value is output.
It's covered in frost.

If even one of the outputs ~α has a high level, R
The EADY input goes low and cycle Tw is inserted.

On the other hand, the gate 6 connected to the clock output of the CPU 3 is opened, and the clock output is connected to the grand trigger terminal (T
Enter D) and start the countdown. When the count reaches zero, all of the outputs QD-cb go low, so the READY input to the CPU 3 goes high, and the cycle ends. At the same time, the clock output gate 6 closes and stops counting.

In this embodiment, the circuit configuration is such that cycles TL and 1 are inserted in the I10 circuit, which has a particularly high need for wait cycle generation, but cycles T1 and 1 are also inserted for memory read/write. If you want to insert 1, a larger capacity P-ROM is required. Since high speed performance is required for the P-R and OM used, bipolar type ones are appropriate.

In the embodiment, a P-ROM is used to facilitate address changes and wait cycle number data changes, but a non-programmable ROM may also be used.

Further, in the embodiment, an example is shown for an Intel 8085 CPU, but it is obvious that the present invention can be similarly applied to an Intel 8085 CPU. The signal corresponding to ALE can be adapted by using or combining memory requests, I10 requests, clock outputs, and other CPUflail signals.

Furthermore, although a down counter is used in the example,
Lateral aperture using an up counter is also possible.

(g) Effects According to the present invention, it is possible to select a specific peripheral circuit and insert the required number of wait cycles into that circuit.
There is no unnecessary waiting for the PU, improving the operating efficiency of the CPU, and the use of the IIIP-ROM makes it easy to change the number of addresses and wait cycles.The overall circuit configuration is very simple, especially for general-purpose applications. This is effective when the CPU board and the peripheral device board are each made as independent boards in a board computer, and used in combination for each device to be used.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, Fig. 2 is a CP
The timing chart inside U, FIG. 3 is a circuit diagram of a conventional example. 1 and 2 are latch circuits, 3 is a CPU, and 4 is a ROM. 5 is a counter.

Claims (3)

[Claims] (1) ROM in which output data for the number of wait cycles is written for each address of an input/output device such as memory
and a circuit that inputs a CPU clock signal as a count trigger and causes an input ready signal to the CPU to become H when the count matches output data of the ROM. Cycle generation circuit. (2) The wait cycle generation circuit according to claim 1, wherein the circuit is a presettable counter. (3) The wait cycle generation circuit according to claim 1 or 2, wherein the ROM is a programmable ROM, and its address and output data can be easily changed.