JPS593563A - Timer for evaluation of computer system - Google Patents

Abstract

PURPOSE:To measure the execution time of each part within a CPU with addition of an extremely small quantity of hardware, by providing busy flags and selecting properly one of these flags to start a clock counter. CONSTITUTION:Signals alpha, beta...epsilon showing a working state are supplied to a busy signal register 20 from a function block part which has to measure the execution time within a CPU. The part 20 is connected to an AND gate 60 via AND gates 32-36 and then an AND gate 37. While busy signal selection flags a, b...e are fed to a busy signal selection flag register 31 via a latch 38. These selection flags are connected to the gate 60 via the gates 32-36 and the gate 37. An output of 1 is supplied from the gate 60 when an initialization control bit A in a clock counter 50 is set at 1. Then pulses C are counted until the count value reaches 0. This count value is delivered to buses 11 and 12 via latches 41 and 42, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer for evaluating a computer system.

Although there are various measures for evaluating the performance of digital computers, data processing speed can be said to be the most basic performance evaluation measure. However, this data processing speed varies greatly depending on the processing target and system configuration.
It is quite difficult to understand this clearly. conventionally,
Data processing speed has been evaluated by dividing the processing targets into business calculations and scientific calculations, and considering what is called an instruction mix, which is a combination of average instructions for each. For example, for scientific and technical calculations, Gihzon mix weights the frequency of occurrence of various instructions such as multiplication, comparison, and floating point multiplication.
is commonly used, and comme is used for administrative calculations.
What is called rcial mix is commonly used.

However, data processing speed has many factors that depend on the system configuration, and the frequency of appearance of certain instructions changes considerably depending on how the program is assembled.Especially in scientific calculations, it is necessary to optimize programs to deal with problems. There is a significant difference in the frequency of appearance of various instructions between the case where the command is executed and the case where a general utility program is executed by specifying parameters. Also, since the data processing speed of each part of the central control unit depends on the length of the data, etc.
It is also necessary to make appropriate corrections for . Therefore, in order to improve evaluation accuracy, there is a need for a simple and inexpensive system evaluation timer that can precisely measure the execution time of each part of the central processing unit.

The present invention was made in response to the above request, and its purpose is to create an inexpensive timer for evaluating computer systems that can actually measure the execution time of each part within a central processing unit by adding a very small amount of hardware. Our goal is to provide the following.

The present invention will be explained in detail below using examples.

FIG. 1 shows the configuration of a timer according to the present invention with a computer internal path 10.
2 is a block diagram showing connections with 11 and 12;
0 is a busy signal register, 30 is a busy signal selection circuit,
40 is a clock counter, and 50 is a lock counter control register.

The busy signal register 20 is connected to a central processing unit (not shown).
Memory access control unit in CPIJ), logic operation unit (CPIJ)
A busy signal α indicating that these parts are in operation from the functional block parts whose execution times should be measured, such as ALU), barrel shifters, multipliers, and floating arithmetic units;
AND gate circuits 32, 33, . . . in the busy signal selection circuit 6o receive β...
・Connect to one input terminal of 36. For many of these busy signals, busy signals forming part of the status flags of each part can be used as they are, but for parts where such status flags are not normally created, a separate busy signal creating means is added. The busy signal generating means may be any suitable means, such as a memory access control unit, an ALU
, barrel shifter, multiplier, and floating arithmetic unit are created as follows.

(b) Example of creating a busy signal for the memory access control unit When the memory access control unit receives an access request from the CPU control unit, it sets a flip-flop in the memory access control unit and sends the output signal of this flip-flop to the external bus. Output as a request signal. This request signal is reset by an ACK or NACK signal from the bus controller in the main memory when access to the path ends. Therefore, this request signal can be used as a busy signal.〇(b) ALU,
Example of creating a busy signal for barrel shifter and multiplier The CPU control unit decodes the micro-operation field of the micro-instruction, and outputs the instruction code from the ALU,
Outputs selection signals for barrel shifters and multipliers. A
The LU, barrel shifter, and multiplier operate according to this instruction code and selection signal. Therefore, each selection signal output by the CPU control section can be used as a busy signal for the ALU, barrel shifter, and multiplier, respectively.

(c) Example of creating a signal for a floating calculation unit The floating calculation unit does not complete operation 1 in one cycle of the microinstruction executed by the CPU control unit. In this case, the CPU control section decodes the micro-operation field of the micro-instruction and outputs an instruction code and an operation start request signal to the floating operation section.

The floating arithmetic unit sets this arithmetic start request signal to the flip-flop, and resets it when the arithmetic operation is completed. Therefore, the output of this flip-flop can be used as a busy signal.

The busy signal selection flag register 51 in the busy signal selection circuit 50 receives busy signal selection flags α, b, . written. These busy signal selection flags are AND gates 32, 33...
- Coupled to the other input terminal of '56. The outputs of these AND gates are coupled to one input terminal of AND gate 60 via OR gate 57. This and gate 6
The counter start/stop bit B in the clock counter control register 50 is coupled to the other input terminal of 0. The clock counter control register 50 stores the initialization control bit A and the above-mentioned start/stop bit B via the internal path 10 and the latch circuit 51 based on input from a program or an external input device. When the initialization control pin A becomes "1", the pulse generator 55 generates a counter clear pulse, and the contents of the clock counter 40 are cleared. The clock counter 40 has its ENAB
When the LE terminal receives an output of "1" from the AND gate 60, it starts counting the clock pulse C input to the CLK terminal, and stops counting when the output of the AND gate 60 becomes "0".

The count value of the clock counter 40 is determined by the latches 41 and 42.
are output to internal buses 11 and 12, respectively.

Only one of the busy signal selection flags α to - written in the busy signal selection flag register 31 becomes "1" at the same time. The selected one enables the clock counter 40 via the OR gate 37 and the AND gate 60. Therefore, by appropriately changing the contents of the busy signal selection flags α to -, there are two desired busy signals C, which can be set to " The clock counter 40 can measure the time during which the clock is kept at 1'', that is, the execution time of a desired portion within the CPU.

FIG. 2 is a block diagram of another embodiment of the busy signal selection circuit 30 shown in FIG. be. In this embodiment, the busy signals α to 6 can be selected by the three-person AND gates 72 to 76 using both the selection flags α to e in the register 31 and the switches 82 to 86. There is an advantage that the actual measurement of the operating time of a specific portion can be stopped by operating the switches 82 to 86 from the outside depending on the collection situation.

Note that this embodiment can be further modified to remove the busy signal selection flag register 31 and use only the switches 82 to 86 to select the busy signal.

FIG. 3 is a block diagram showing the configuration of still another embodiment of the busy signal selection circuit 50 shown in FIG. It is the same as that in FIGS. 1 and 2. In this embodiment, the flags α to − in the busy signal selection flag 31 correspond to the signals input from the switches 82 to 86 and the OR gate 9.
After the logical OR is performed on the signals 2 to 96, the signals are coupled to one input terminal of the AND gates 32 to 36. With this configuration, switch 8 can be connected externally depending on the data collection situation.
2 to 86 has the advantage that it is possible to additionally measure the operating time of a specific portion.

In the embodiment shown in FIG. 1, a busy signal register 20 is provided, but such a register may be omitted by directly coupling the busy flag of the ALU, etc. in the central processing unit to the AND gates 32 to 36. You can also do it.

As explained above in detail, the present invention has a configuration in which a busy flag is provided for each functional block in the central processing equipment to indicate that it is in operation, and one of them is appropriately selected to start the clock counter. Therefore, there is an advantage that the execution time of each part of the central processing unit can be actually measured using an extremely simple and inexpensive eight-domain configuration.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of one embodiment of the present invention, and Figures 2 and 3 are block diagrams showing the configuration of other embodiments of the busy signal selection circuit 30 shown in Figure 1. 20... Busy signal register, 30... Busy signal selection circuit, 31... Busy signal selection flag register,
40... Clock counter, 50... Clock counter control register. Agent Patent attorney Gobe Tamamushi (6 others) Figure 2 Figure 3

Claims (1)

[Claims] In a computer system, a busy flag is provided for each functional block of a central processing unit to indicate that the functional block is in operation, and one of the busy signals causes a clock counter to start counting. A computer system evaluation timer characterized by the following.