JPS61247017A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS61247017A
JPS61247017A JP8776785A JP8776785A JPS61247017A JP S61247017 A JPS61247017 A JP S61247017A JP 8776785 A JP8776785 A JP 8776785A JP 8776785 A JP8776785 A JP 8776785A JP S61247017 A JPS61247017 A JP S61247017A
Authority
JP
Japan
Prior art keywords
groove
semiconductor film
semiconductor
stress
overhang
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8776785A
Other languages
Japanese (ja)
Inventor
Takahisa Sakaemori
貴尚 栄森
Shuichi Matsuda
修一 松田
Kenji Sugimoto
謙二 杉本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8776785A priority Critical patent/JPS61247017A/en
Publication of JPS61247017A publication Critical patent/JPS61247017A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02428Structure
    • H01L21/0243Surface structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To make it possible to manufacture a semiconductor device of high reliability avoiding the generation of cracks and warps, by forming previously a groove in the scribed part of the semiconductor substrate and dispersing the internal stress of the semiconductor film formed on the groove. CONSTITUTION:The concave groove 3 is formed on the scribed part of the semiconductor substrate 1 by etching, and the semiconductor film 2a is formed on the groove. As the shape of the groove is concave, the semiconductor film 2a is continuously formed along the groove, but the chain of molecules constituting the semiconductor film 2a, the source of stress, decreases to the amount corresponding to the fall of the groove, and the stress is reduced. In the case where the groove 4 in the form of an overhang is formed on the scribed part of the semiconductor substrate 1 by etching, and the semiconductor film 2a is formed on the groove, the semiconductor film 2a is divided by the overhang part because of the overhang shape of the groove 4. Consequently, the chain of molecules constituting the semiconductor film 2a is also divided and the stress is still more reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法に係シ、特に、半導体
基板上に半導体膜を形成したときのストレスの緩和方法
に関するものである0 〔従来の技術〕 第3図は従来方法で半導体基板上に半導体膜を形成した
場合の状態を示す模式断面図で、図において、(1)は
半導体基板、(2a)及び(21))はその上にスパッ
タリングまたはCVDなどで形成され、それぞれ圧縮応
力及び引張シ応力を生じた半導体膜を示す。第3図(a
)は圧縮応力(図では−で示す)を生じた半導体膜(2
a)の場合、第3図(b)は引張シ応力(図では←で示
す)を生じた半導体膜(2b)の場合を示す0半導体基
板(1)は多層下部構造を有している場合も、有してい
ない場合も含む。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for alleviating stress when a semiconductor film is formed on a semiconductor substrate. [Technology] Figure 3 is a schematic cross-sectional view showing the state when a semiconductor film is formed on a semiconductor substrate by a conventional method. 2 shows a semiconductor film formed by sputtering or CVD, and has compressive stress and tensile stress, respectively. Figure 3 (a
) is the semiconductor film (2
In the case of a), FIG. 3(b) shows the case of the semiconductor film (2b) with tensile stress (indicated by ← in the figure).0 Case where the semiconductor substrate (1) has a multilayer substructure. This also includes cases where the person does not have one.

すなわち、半導体膜(2)の膜材質、形成方法、形成温
度等によって、膜内に圧縮または引張)応力が生じ、そ
の結果、図(a)及び(1,)のような反シが生じてい
た。
In other words, depending on the film material, formation method, formation temperature, etc. of the semiconductor film (2), compressive or tensile) stress is generated within the film, and as a result, the cracks as shown in Figures (a) and (1,) occur. Ta.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

で1゜ 従来の半導体装置での製造方法も、以上のように、形成
膜の内部応力が生じるが、大きな内部応力がかかると、
たとえばクラック等を生じさせ、デバイスの信頼性を低
下させる。また、ウェーハのそりは、パターン転写時に
ウェーハの一部にパターンずれを生じさせ、重ね合せ精
度を劣化させる等の問題点があった。
In the conventional manufacturing method for semiconductor devices, internal stress occurs in the formed film as described above, but when large internal stress is applied,
For example, it causes cracks and the like, reducing the reliability of the device. Further, warpage of the wafer causes a pattern shift in a part of the wafer during pattern transfer, resulting in problems such as deterioration of overlay accuracy.

この発明は、上記のような問題点を解決するためになさ
れたもので、内部応力をウェーハ内で分散できるととも
に、ウェーハの反シを緩和する半導体装置の1!!造方
法を得ることを目的とする。
This invention was made to solve the above-mentioned problems, and is one of the features of a semiconductor device that can disperse internal stress within a wafer and alleviate the warping of the wafer. ! The purpose is to obtain a manufacturing method.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

この発明に係る半導体装置の製造方法では、半導体基板
のスクライブ部に、凹状の溝またはオーバーハング状の
溝を形成するものである。
In the method for manufacturing a semiconductor device according to the present invention, a concave groove or an overhang groove is formed in a scribe portion of a semiconductor substrate.

〔作用〕[Effect]

この発明では、スクライブ部に形成した溝により、その
上部に形成される半導体膜を凹状、もしくは分断に近い
状態にして、形成膜の内部応力を分散することができる
In this invention, the groove formed in the scribe portion makes the semiconductor film formed thereon concave or nearly divided, thereby dispersing the internal stress of the formed film.

〔実施例〕〔Example〕

第1図はこの発明の一実施例方法で得られた半導体ウェ
ーハを示す断面図で、第3図の従来例と同一符号は同等
部分を示す。この実施例では、半導体基板(1)のスク
ライブ部に凹状の溝(3)をエツチングで形成し、その
上から半導体膜(2a)を形成する0 この場合、溝(3)は凹状であるので、半導体膜(2a
)は溝に沿って連続して形成されるが、ストレスの源で
ある半導体膜(2a)の構成分子のチェーンは凹部の落
差に対応する分だけ減少し、ストレスは弱められる。
FIG. 1 is a sectional view showing a semiconductor wafer obtained by a method according to an embodiment of the present invention, and the same reference numerals as in the conventional example of FIG. 3 indicate equivalent parts. In this example, a concave groove (3) is formed in the scribe portion of the semiconductor substrate (1) by etching, and a semiconductor film (2a) is formed over it. In this case, since the groove (3) is concave, , semiconductor film (2a
) are formed continuously along the groove, but the chain of constituent molecules of the semiconductor film (2a), which is the source of stress, is reduced by an amount corresponding to the height of the recess, and the stress is weakened.

第2図はこの発明の他の実施例方法で得られた半導体ウ
ェーハを示す断面図で、この実施例では、半導体基板(
1)のスクライブ部にオーバーハング状の溝(4)をエ
ツチングで形成し、その上から半導体膜(2a)を形成
する。
FIG. 2 is a sectional view showing a semiconductor wafer obtained by a method according to another embodiment of the present invention.
An overhanging groove (4) is formed in the scribe portion of 1) by etching, and a semiconductor film (2a) is formed thereon.

この場合、溝(4)はオーバーハング状であるので、半
導体膜(2a)はオーバーハング部で分断され、その結
果、ストレスの源である半導体膜(2a)の構成分子の
チェーンも分断され、ストレスは一層弱められる。この
形状で半導体Jl(2a)が完全に分断されなくても、
オーバーハング部直下にできる空隙によって基板(1)
にかかるストレスを緩和する0以上、圧縮応力を生じる
半導体膜(2a)の場合について説明したが、引張シ応
力を生じる半導体膜(2b)の場合にも、勿論同一であ
る。
In this case, since the groove (4) has an overhang shape, the semiconductor film (2a) is divided at the overhang, and as a result, the chain of constituent molecules of the semiconductor film (2a), which is a source of stress, is also divided. Stress is further reduced. Even if the semiconductor Jl (2a) is not completely divided in this shape,
Board (1) due to the gap created directly under the overhang.
Although the case of the semiconductor film (2a) which generates a compressive stress of 0 or more to relieve the stress applied to the semiconductor film (2a) has been described, the same applies, of course, to the case of the semiconductor film (2b) which generates a tensile stress.

〔発明の効果〕〔Effect of the invention〕

以上のように1この発明では半導体基板のスクライブ部
にあらかじめ溝を形成しておくだけで、その上に形成す
る半導体膜の内部ストレスを分散できるので、クラック
や反りの発生を回避でき、信頼性の高い半導体装置を製
造できる。
As described above, 1. In this invention, by simply forming a groove in the scribe portion of a semiconductor substrate in advance, the internal stress of the semiconductor film formed thereon can be dispersed, thereby avoiding the occurrence of cracks and warping, and improving reliability. It is possible to manufacture semiconductor devices with high performance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれこの発明の一実施例方法及
び他の実施例方法で得られた半導体ウェーハを示す断面
図、第3図は従来方法で半導体基板上に半導体膜を形成
した場合の状態を示す模式断面図で、第3図(a)は圧
縮応力発生の場合、第3図(1))は引張り応力発生の
場合を示す0図において、(1)は半導体基板、(2a
)、(2b)は半導体114、(31は凹部(凹形の溝
’) 、(4)はオーバーハング形状の凹部(溝)であ
る。 なお、図中同一符号は同一または相当部分を示す0
FIG. 1 and FIG. 2 are cross-sectional views showing semiconductor wafers obtained by one embodiment method of the present invention and another embodiment method, respectively, and FIG. 3 is a case in which a semiconductor film is formed on a semiconductor substrate by a conventional method. FIG. 3(a) is a schematic cross-sectional view showing a state in which compressive stress is generated, and FIG. 3(1)) is a case in which tensile stress is generated.
), (2b) are the semiconductor 114, (31 is a recess (concave groove), and (4) is an overhang-shaped recess (groove). In addition, the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に成膜技術を用いて上記半導体基板
中にストレスを誘起させる半導体膜を形成するに際して
、あらかじめ上記半導体基板のダイシングライン部内の
少なくとも一部の領域に凹部を形成する工程を有するこ
とを特徴とする半導体装置の製造方法。
(1) When forming a semiconductor film that induces stress in the semiconductor substrate using a film formation technique, a step of forming a recess in at least a part of the dicing line portion of the semiconductor substrate is performed in advance. A method for manufacturing a semiconductor device, comprising:
(2)凹部の形状をオーバーハング形状とすることを特
徴とする特許請求の範囲第1項記載の半導体装置の製造
方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the shape of the recess is an overhang shape.
JP8776785A 1985-04-24 1985-04-24 Preparation of semiconductor device Pending JPS61247017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8776785A JPS61247017A (en) 1985-04-24 1985-04-24 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8776785A JPS61247017A (en) 1985-04-24 1985-04-24 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61247017A true JPS61247017A (en) 1986-11-04

Family

ID=13924114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8776785A Pending JPS61247017A (en) 1985-04-24 1985-04-24 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61247017A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57197836A (en) * 1981-05-29 1982-12-04 Fujitsu Ltd Manufacture of semiconductor device
JPS5871642A (en) * 1981-10-23 1983-04-28 Nec Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57197836A (en) * 1981-05-29 1982-12-04 Fujitsu Ltd Manufacture of semiconductor device
JPS5871642A (en) * 1981-10-23 1983-04-28 Nec Corp Semiconductor device

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