JPS61243528A - Buffer memory controller - Google Patents

Abstract

PURPOSE:To control flexibly a buffer memory to simplify a control circuit of the buffer memory by dividing the buffer memory use state into plural levels and giving meanings to these levels and limiting acceptance of write requests. CONSTITUTION:Control signals 101 and 102 are applied to a write pointer register 11 and a read pointer register 12 of a buffer memory controller respectively, and they are applied to a pointer switch 13 also. Outputs of registers 11 and 12 are inputted to write and read pointer registers 14 and 15 respectively. The output of the register 14 is inputted to the switch 13 and a comparator 17 of a buffer memory use state calculating part 16. The output of the register 15 is applied to the switch 13 and a full adder 18 of the calculating part 16, and the output of the adder 18 is applied to the comparator 17. A write address signal 103 is outputted from the switch 13, and a buffer memory use state display signal 104 is outputted from the calculating part 16, thus simplifying the circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer memory management device that has a write pointer and a read pointer and performs first-in/first-out processing for memory means.

〔overview〕

The present invention provides a memory management device that has a write pointer and a read pointer and performs first-in/first-out processing for memory means, in which the same number of hints is applied to a certain number of upper bit strings of read pointer information. The buffer memory usage status calculation circuit calculates the buffer memory usage status by adding the fixed value of , and expressing the usage status of the buffer memory with a match detection signal (buffer memory usage status display signal) between this result and a fixed number of high-order bit strings of the write pointer information. It is designed to simplify and speed up the process.

[Conventional technology]

Conventionally, the amount of buffer memory used has been determined by calculating the difference between write pointer information and read pointer information. This method requires a subtraction circuit that can perform subtraction for the number of bits of the pointer in order to calculate the difference between two variables.

In addition, when restricting writing to the sofa memory based on the usage amount of the sofa memory, a circuit is required to compare the difference between the write pointer information and the read pointer information with a predetermined fixed value. be.

[Problem that the invention seeks to solve]

Therefore, such a conventional buffer memory management device has the disadvantage that software such as the above-mentioned subtraction circuit and a circuit for performing size comparison increases. In addition, in order to calculate the difference between all bits of two pointer information, it takes a long time to determine the difference between each pointer information, and in addition, time is also required to compare the sizes, which increases the amount of buffer memory used. The disadvantage was that it took a long time to calculate.

SUMMARY OF THE INVENTION The present invention aims to solve these conventional drawbacks and to provide a buffer memory management device that can calculate the usage status of a buffer memory with a simple circuit configuration.

[Means for solving problems]

The present invention provides a buffer memory management device that has a write pointer and a read pointer and performs first-in/first-out processing for memory means, and the buffer memory management device instructs the memory address to be written next. write pointer processing means for storing pointer information and updating this information in response to writing; and successive pointer processing means for storing pointer information indicating the memory address to be read next and updating this information in response to reading. , a means for adding a fixed value of the same number of bits to a fixed number of high-order bit strings of the read pointer information, and a fixed value of the same number of bits of the pointer information of the write pointer processing means and and means for comparing and detecting a match.

Means for adding a fixed value of the same number of bits to a bit string of a fixed number of higher-order bits of pointer information of a read pointer processing means, and comparing the addition result with a fixed number of higher-order bit strings of pointer information of a write pointer processing means. However, it is preferable to have a plurality of means for performing coincidence detection, and to perform coincidence detection for a plurality of fixed values in parallel.

[Effect]

The present invention adds a fixed value of the same number of focuses to a fixed number of upper bit strings of read pointer information, and detects a match between this addition result and a fixed number of upper bit strings of write pointer information. By representing the buffer memory usage state with a coincidence detection signal, it can be realized with simple hardware, and the processing time for calculating the buffer memory usage state can also be shortened.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the buffer memory management device of the present invention. In FIG. 1, control signals 101 and 102 are respectively written to the write pointer control unit 1).
and read pointer control section 12 , and further connected to pointer switch 13 . The output of the write pointer control section 1) and the output of the read pointer control section 12 are connected to a write pointer register 14 and a read pointer register 15, respectively.

The output of the write pointer register 14 is the pointer switch 1
3 and the comparator 1 of the buffer memory usage state calculation unit 16
7 and read pointer register 1
The output of 5 is connected to the pointer switch 13 and the negative input of the full adder 18 of the buffer memory usage state calculation unit 16. A fixed value is connected to the other power of the full adder 18, and the output of the full adder 18 is connected to the other power of the comparator 17. The pointer switch 13 has a sofa memory section (
The write address signal 103 (not shown) is output, and the memory usage state calculation unit 16 (comparator 17) outputs the control signal 1.
Outputs 04.

FIG. 2 is a block diagram schematically showing an information processing device including the buffer memory management device of the present invention. In FIG. 2, a buffer memory section 20, a write request source 30. ．． 3
ON, the read request source 40 is connected via the data bus 100. A buffer memory management device 10 is connected to the buffer memory unit 20 via a write address signal 103. The control unit l controls the buffer memory management device IO and the buffer memory unit 20 via control signals 101 and 102 and a buffer memory usage status display signal 104, and the write request source 30. via write request signals 131 and 132. ．． 3
ON, read request source 4 via read request signal 140
0 are connected respectively.

Next, the operation of the device of this embodiment will be explained.

When the write request source 301 writes data to the buffer memory unit 20, it sets the write request signal 131 to logic 1.1 and issues a write request to the control unit 1. The control unit l monitors the write request signals 131 and 132 and the read request signal 140, and when it confirms that the data bus 100 is not in use, it accepts one request according to the priority order. When the sent buffer memory usage state display signal 104 is logic "1", a part of the write request signal is ignored, thereby selecting a write request according to the buffer memory usage state.

When the write request signal 131 is accepted by the control unit 1, the control unit 1 reports to the buffer memory management device 10 via the control signal 101 that a write operation is in progress. As a result, the pointer switch 13 sends the address to be written in the buffer memory section 20 onto the write address signal 103. Further, the control unit 1 also controls the write request source 30. is given permission to use the data buffer 100, and after a certain period of time, after sending a write signal to the buffer memory section 3, the data bus 1
End the use of 00. On the other hand, write request source 30. teeth,
When data bus use permission is confirmed, write request signal 131
is set to logic "0" and sends write data to the data bus 100-H while receiving the data bus use permission signal. When the writing to the buffer memory section 20 is completed, the control section 1 instructs the write pointer control section 1) to update the contents of the write pointer register 14 in the sofa memory management device 10 via the control signal 101. As a result, write pointer control unit 1), write pointer register 1
4 is updated to indicate the next memory address of the buffer memory section 20. Next, the comparator 17 compares the result of adding a fixed value of the same number of bits to the bit string of the upper fixed number of bits of the read pointer register 15 and the bit string of the updated upper fixed number of bits of the write pointer register 14. , - If the result is a failure, the Sofa memory use state instruction signal 104 is set to logic "1", and if they do not match, it is set to logic rOJ and the registration operation is completed.

Data is registered in the buffer memory section 20, and the read request signal 140 sent from the read request source 40 becomes logic "1".
”, the control unit 1 confirms that the data bus 100 is not in use, and then accepts the read requests in accordance with the priority order. When the control unit 1 receives the read request, it reports to the buffer memory management unit N10 via the control signal 102 that the read operation is in progress. As a result, pointer switch 1
Third, the address to be read from the buffer memory section 20 is sent on the write address signal 103. In addition, the control unit 1
commands the buffer memory unit 20 to send data to the data bus 100'2, and after a certain period of time, the read request source 40
Sends a data write signal to. Next, the control unit 1 instructs the read pointer control unit 12 to end the use of the data bus 100 and to update the contents of the read pointer register 15 in the buffer memory management device 10 via the control signal 102. As a result, the read pointer control unit 12 transfers the contents of the read pointer register 15 to the buffer memory unit 20.
Update to point to the next memory address. Next, the full adder 18 sends the updated read pointer register 15
The comparator 17 adds the bit string with a fixed number of high-order bits and the fixed value with the same number of bits, and the comparator 17 compares this addition result with the hit string with a fixed number of first bits in the - of the write pointer register 14. Bahe sofa memory usage status display signal 10
4 is set to logic "1", and if they do not match, set to logic rOJ and the read operation is completed.

FIG. 3 is a block diagram showing a second embodiment of the present invention. The second embodiment includes a plurality of full adders 18 and comparators 17, and shows a case where a plurality of fixed values are compared. Depending on the state of the buffer memory use state display signal 104 output from these plurality of comparators 17, the state of the panzer memory is changed by the level, and the write request signals 131 and 132 are changed to the above-mentioned half memory state and written based on the level. It is easy to restrict acceptance of requests.

Since one input value is a fixed value, the full adder 18 has 2 input values.
It is not necessary to have a configuration that allows variable input, and a simple and high-speed circuit configuration is possible. FIG. 4 is a diagram showing an example of the circuit configuration of the sofa memory usage state calculating section, in which the read pointer register 15 and the write pointer register 14
is an 8-bit configuration, and a fixed value 1) 1tt is added to the upper 3 bits of the read pointer register 15 and compared with the upper 3 bits of the write pointer register 14. Full adder 18 has read pointer register 1
The comparator 17 inputs the signal of the upper 3 bits of the write pointer register 14.

FIG. 5 is a diagram showing the relationship between the buffer memory usage status display signal 104 outputted in this embodiment, write pointer information, and read pointer information.

In FIG. 5, the shaded area is the area where the buffer memory usage state display signal 104 is logic "1".

〔Effect of the invention〕

As described above, the present invention has the advantage of simplifying and speeding up the buffer memory usage state calculation circuit, and can be easily implemented even in small-scale mask slice LSIs, PLAs, etc.

Further, by dividing the buffer memory usage state into a plurality of levels, assigning meaning to these levels, and restricting acceptance of write requests, there is an effect that the buffer memory can be managed flexibly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an apparatus according to a first embodiment of the present invention. FIG. 2 is a block configuration diagram showing an example of the configuration of an information processing device including the device of the present invention. FIG. 3 is a block diagram showing an apparatus according to a second embodiment of the present invention. FIG. 4 is a diagram showing an example of the circuit configuration of a buffer memory usage state calculating section. FIG. 5 is a diagram showing an example of the relationship between areas where write pointer information, read pointer information, and a buffer memory usage state display signal are logic "1". 1... Control unit, 10... Buffer memory management device,
1)...Write pointer control unit, 12...Read pointer control unit, 13...Pointer switch, 14...
Write pointer register, 15... Read pointer register, 16... Buffer memory usage state calculation unit, 1
7...Comparator, 18...Full adder, 20...Hasophor memory section, 30...Write request source, 40...Read request source, 100...Data bus, 101.102
...Control signal, 103...Write address signal, 1
04... Buffer memory usage status display signal, 131.
132...Write request signal, 140...Read request signal. Patent applicant NEC Corporation ~ Agent Patent attorney Naotaka Ide 5th

Claims (2)

[Claims] (1) In a buffer memory management device that has a write pointer and a read pointer and performs first-in/first-out processing for memory means, the buffer memory management device includes pointer information that indicates the memory address to be written next. write pointer processing means for storing pointer information and updating this information in response to writing; read pointer processing means for storing pointer information indicating the memory address to be read next and updating this information in response to reading; means for adding a fixed value of the same number of bits to the upper fixed number of bit strings of the pointer information; and detecting a match by comparing the above addition result with the upper fixed number of bit strings of the pointer information of the write pointer processing means. A buffer memory management device comprising: means. (2) means for adding a fixed value of the same number of bits to a bit string of a fixed number of uppermost bits of pointer information of the read pointer processing means; The buffer memory management according to claim (1), wherein the buffer memory management is configured to have a plurality of means for comparing bit strings and detecting a match, and detecting a match for a plurality of fixed values in parallel. Device.