JPS61243379A - Ic test system - Google Patents

Abstract

PURPOSE:To obtain an IC test system which enables the switching of digital patterns without causing any dummy cycle, by providing a hand shake logic between amain controller and a digital test section. CONSTITUTION:A command signal GO is applied to a digital test section FC from a main controller MC to switch patterns in addition to a signal RUM/ STOP for controlling the startup/stoppage while a response signal GACK is returned to the main controller MC from the digital test section FC corresponding to the command signal GO. For example, the command signal GO for switching patterns is applied to a hand shake logic from the MC at the time t1. At the time t2, a flag is erected and at the time t3, the GACK is outputted to the MC. On the other hand, an address multiplexer outputs an address of a table B for a specified digital pattern at the time t4 to output a pattern corresponding to the table. Thereafter, the GO and GACK are released at the time t5 and t6.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention is applied to an IC test system. In an IC test system including a main controller controlling a test section, a predetermined digital pattern can be continuously switched and generated from a digital test section without generating a dummy cycle.

(Prior Art) FIG. 5 is a block diagram showing an example of a system used for testing an LSI in which an analog signal system and a digital signal system are mixed and integrated. In Figure 5, AM performs analog signal system tests such as adding analog signals to the LSI (hereinafter referred to as DUT), which is the IC to be tested, and measuring analog mini No. 3 output from D (JT). The analog test section, FC, is a digital test section that adds a predetermined digital pattern to CUT and tests the digital signal system, and MC is each of these test sections AM, F.
It is the main controller that generally serves as the sub-III of C.

In such a container configuration, each test portion Δ~1. The FC is connected to the main controller MC via a relatively low-speed (1 MW/SPi! degree) bus. Then, the main controller MC performs, for each of the test units AM and FC, (1) data communication such as measurement data and pattern data, (2) control for generating test signals and starting and stopping measurement operations.

By the way, if we focus on the speeds required of these digital test section FC and main controller MO, the speed required for digital test section FC is 25 ns to 100 ns per one instruction, whereas the speed required for main controller MC is 500 ns to 3000 ns per one instruction. For example, as the processor of the digital test section FC, a micromachine with one instruction of 100 ns or less and a microcode of about 50 to 120 bits is used, and as the main controller MC, a general-purpose microprocessor such as 68000 or 8086 is used.

(Problems to be Solved by the Invention) However, with such a configuration, the main controller MC cannot follow the speed of each instruction of the digital test section FC, and cannot achieve fine synchronization. Therefore, in general, the main controller MC is connected to the digital test section FC.
In many cases, it only executes simple commands such as starting and stopping the computer. In addition, some devices are configured to install 6q general-purpose slices ΔLU (A m2901 manufactured by Advanced Micro Devices, etc.) in the digital test section FC and perform synchronous communication with the main controller MC at a relatively slow speed. When switching between A and LU, data must be transmitted within LU.
During that period, the output of the digital pattern will stop, and a dummy cycle will occur. Such a dummy cycle is used, for example, when testing an LSI in which an analog signal system and a digital signal system are mixedly integrated.
This causes inconvenience when continuity of the digital pattern is required.

The present invention has focused on this point, and its purpose is to provide an IC test system that can switch digital patterns without causing dummy cycles.

(Means for Solving the Problems) The present invention that achieves the above object includes a digital test section that tests a digital signal system on an IC to be tested, and a main controller that controls this digital test section. In an IC test system, a handshake logic is installed in which the main controller sends a command signal for pattern switching to the digital test section, and the digital test section returns a response signal according to the command signal to the main controller. It is characterized by

(Example) Hereinafter, it will be explained in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a signal RUN is sent from the main controller MC to the digital test section FC to control start/stop.
In addition to /5TOP, a command signal Go for pattern switching is applied, and a response signal GACK corresponding to the command signal GO is sent back from the digital test section FC to the main controller MC.

FIG. 2 is a block diagram showing a specific example of the digital test section FC according to the present invention. In FIG. 2, MUX1 is an address multiplexer that selectively outputs an address by using a decoder signal applied from an instruction decoder ID as a selection signal. The address stored in the jump address memory JM is added to the address multiplexer MUX1 via the vibe line register PLR, and the address output from the program counter PC is also added to the address multiplexer MUX1. The addresses output from this address multiplexer MLIX1 are the instruction memory IM, jump address memory JM, and condition multiplexer memory C.
M and the pattern memory PM, and is also added to the program counter via an arithmetic unit that adds +1 to the address. The outputs of these instruction memory IM, digital address memory JM, condition multiplexer memory CM, and pattern memory PM are stored in vibe line registers PLR1 to PLR, respectively.
It has been added to 4. The output of the vibe line register PLR1 is applied to the instruction decoder ID, the output of the pipeline register PLR2 is applied to the address multiplexer MUX1, and the output of the pipeline register PLR3 is applied to the condition multiplexer MUX.
2 as a selection signal, and the pipeline register P
The output of LR4 is applied to the DUT as a digital pattern. To the condition multiplexer MUX2, a predetermined flag representing the completion of the handshake operation is added from the handshake logic 1-(SL), and flags representing the respective statuses are added from other parts (not shown). , the output of the instruction memory IM is added as a control signal.A command signal GO for pattern switching is applied from the main controller MO to this handshake logic H3L, and a command signal GO for pattern switching is applied from the handshake logic H8L to the main controller MC. Response signal GACK according to command signal Go
has been returned.

The operation of the system configured in this way will be explained.

FIG. 3 is an explanatory diagram showing an example of a program for skipping the operation of the system of FIG. 2, and FIG. 4 is a timing chart. In addition, in FIG. 4, Ll) indicates the clock CLK, (b) indicates the state of the table output from the pattern memories P and M, and (C) indicates the state of the table output from the main controller MC to the handshake logic l-ISL. Indicates a command signal Go applied for pattern switching,
(d) shows the response signal GACK applied from the handshake logic I-ISL to the main controller MC in response to the command signal Go, and (e) shows the flag FLΔG applied from the handshake logic H8L to the instruction decoder ID. ing.

For example, if a command signal Go for pattern switching is applied from the main controller MC to the handshake logic l-ISL at time [, when the digital pattern based on the table Δ is being output, then the rising edge of the clock CLK immediately after that A flag is raised at time t2. Then, the handshake logic H8L outputs a response signal GΔCK according to the command signal GO to the main controller to IC at time t3 after the flag rises. On the other hand, address multiplexer M
UX1 is an address corresponding to a table (table B in this embodiment) for generating a predetermined digital pattern at the rising edge time t4 of the next gate C and K when a flag is output from the handshake logic l-l5L. Output. As a result, a digital pattern according to table B is output from pipeline register PLR4. At time t5 after the table has been switched in this way, the main controller M
C releases the command signal Go, and then at time t6, handshake logic (sL releases the response signal GACK.In addition, in a series of table switching operations from time 11 to time t6, from time t1 to time t4
The processing is performed at high speed until then, and the processing is performed at low speed from time t4 to time t6.

As is clear from these explanations, f) SI et al., by configuring as shown in Figure 2, tables can be switched at high speed without generating dummy cycles when switching tables, and for example, in an analog signal system. Even when testing an LSI in which a digital signal system and a digital signal system are mixed and integrated, there is no problem when continuity of the digital pattern is required.

In addition, the main controller MC and digital test section FC
As for the synchronization between the two, the next step is not performed until each other's signals are completely recognized, so synchronization will not be lost.

Also, regarding programs, simple instructions (JMNG)
All you have to do is add , it's not complicated.

Furthermore, the circuit configuration only requires the addition of two or three ICs, and can be configured relatively inexpensively.

In the above embodiment, an example of a system used for testing an LSI in which an analog signal system and a digital signal system are mixed and integrated has been described, but the system can also be applied to a test system for an IC with only a digital signal system. It is.

(Effects of the Invention) As explained above, according to the present invention, it is possible to realize an IC test system that can switch digital patterns without causing a dummy cycle with a relatively intermediate configuration, and has great practical effects. .

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing a specific example of the digital test section FC according to the invention, and Fig. 3 is a program for operating the system shown in Fig. 2. 4 is a timing chart, and FIG. 5 is a block diagram showing an example of an IC test system to which the present invention is applied. AM...part of analog device 1, DUT...・Test object +C, FC...Digital test section, MC...Main controller 1-roller, it S L...Handshake logic. Fig. 3 Fig. 4

Claims (1)

[Claims] In an IC test system that includes a digital test section that tests the digital signal system of an IC to be tested and a main controller that controls this digital test section, a command signal for pattern switching is sent from the main controller to the digital test section. 1. An IC test system characterized by further comprising a handshake logic for returning a response signal according to a command signal from a digital test section to a main controller.