JPS5969836A - Large scale integrated circuit for series i/o interface - Google Patents

Abstract

PURPOSE:To omit connecting work, to reduce a mounting area and to improve accuracy and reliability by constituting plural circuits on one chip in a series I/O interface. CONSTITUTION:A series I/O interface LSI10 which is an oridinary used circuit, a transmitting/receiring FiFo memory stack 12 and a transmitting/receiving hand shake logic circuit 14 are formed on one LSI chip 26. Consequently, connection work can be omitted, the mounting area can be reduced and noise resistivity can be also improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a large-scale integrated circuit for serial input/output interfaces, and particularly to a large-scale integrated circuit configured to include peripheral interfaces on one chip.

Conventionally, serial input/output interface LSIs have been commercialized, and these interface LSIs have excellent features such as independent receiving and transmitting sections and a double buffer structure. It is widely used because of its characteristics.

However, in this type of LSI, the central processing unit checks a status signal indicating that the transmission buffer is empty for each transmission data (e.g., 8 bits), inputs a transmission data load signal, or inputs a transmission data load signal. Procedures such as checking the reception of data and inputting the received data/read signal are required each time, and when data is sent and received frequently, the overhead on the central processing unit side increases, reducing efficiency and increasing throughput. It was impossible to realize this.

To solve this problem, a first-in, first-out memory stack (hereinafter referred to as a FiFo memory stack) is connected to the serial input/output interface L8110 as shown in FIG.

Interfaces with added logic circuits have been put into practical use.

In the figure, 10 is a serial input/output interface LSI having a transmitting section 10T and a receiving section 10R, and 12T is a transmitting Fi
12R is a reception FiFo memory stack, 14T is a transmission handshake logic circuit, and 14R is a reception handshake logic circuit. F i F o memory stack 12T, 1
2R plays the role of a data buffer, and the handshake logic circuits 14T and 14R connect the serial input/output interface LS110 and the F i l; This will be done automatically when the preparation is complete.

16T is a write signal to write data to the FiFo memory stack 12'l'', 16R is a read signal to read data from the FiFo memory stack 12ft, 18T
is a control signal indicating that the F i F o memory stack 12T is empty, and 18R is F i F .

This is a control signal indicating that the memory stack 12R is full.

20T is serial transmission data of the serial input/output interface LSIl0, and 20R is its serial reception data.

22'l'' is a transmission FiFo buffer data bus, 22
R is a receiving FiFo buffer data bus, and 24 is a data bus with a central processing unit (not shown).

Now, when it is assumed that the transmission FiFo memory stack 12T is empty, the central processing unit sends a control signal 1 to indicate that the transmission FiFo memory stack 12T is empty.
Confirm with 8T and send light signal 16T to transmit signal FiF
o The data is sent to the memory stack 12T and several times of transmission data is written therein.

In this state, the handshake logic circuit 14T
iFo memory 12'l' and interface LSI
After checking the status of the transmitting section 10T of l0 and completing preparations for both, the data is automatically transferred from the memory 12T to the transmitting section 10Tf.
C Transfer. The transmitter 10T serially transmits the transmission data 20T at the same time as data transfer.

Therefore, F'i)+', the central processing unit is not occupied by the serial input/output interface while data is stored in the memory stack 12T.

Similarly, in the receiving system, the received data 2OR is received by the ear p-face LS11o! 10B, and the received data is written to the reception FiF□ memory stack 12R by the reception handshake logic circuit 14R, but the central processing unit is not concerned until the memory stack 12R is full. FI
When the FO memory stack 12R is full, this is communicated to the central processing unit by the control signal 18R, and a read signal 161% can be sent to the memory stack 12H to read the received data from the memory stack 12R.

However, the interface circuits described above are in high demand because they can improve serial input/output transfer efficiency and reduce the time occupied by the central processing unit. The drawback is that each circuit must be combined, which requires time and effort.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to
It is an object of the present invention to provide a large-scale integrated circuit for a serial input/output interface that can omit the connection work of various parts by configuring it on a chip, reduce the mounting area, and have high accuracy and reliability.

To achieve the above object, the present invention is characterized in that a serial input/output interface LSI, two first-in first-out memory stacks, and a handshake logic circuit are mounted on one chip.

Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

In FIG. 2, 26 is one LSI chip,
A serial input/output interface LS1 is provided on this chip 26.
10. Transmission and reception F 1 F □Memory stacks 12T and 12R1 Transmission and reception handshake logic circuits 14T and 14R are connected to each other and housed. 22 is a parallel data bus p, the first
This is a bidirectional bus that also serves as data buses 22T and 22R in the figure.

In addition, the control signals 16T, 16J18T, corresponding to FIG.
18R are all formed within the chip 26 and configured to be taken out to the outside of the chip.

Note that 28T and 28R are serial transmission data to the outside and serial reception data from the outside.

The above is an example of the configuration of the present invention, and its operation is basically the same as the conventional circuit described above, and a detailed explanation thereof will be omitted. can be improved, and the time occupied by the central processing unit can also be reduced.

In this example, since the data bus 22 is bidirectional, when the data bus 22 is supplied with the high IJ-do signal 16R, the write signal 16T is supplied in the output direction as seen from the chip 26 side. It is necessary to control each direction in the input direction.

As described above, according to the present invention, the serial input/output interface 1, the SI, the PiFo memory stack, and the hand
Since the shake logic circuit is mounted on one chip to form a large-scale integrated circuit for the interface, the mounting area can be reduced, accuracy and reliability can be increased, and noise resistance can be provided. This has the advantage of being able to eliminate unnecessary hardware design.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional interface circuit with a FiFo memory stack, and FIG. 2 is a perspective view showing an embodiment of the present invention. In each figure, the same members are given the same reference numerals, 1o is a serial input/output interface LSI, 12Til [trusted FiFo
Memory stack, 12R is FiFo memory stack for reception, 14T is 2nd for transmission. Shake logic circuit, 14R is the receiving hand. The shake logic circuit 26 is a chip. Agent: Patent attorney Shin Kuzuno - (1 other person)

Claims (1)

[Claims] (1) A large-scale integration for serial input/output interfaces characterized by mounting a serial input/output interface LSI, two first-in first-out memory stacks, and a seven-point shake logic circuit on one chip. circuit.