JP2006171810A - Debugging control system and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To adequately grasp an operational state of a specific peripheral circuit, easily cut out malfunctions of hardware and software, and analyze the malfunctions. <P>SOLUTION: The operation of a specific peripheral circuit (a DMA control part 233 and a timer control part 242) is stopped at a clock control part 262 based on a debugging mode notification signal 211 showing the start of debugging, and debugging of the specific peripheral circuit is executed under the conditions that the operation of the specific peripheral circuit is stopped. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a debug control system for executing debugging on a specific peripheral circuit.

  In general, when debugging a system LSI with a built-in CPU, an ICE (In-Circuit Emulator) is connected to the outside of the system LSI, and the on-chip CPU is controlled from the ICE to perform break processing and step execution of the user program. ing. This is because a breakpoint is set at a point where the user program is to be stopped in advance, and when the program actually executed in real time reaches that point, the CPU forcibly shifts to the debug mode, and the subsequent program This is realized by temporarily stopping execution (see, for example, Patent Document 1).

  This method of transition to debug mode uses, for example, a hardware break that is implemented by the CPU having a debug circuit for transitioning to debug mode in advance, and a part of the program to be executed is replaced with a trap instruction to use a software interrupt. Then, there is a software break that is implemented by moving to the monitor program. However, in any case, only the program execution is temporarily stopped in the debug mode by ICE, and peripheral circuits other than the CPU including the on-chip bus operate in real time. This will be described with reference to FIG.

  FIG. 1 is a diagram illustrating an example of a configuration of a general debug control system. As shown in FIG. 1, the debug control system 100 includes a CPU 110 connected to an on-chip bus 120, a DMA controller 130, a timer controller 140, and an external memory device 102, which are specific peripheral circuits. 150.

  Here, the DMA controller 130 is configured by modules of a slave I / F 131, a master I / F 132, and a DMA control unit 133. In addition, the timer controller 140 is configured by modules of a slave I / F 141 and a timer control unit 142. Further, the MEM controller 150 is configured by modules of a slave I / F 151 and a MEM control unit 152.

  As shown in FIG. 1, the CPU 110 is connected to an external ICE 101 via a dedicated bus and can be directly controlled by the designer from the ICE 101. Here, the state in which the CPU 110 has shifted to the debug mode is a state in which the execution of the user program of the CPU 110 is temporarily stopped, and the other DMA controller 130 including the on-chip bus 120, the timer controller 140, and the MEM controller. Reference numeral 150 denotes a state in which all are operating in real time.

  Accordingly, these peripheral circuits continue to operate until each pre-programmed operation is completed or until the designer issues an operation stop command by the ICE 101 even when the CPU 110 is in the debug mode.

  After shifting to the debug mode, all control of the CPU 110 is executed from the ICE 101 by the designer. For example, step execution is performed to ensure that the execution of each instruction is processed by the designer confirming the result of sequential execution of the program after entering the debug mode, and the ICE 101 instructs the CPU 110 to execute one instruction. Are executed sequentially by allowing execution of a minute's program.

  While the CPU 110 is in the debug mode, the designer controls the CPU 110 from the ICE 101 to access an arbitrary memory area or I / O area independently of the currently executed program, and the contents Can be confirmed or the value can be rewritten, whereby a failure of the user program and hardware can be analyzed.

  For example, in FIG. 1, when the designer dumps and displays an arbitrary area of the external memory device 102, the CPU 110 is controlled from the ICE 101 to control the external memory device 102 via the on-chip bus 120 and the MEM controller 150. The data is read by sequentially accessing an arbitrary area, and the read data is transferred to the ICE 101.

  In addition, when the designer wants to know the counter value of the timer controller 140 and the value of the status register, the CPU 110 is controlled from the ICE 101 to access the counter and status register of the timer controller 140 via the on-chip bus 120. The value can be confirmed by reading the data and transferring the read data to the ICE 101.

However, since the peripheral circuit operates in real time as described above, these values are not the values at the time when the CPU 110 enters the debug mode, but the counter values and the state of the control unit when the CPU 110 accesses the peripheral circuits. Is a value indicating.
JP 2002-055849 A

  As described above, in the prior art, it is possible to stop the operation of the CPU in the debug mode, but it is not possible to stop the operation of other peripheral circuits. Therefore, in these peripheral circuits, there is a problem that even though the CPU is stopped and the program step execution is executed, the execution is performed in real time, and the state according to the actual operation cannot be observed. .

  On the other hand, higher functionality and higher integration of LSIs have progressed, and events that could not be anticipated at the design simulation stage have occurred at the actual machine debug stage. This is because many peripheral circuits other than the CPU have been built into the LSI at the same time due to high functionality and high integration of the LSI, and it has become difficult to perform all of these functional verifications at the simulation stage. is there.

  In particular, in a real machine system, problems caused by competing operations when peripheral circuits operate simultaneously cannot be reproduced by simulation, and it is determined whether this is a software problem or a hardware problem. It was very difficult to do.

  Moreover, one of the reasons for making these analyzes more difficult is that the user program and the peripheral circuit are not synchronized even in the debug mode, so that the cause of the failure cannot be specified.

  For example, if the value of a specific data area is not correct and the DMA control unit is operating in a pre-programmed state, the DMA control unit operates in real time even if step execution of the program is performed. The actual system determines whether the data has been rewritten without the program's intention, whether the data has been rewritten because the DMA controller does not operate correctly, or whether other peripheral circuits have rewritten the data without intention. Was very difficult.

  The present invention has been made to solve the above-described problems, and accurately grasps the operating state of a specific peripheral circuit, and easily performs a hardware and software defect extraction and an analysis for the defect. With the goal.

  The present invention relates to a debug control system for executing debugging on a specific peripheral circuit, wherein a unit for stopping the operation of the specific peripheral circuit based on a signal indicating the start of debugging, and an operation of the specific peripheral circuit And executing means for executing debugging of the specific peripheral circuit in a stopped state.

  Further, the present invention provides a control method of a debug control system for executing debugging on a specific peripheral circuit, the step of stopping the operation of the specific peripheral circuit based on a signal indicating start of debugging, And an execution step of executing debugging on the specific peripheral circuit in a state in which the operation of the peripheral circuit is stopped.

  According to the present invention, it is possible to accurately grasp the operating state of a specific peripheral circuit, and to easily identify and analyze a defect in hardware and software.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings. In the present embodiment, in a debugging environment in which an ICE (In-Circuit Emulator) is connected to an on-chip CPU to perform a program break process or step execution, a specific peripheral other than the CPU is simultaneously executed with the program break process. After the clock supplied to the circuit is stopped and the operation of the peripheral circuit is stopped, the clock supply to the specific peripheral circuit is controlled from the ICE, so that the specific peripheral circuit can be sequentially executed in units of clocks. A debug control system will be described.

  FIG. 2 is a diagram illustrating an example of the configuration of the debug control system according to the first embodiment. As shown in FIG. 2, the debug control system 200 includes a CPU 210 connected to an on-chip bus 220, a DMA controller 230 that is a specific peripheral circuit, a timer controller 240, and an MEM controller 250 for accessing an external memory device 202. , A clock controller 260, and a clock generation circuit 270.

  Here, the DMA controller 230 includes modules of a slave I / F 231, a master I / F 232, and a DMA control unit 233. In addition, the timer controller 240 is configured by modules of a slave I / F 241 and a timer control unit 242. Further, the MEM controller 250 includes modules of a slave I / F 251 and a MEM control unit 252. Further, the clock controller 260 is configured by modules of a slave I / F 261 and a clock control unit 262.

  The peripheral circuit shown in FIG. 2 is an example for explaining the present invention, and is not limited to this.

  As shown in FIG. 2, the CPU 210 is connected to an external ICE 201 via a dedicated bus, and the designer can directly control from the ICE 201. The clock controller 260 is connected to the debug mode notification signal 211 output from the CPU 210, and the clock control unit 262 generates and outputs the clock enable signal 263 based on this signal.

  On the other hand, an external clock (XSYSCLK) 271 is input to the clock generation circuit 270, and the reference clock generated from the XSYSCLK 271 is always operated by each module (slave I / F 231, 241, 251, 261). , Master I / F 232, MEM control unit 252, clock control unit 262) and CPU 210 (not shown). Further, the clock (PCLK) 272 masked by the clock enable signal 263 is supplied to each module (DMA control unit 233, timer control unit 242) that sequentially executes operations according to the clock 272.

  Next, a detailed operation of the debug control system 200 according to the first embodiment having the above configuration will be described.

  First, the procedure for the CPU 210 to enter the debug mode is executed by a hardware break and a software break as in the conventional example. When shifting to the debug mode, the CPU 210 asserts a debug mode notification signal 211. The clock controller 262 of the clock controller 260 deasserts the clock enable signal 263 by asserting the debug mode notification signal 211.

  FIG. 3 is a diagram illustrating an example of a circuit that generates the clock enable signal 263. As shown in FIG. 3, the input debug mode notification signal 211 is inverted by the inverter 301 and output as the clock enable signal 263.

  When the clock enable signal 263 is deasserted, the clock generation circuit 270 fixes the PCLK 272 at a low level and stops the clock supply to the DMA control unit 233 and the timer control unit 242.

  FIG. 4 is a diagram illustrating an example of the configuration of the clock generation circuit 270 and a timing chart. As described above, since the DMA control unit 233 and the timer control unit 242 are clock synchronization circuits, when the supply of the PCLK 272 is stopped, the operation is immediately stopped.

  As shown in FIG. 2, the slave I / Fs 231 and 241 and the master I / F 232 that directly communicate with the on-chip bus 220 are normal operation units, and a clock different from the PCLK 272 is supplied. Does not stop even after moving to.

  The slave I / Fs 231 and 241 and the master I / F 232 are independent of the DMA control unit 233 and the timer control unit 242, and are affected even when the PCLK 272 to the DMA control unit 233 and the timer control unit 242 is stopped. It is possible to access from the CPU 210 or access to the on-chip bus 220 without using it.

  Therefore, even if the CPU 210 shifts to the debug mode and the DMA control unit 233 and the timer control unit 242 stop, the CPU 210 accesses the control registers and status registers of these peripheral circuits via the on-chip bus 220 as usual. Is possible.

  In this state, the designer can control the CPU 210 from the ICE 201 and know the accurate values and states of the peripheral circuits at the time of shifting to the debug mode. What is the program currently being executed for debugging? Even if you access any memory area or I / O area independently, the operation of the peripheral circuit is stopped, so even if you access the peripheral circuit again, the state at the time of shifting to the debug mode is continuously observed. Is possible. For example, the designer can check the exact time at the time of shifting to the debug mode by controlling the CPU 210 from the ICE 201 and accessing the counter of the timer control unit 242, and can arbitrarily check the external memory device 202. After dumping the area, it is possible to confirm the exact time at the time of shifting to the debug mode even if the counter of the timer control unit 242 is accessed again.

  Also, when analyzing a failure of the user program, it is possible to execute only the operation of the CPU 210 by performing step execution of the user program in the state of shifting to the debug mode, and the analysis is continued without being affected by peripheral circuits. Is possible. Specifically, when the debug mode is entered while the pre-programmed DMA controller 233 is operating, the operation of the DMA controller 233 is temporarily stopped simultaneously with the transition to the debug mode. If step execution of the user program is performed in this state, the CPU 210 is the only module that performs a master operation on the on-chip bus 220. Therefore, even if it is found that the value of a specific data area is incorrect due to step execution of the user program. It is easy to identify that the cause was caused by the user program.

  According to the first embodiment described above, it is possible to easily extract a defect in hardware and software.

  In addition, it is possible to easily stop the clock supply to each module in implementation debugging by using the gated clock mechanism for each module, which is frequently used with the recent reduction in power consumption. .

  Next, Embodiment 2 according to the present invention will be described in detail with reference to the drawings. In the second embodiment, the clock controller is provided with a pulse generation circuit for sequentially executing peripheral circuits after the clock supply is stopped.

  FIG. 5 is a diagram illustrating an example of the configuration of the debug control system according to the second embodiment. As shown in FIG. 5, the second embodiment is different from the first embodiment described with reference to FIG. 2 in the clock controller 560.

  In the clock controller 560 shown in FIG. 5, the slave I / F 561 is the same as the slave I / F 261 of the first embodiment shown in FIG. 2, but the clock control unit 562 has a different configuration as described with reference to FIG. Is. Here, the configuration of the clock control unit 562 in the second embodiment will be described.

  FIG. 6 is a diagram illustrating an example of the configuration of the clock control unit 562 in the second embodiment. In FIG. 6, reference numeral 601 denotes a pulse generation circuit, which generates a waveform for one pulse according to a set signal described later and outputs a clear signal. A step execution register 602 outputs a set signal to the pulse generation circuit 601 when an arbitrary value is set from the CPU 210, and clears the register value with a clear signal. Reference numeral 603 denotes an OR circuit. When the debug mode notification signal 211 is asserted, the clock enable signal 563 is deasserted and the pulse waveform from the pulse generation circuit 601 is output as the clock enable signal 563.

  Next, a detailed operation of the debug control system 500 according to the second embodiment having the above configuration will be described.

  First, the procedure for the CPU 210 to shift to the debug mode is the same as that in the conventional example, and thereafter, the procedure until the clock supply to the peripheral circuit is stopped is the same as that in the first embodiment.

  Then, with the CPU 210 transitioning to the debug mode, the designer controls the CPU 210 from the ICE 201 and sets an arbitrary value in the step execution register 602 of the clock control unit 562 via the on-chip bus 220. The value of the step execution register 602 is given to the pulse generation circuit 601 as a set signal, and the pulse generation circuit 601 generates a waveform for one pulse. At the same time, the pulse generation circuit 601 outputs a clear signal to the step execution register 602 to automatically clear the value of the step execution register 602.

  Next, the pulse waveform generated by the pulse generation circuit 601 is output from the OR circuit 603 to the clock generation circuit 270 as a clock enable signal 563.

  FIG. 7 is a diagram illustrating an example of the configuration of the clock generation circuit 270 and a timing chart. As shown in FIG. 7B, the clock generation circuit 170 supplies the PCLK 272 to the DMA control unit 233 and the timer control unit 242 only during the pulse output period of the clock enable signal 563.

  As described above, since the DMA control unit 233 and the timer control unit 242 are clock synchronization circuits, when the PCLK 272 is supplied, the DMA control unit 233 and the timer control unit 242 operate for that cycle.

  Here, a case where sequential execution is performed in units of cycles will be described by paying attention to the timer control unit 242 described above.

  When the designer controls the CPU 210 from the ICE 201 to set an arbitrary value in the step execution register 602 of the clock control unit 562, the clock generation circuit 270 supplies the PCLK 272 for one cycle to the timer control unit 242. When this PCLK 272 is supplied, the timer control unit 242 counts up the counter value by one. Also in this case, since the state is still shifted to the debug mode, the designer can check the counted up value by controlling the CPU 210 from the ICE 201 and accessing the timer control unit 242.

  Similarly, the designer can operate the timer control unit 242 for a necessary cycle. During this operation period, the timer control unit 242 does not count up correctly, or a specific counter of the timer control unit 242 is displayed. It is possible to easily check on the actual system for problems that interrupts do not occur with values.

  FIG. 8A shows a case where the count-up function of the timer controller 240 is executed as sequential execution by the step execution register 602, the actual counter value is monitored in that state, and a count-up error occurs. is there. FIG. 8B shows a case in which an interrupt signal is generated when the counter value of the timer controller 240 matches the value of the comparison value register, and no interrupt signal is generated.

  According to the second embodiment described above, a designer can sequentially execute peripheral circuits in units of cycles, and easily analyze hardware faults in units of cycles, which was impossible in the past in an actual system. Can be done.

  Next, Embodiment 2 according to the present invention will be described in detail with reference to the drawings. In the third embodiment, the clock control unit 562 described in the second embodiment further includes a clock selection register that selects in advance the stop of the clock supply.

  FIG. 9 is a diagram illustrating an example of the configuration of the debug control system according to the third embodiment. As illustrated in FIG. 9, the third embodiment is different from the second embodiment described with reference to FIG. 5 in the clock controller 960 and the clock generation circuit 970.

  In the clock controller 960 shown in FIG. 9, the slave I / F 961 is the same as the slave I / F 261 of the first embodiment and the slave I / F 561 of the second embodiment, but the clock control unit 962 will be described with reference to FIG. The configuration is different. Here, the configuration of the clock control unit 962 in the third embodiment will be described.

  FIG. 10 is a diagram illustrating an example of the configuration of the clock control unit 962 according to the third embodiment. In the third embodiment, as shown in FIG. 10, the configuration of the second embodiment further includes a clock selection register 1001, and by setting a predetermined value in the clock selection register 1001 in advance, the periphery of the corresponding bit is set. The supply of the clock is stopped only to the circuit.

  In the example shown in FIG. 10, when the bit [0] of the clock selection register 1001 is set to “1” and the debug mode notification signal 211 is asserted, the clock enable signal a963 is deasserted. When the bit [1] of the clock selection register 1001 is set to “1” and the debug mode notification signal 211 is asserted, the clock enable signal a963 is deasserted.

  Further, the clock generation circuit 970 according to the third embodiment includes two configurations in parallel corresponding to the clock enable signals a963 and b964 output from the clock control unit 962 described above with reference to FIG. , B972 are generated.

  Next, a detailed operation of the debug control system 900 according to the third embodiment having the above configuration will be described.

  First, before the CPU 210 shifts to the debug mode, an arbitrary bit of the clock selection register 1001 corresponding to the peripheral circuit whose supply of clock is to be stopped in the debug mode is set.

  Here, it is assumed that bit [0] of the clock selection register 1001 corresponds to the DMA control unit 233 and bit [1] corresponds to the timer control unit 242, and only bit [0] is set in advance. .

  Next, the procedure for the CPU 210 to shift to the debug mode is the same as that in the conventional example. Thereafter, the procedure for stopping the clock supply to the peripheral circuit and the sequential execution in units of cycles to the peripheral circuit by the step execution register 602 is described in the embodiment. Same as 2.

  Note that the clock supply to peripheral circuits not previously selected by the clock selection register 1001 is not stopped and operates in real time as usual. This is performed by the following procedure.

  When shifting to the debug mode, the CPU 210 asserts the debug mode notification signal 211. On the other hand, the clock control unit 962 generates clock enable signals a963 and b964 corresponding to the peripheral circuits. When the debug mode notification signal 211 is asserted, only the signal for which the corresponding bit of the clock selection register 1001 is set is deasserted.

  Here, since only bit [0] of the clock selection register 1001 is set in advance, only the clock enable signal a963 for the DMA control unit 233 is deasserted. The clock enable signal b964 for the timer control unit 140 remains asserted because the bit [1] of the clock selection register 1001 is not set.

  On the other hand, the clock generation circuit 970 generates a clock 971 (PCLKa) and a clock 972 (PCLKb) from the clock enable signal a963 for the DMA control unit 233 and the clock enable signal b964 for the timer control unit 242, respectively. Here, when the clock enable signal a963 is deasserted, the clock 971 (PCLKa) is fixed at a low level and the clock supply to the DMA control unit 233 is stopped.

  As described above, since the DMA control unit 233 is a clock synchronization circuit, when the supply of the PCLKa 971 is stopped, its operation is immediately stopped.

  The clock 972 (PCLKb) is operating normally because the clock enable signal b964 is still asserted, and the clock supply to the timer control unit 242 is not stopped.

  In this state, the designer can continue the analysis without being influenced by the DMA control unit 233 by executing the step execution of the user program.

  According to the third embodiment described above, the designer can operate only the minimum modules necessary for debugging when shifting to the debug mode, and the work efficiency in actual machine debugging can be improved.

  Furthermore, by operating any peripheral circuit simultaneously, it is possible to analyze a problem caused by the competing operation.

  In the embodiment described above, the PCLK supplied from the clock control unit and the clock generation circuit to the peripheral circuit is stopped based on the debug mode notification signal from the CPU, but is configured to be stopped by a predetermined signal from the ICE. May be.

  Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), it is applied to an apparatus (for example, a copier, a facsimile machine, etc.) composed of a single device. It may be applied.

  Another object of the present invention is to supply a recording medium that records software program codes for realizing the functions of the above-described embodiments to a system or apparatus, and the computer (CPU or MPU) of the system or apparatus uses the recording medium as a recording medium. Needless to say, this can also be achieved by reading and executing the stored program code.

  In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like is used. be able to.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) operating on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.

  Further, after the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.

It is a figure which shows an example of a structure of a general debug control system. It is a figure which shows an example of a structure of the debug control system in Example 1. FIG. 3 is a diagram illustrating an example of a circuit that generates a clock enable signal 263. FIG. 3 is a diagram illustrating an example of a configuration of a clock generation circuit 270 and a timing chart. FIG. It is a figure which shows an example of a structure of the debug control system in Example 2. FIG. 6 is a diagram illustrating an example of a configuration of a clock control unit 562 in Embodiment 2. FIG. 3 is a diagram illustrating an example of a configuration of a clock generation circuit 270 and a timing chart. FIG. 6 is a diagram for explaining an example of a problem that occurs in sequential execution by a step execution register 602. FIG. FIG. 10 is a diagram illustrating an example of a configuration of a debug control system according to a third embodiment. FIG. 10 is a diagram illustrating an example of a configuration of a clock control unit 962 according to the third embodiment.

Explanation of symbols

100 Debug control system 101 ICE
102 External memory 110 CPU
120 On-chip bus 130 DMA controller 131 Slave I / F
132 Master I / F
133 DMA controller 140 Timer controller 141 Slave I / F
142 Timer Control Unit 150 MEM Controller 151 Slave I / F
152 MEM Control Unit 200 Debug Control System 201 ICE
202 External memory 210 CPU
211 Debug mode notification signal 220 On-chip bus 230 DMA controller 231 Slave I / F
232 Master I / F
233 DMA controller 240 Timer controller 241 Slave I / F
242 Timer control unit 250 MEM controller 251 Slave I / F
252 MEM Control Unit 260 Clock Controller 261 Slave I / F
262 Clock control unit 263 Clock enable signal 270 Clock generation circuit 271 External clock (XSYSCLK)
272 PCLK

Claims (6)

A debug control system that executes debugging to a specific peripheral circuit,
Means for stopping the operation of the specific peripheral circuit based on a signal indicating the start of debugging;
A debug control system comprising: execution means for executing debugging of the specific peripheral circuit in a state where the operation of the specific peripheral circuit is stopped.   2. The debug control system according to claim 1, wherein the stopping means stops the operation of the specific peripheral circuit by stopping a predetermined clock supplied to the specific peripheral circuit. Generating means for generating the predetermined clock for one clock in a state in which the operation of the specific peripheral circuit is stopped;
2. The debug control system according to claim 1, further comprising sequential debug execution means for operating the specific peripheral circuit with a clock of one clock generated by the generation means and executing sequential debug.   4. The debug control system according to claim 3, further comprising selection means for selecting the specific peripheral circuit from a plurality of peripheral circuits. A control method of a debug control system for executing debugging to a specific peripheral circuit,
Stopping the operation of the specific peripheral circuit based on a signal indicating the start of debugging;
A control method for a debug control system, comprising: an execution step of executing debugging on the specific peripheral circuit in a state where the operation of the specific peripheral circuit is stopped.   The program for making a computer perform each procedure of the control method of the debug control system of Claim 5.

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