JPS6124280A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the dispersion of the characteristics of a transistor having LDD structure by controlling the width of a low-concentration diffusion layer under the conditions of oxidation through which an oxide film is formed and conditions for heat treatment. CONSTITUTION:Oxide films 28, 28 and a gate electrode 29 are shaped through thermal oxidation at a high temperature in an oxidizing atmosphere while using a silicon nitride film pattern 25 on a polycrystalline silicon film pattern 24 and silicon nitride films 27 on the surfaces of N<-> type diffusion layers 26a, 26b as oxidation-resistant masks. N<+> type diffusion layers 30a, 30b are formed while employing the silicon nitride film pattern 25, the gate electrode 29 and the oxide films 28, 28 on the side wall of the gate electrode as masks. Accordingly, the width L of N<-> type diffusion layers 26a, 26b can be controlled with high accuracy, thus improving element characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
Lightly Doped Drain) structure M
It is used for manufacturing OS devices.

[Technical background of the invention and its problems]

In recent years, the miniaturization of MOS transistors has progressed significantly, but as a result, problems with device characteristics and reliability due to electric field concentration near the drain of the transistor have become noticeable. In other words, carriers are accelerated in the strong electric field region near the drain, collide with silicon atoms, and cause carrier multiplication, and the resulting majority carriers flow toward the substrate, becoming a substrate current and raising the potential of the substrate. , the characteristics of f-4-i will deteriorate. Further, at this time, some of the minority carriers gain high energy, enter the gate oxide film, and are captured, changing the amount of charge in the gate oxide film, thereby changing the threshold voltage of the transistor.

Therefore, in order to solve the problem of electric field concentration near the drain, so-called LDD (Lightly
An element with a doped drain structure has been proposed. This LDD structure element has source and drain regions consisting of a low concentration diffusion layer near the channel region and a high concentration diffusion layer (same impurity concentration as conventional source and drain regions) adjacent to these regions. It is something.

Conventionally, elements with this LDD structure are shown in FIGS. 2(a) to 2(a).
It is manufactured by the method shown in Q). First, for example, P
Sigut oxide film 2 is formed on the surface of mold silicon substrate 1 by thermal oxidation.
form. Next, after depositing a polycrystalline silicon film over the entire surface, patterning is performed using the photoresist pattern 3 as a mask to form a polycrystalline silicon film/mother turf 4. Subsequently, using this polycrystalline silicon film pattern 4 as a mask, for example, arsenic is ion-implanted at a high dose.
U-type scattering layer 5m5bt! form (as shown in FIG. 2(, )). Next, using the photoresist cutter 3 as a mask, the side walls of the polycrystalline silicon film groove 4 are etched by chemical dry etching or wet etching to form a gate electrode 6 (as shown in FIG. 4B). Next, after removing the photoresist pattern 3, the gate electrode 6 is removed.
The JN"' type diffusion layers 7m and 7b are formed by ion-implanting, for example, arsenic at a low dose using the mask as a mask.

As a result, N-type diffusion layers 7*, 7b near the channel region
and adjacent to these areas? Source and drain regions 8 and 9 consisting of type diffusion layers 5m and 5b are formed (as shown in FIG. 1C).

In the above method, the width Li of the N-type diffusion layers 7g and 7b is
It is almost determined by the amount of recession of the sidewall of the polycrystalline silicon film pattern 4 in the process shown in FIG. 3(b).

However, since it is extremely difficult to control the amount of lateral etching of the polycrystalline silicon film pattern 4,
There is a large variation in the width of the type diffusion layer 7a7b,
The disadvantage is that the transistor characteristics are not constant.

Elements with an LDD structure are also manufactured by the method shown in FIGS. 3(a) and 3(b). First, for example, a gate oxide film 12 is formed on the surface of a P-type silicon substrate 11, and then a polycrystalline silicon film is deposited on the entire surface and further patterned to form a gate electrode 13. Next, using the gate electrode 13 as a mask, arsenic, for example, is ion-implanted at a low dose to form an N'''' type diffusion layer 14a4b. Subsequently, a CVD oxide film 15 is deposited on the entire surface (as shown in FIG. 3 (-)). Next, the JCVD oxide film 15 is etched by reactive ion etching (HIE) to form CVD oxide films 15' and 15' on the side walls of the gate electrode 13.
5' remains. Next, using the CVD oxide films 15' and 16' remaining on the gate electrode 13 and its side walls as a mask, ions of, for example, arsenic are implanted at a high dose to form resistant diffusion layers 16m and 16b. As a result, N-type diffusion layers 14m and -14b near the channel region and type-resistant diffusion layers 16a and 16b adjacent to these regions are formed as source and drain regions 17, 18-1ti (FIG. 2(b)). (Illustrated).

In the above method, the width of the N-type diffusion layers 14a and 14b is C
It is determined approximately by the thickness of the VD oxide film 15 and the conditions for etching the CVD oxide film 15 by the RIE method. but,
Among these, the etching conditions particularly determined by the RIE method are set based on the distance, so there is a problem that the transistor characteristics are not constant. Well, in the above method, the RIE method is -
It also has the drawback of increasing costs due to lack of productivity. [Object of the Invention] The present invention has been made in order to eliminate the above drawbacks.
, it is an object of the present invention to provide a method of manufacturing a semiconductor device that can manufacture a transistor having an LDD structure with good controllability so that there is no /4 luck in characteristics, and at low cost.

[Summary of the Invention] The method for manufacturing a semiconductor device of the present invention includes forming a gate oxide film on the surface of a semiconductor substrate of a first conductivity type, and forming a pattern of an oxidizable conductive film (for example, a polycrystalline silicon film) thereon. After that, a low concentration diffusion layer of the second conductivity type for mitigating the strength of the stain field is formed by ion implantation using this pattern as a mask, and then an oxidation-resistant film is formed on the surface of this low concentration diffusion layer.
Perform thermal oxidation to form an oxide film on the sidewalls of the oxidizable conductive film, form a gate electrode made of the remaining oxidizable conductive film, and then perform ion implantation using the gate electrode and the oxide film on the sidewalls as a mask. The main idea is to form a highly concentrated diffusion layer of the second conductivity type.

According to this method, the width of the low concentration diffusion layer depends on the oxidation conditions when forming the oxide film on the sidewall of the oxidizable conductive film and the lateral spread of the low concentration diffusion layer and the high concentration diffusion layer. Since the heat treatment conditions that regulate the heat treatment conditions are determined by factors that are easy to control, controllability is extremely good. Still, RIE
The cost is low because it does not use a method that causes an increase in cost, such as the method used in the method. Furthermore, since an oxidation-resistant film is formed on the surface of the low-concentration diffusion layer, an oxide film will not grow on the surface of the low-concentration diffusion layer when forming an oxide film on the sidewalls of the oxidizable conductive film (gate electrode). There's nothing to do. Therefore, the conditions for ion implantation to form a highly concentrated diffusion layer can be relaxed.
Embodiments of the Invention Examples of the present invention will be described below with reference to FIGS. 1(,) to (e).

First, a field oxide film 22 is formed on the surface of a P-type silicon substrate 21 by selective oxidation, and then a gate oxide film 23 having a thickness of 300× or less is formed on the surface of the element region surrounded by the field oxide film 22. Next, a polycrystalline silicon film doped with phosphorus, for example, is deposited on the entire surface, and then carbon
A silicon nitride film is deposited by the VD method. Subsequently, these are sequentially turned to form a polycrystalline silicon film pattern 24 and a silicon nitride film pattern 25 on the gate oxide film 23 (as shown in FIG. 1(a)).

Next, using the silicon nitride film nozoturn 25 and the polycrystalline silicon film noreen 24 as masks, ions of arsenic, for example, are implanted at a low dose to form N for reducing the electric field strength.
- type diffusion layer 26a.

26b (as shown in FIG. 26(b)). Next, nitrogen ions are implanted using the silicon nitride film pattern 25 and the polycrystalline silicon film pattern 24 as masks. The condition for this ion implantation is that the distribution of nitrogen ions is extremely thick in the gate oxide film 2.
The acceleration energy is set so that the acceleration energy is located near the interface between 3 and the N- type diffusion layers 26g and 26b. For example, if the thickness of the gate oxide film 22 is about 300X or less, the acceleration energy is set to about 15 keV. The dose is 4X
It should be about 1015 cm-2. Subsequently, by performing high-temperature heat treatment in a non-oxidizing atmosphere, nitrogen and silicon of the substrate are reacted to form a gate oxide film 23 and an N- type diffusion layer 2.
A silicon nitride film 27 is formed near the interface with 6h and 26b (as shown in FIG. 6C).

Next, a flat turn 25 of the silicon nitride film on the polycrystalline silicon film pattern 24 and an N″′ type diffusion layer 26 & 6b are formed.
High-temperature thermal oxidation is performed in an oxidizing atmosphere using the silicon nitride film 27 on the surface as an oxidation-resistant mask. As a result, oxide films 28 and 28 are formed only on the side walls of the polycrystalline silicon film pattern, and a gate electrode 29 is formed from the remaining polycrystalline silicon film pattern. Further, when polycrystalline silicon is oxidized, the volume of the silicon oxide is approximately twice that of the polycrystalline silicon, so as the oxidation progresses, the oxide films 28, 28 extend outward from the original sidewall position. For example, when extending the oxide film 28.28 from the original sidewall position to 0.1 μm (a in the figure), about 0.1 μm of the sidewall of the polycrystalline silicon film pattern will be consumed by oxidation, and the oxide film 28.28 will be consumed by oxidation. The width of 28 is approximately 0.2 μm. Next, using the silicon nitride film pattern 25, the gate electrode 29, and the oxide films 2s and zs on its side walls as masks, ions of, for example, arsenic are implanted to form the fiN+ type diffusion layers 30m and 30.
form b. Regarding the conditions for this ion implantation, if the total of the gate oxide film 23 and silicon nitride film 27 is about 300X, the acceleration energy may be about 60 keV. As described above, the N- type diffusion layer 26a near the channel region is
, 26b and a furnace-type diffusion layer 30a adjacent to these regions,
Source and drain regions 31 and 32 consisting of 30b are formed (as shown in FIG. 3(d)). Next, PF3 on the entire surface
After the G film 33 is completely coated, a contact hole is opened.

Next, an At film was deposited on the entire surface. After C, patterning is performed to form a source electrode 34 and a drain electrode 35, and the LD
Manufacturing a D-structure MOS) transistor (same figure (=)
(Illustrated).

According to the above method, however, the N-type diffusion layer 26 shown in FIG. 1(d)! The width of L, 26b is determined by the length a of the oxide film 28.211 formed on the sidewall of the gate electrode 29 from the original sidewall, and the N-type diffusion layer 26 in the heat treatment process.
a, 26 a, and N+ type scattered layer 30a30b%
is determined by the lateral elongation of Here, in the former case, Vcff can be easily controlled to a good degree by changing the temperature, time, and atmosphere during oxidation. Furthermore, the latter also allows easy control of the temperature and time of the heat treatment process. For example, the N-type diffusion layer 26
If it is desired to extend only g and 26b toward the channel side, appropriate heat treatment may be performed in a non-oxidizing atmosphere before ion implantation for forming the furnace-type diffusion layers 30a and 30b.

Further, in the step of FIG. 1(C), an N- type diffusion layer 26a is formed.

By forming the silicon nitride film 27 on the surface of 26b, the following effects can be obtained. In other words, if the thermal oxidation in the step of FIG. 1(d) is performed without forming the silicon nitride film 27 on the surfaces of the N-type diffusion layers 26m and 26b, even the surfaces of the N-type diffusion layers 26&, 26b An oxide film grows. For example, if an oxide film 28, 211 with a width of 0.3 μm is to be formed on the side wall of the gate electrode 29, an 800× oxide film will grow on the surfaces of the N− type diffusion layers 26h and 26b. In order to perform arsenic ion implantation through this thick oxide film and lower the sheet resistance of the N+ type scattering layer 30a30b to a usable value, the ion implantation conditions are as follows: acceleration energy of 180 keV or higher, and dose of 2X. It requires about 10''' cm-2 or more.

However, such high acceleration energy and high dose ion implantation requires a long time and lacks productivity. Such drawbacks occur even when phosphorus is used for ion implantation, and when ions are implanted through an 800X oxide film,
801 ceV or more is required as acceleration energy.

Therefore, the N-type diffusion layer 26a.

It is desirable that the thickness of the insulating film on the surface of 26b be approximately 300X at most, and that the acceleration energy be 40 to 60 keV.

On the other hand, after oxidizing the sidewalls of the polycrystalline silicon pattern without forming a silicon nitride film on the surface of the N-type diffusion layer 26m6b, the oxide film grown on the surface of the N-type diffusion layer 26a, 26b is removed. It may be possible to thin it by etching. However, in isotropic etching such as an HF aqueous solution or chemical dry etching (CDE), the oxide film 28.28 on the side wall of the gate electrode 29 is also etched at the same time as the oxide film on the surface is etched.
The variations in the widths of the transistors 28 and 28 greatly increase the variations in the characteristics of the transistors. In addition, anisotropic etching using reactive ion etching (RIE)
Although there is no variation in the width of the oxide films 28, 28 on the side walls of the top electrode 29, RIE has the drawback of increasing costs because it lacks mass productivity. Jl! In addition, as the oxide film on the surface is etched, whether it is isotropic etching or anisotropic etching,
Since the field oxide film 22 is also etched at the same time,
Parasitic MO8) This may cause a decrease in the threshold voltage of the transistor, resulting in deterioration of device characteristics and reliability.

On the other hand, as in the method of the present invention, the N-q diffusion layer 26h,
After forming a silicon nitride film 27 on the surface of the gate electrode 26b, an oxide film 28° 2H is formed on the side wall of the gate electrode 29 and an N++
If ion implantation is performed to form a diffused layer, the ion implantation conditions will be relaxed, there will be no reduction in productivity, and there will be no risk of variation or deterioration of device characteristics.

In the above embodiment, after nitrogen ion implantation, heat treatment is performed in a non-oxidizing atmosphere to form the N-type diffusion layer 26h.
, 26b was formed with silicon nitride 1127, but
Other means may be used to form the silicon nitride film. Furthermore, other oxidation-resistant films may be formed instead of the silicon nitride film.

〔Effect of the invention〕

As described in detail above, if the method for manufacturing a semiconductor device of the present invention is used, there will be no decrease in productivity or increase in manufacturing costs (L
The source and drain regions of the DD structure can be formed with high precision.
This has remarkable effects such as improving device characteristics.

[Brief explanation of drawings]

FIG. 1(m) to (,) are LDDs in embodiments of the present invention.
MOS structure) A cross-sectional view showing a method of manufacturing a transistor,
Figure 2 (,) to (C) are conventional LDD a-structured MOS
) Cross-sectional view showing the method of manufacturing a transistor, Figure 3 (, )
and (b) are cross-sectional views showing another method of manufacturing a conventional LDD structure MOS transistor. 21... P-type silicon substrate, 22... Field oxide film, 23... Gate oxide film, 24... Polycrystalline silicon film pattern, 25... Silicon nitride film pattern,
26m, 26b--N- type diffusion layer, 27-- silicon nitride film, 28-- oxide film, 29-- gate electrode, 30
m, 30b.-N+ type scattering layer 31. 32... Source, drain region, 33... PSG film, 34... Source electrode, 35... Drain electrode.

Claims (3)

[Claims] (1) A step of forming a gate oxide film on the surface of a first conductivity type semiconductor substrate, a step of depositing an oxidizable conductive film on the entire surface, and then patterning it to form a pattern of the oxidizable conductive film; Using the pattern of the oxidizable conductive film as a mask, the second
A process of forming a low concentration diffusion layer of a second conductivity type by ion-implanting a conductivity type impurity at a low dose, a process of forming an oxidation-resistant film on the surface of the low concentration diffusion layer, and a process of thermal oxidation. forming an oxide film on the sidewalls of the pattern of the oxidizable conductive film, forming a gate electrode made of the remaining oxidizable conductive film; and using the gate electrode and its sidewall oxide film as a mask, a second conductivity type forming a second conductivity type high concentration diffusion layer by ion-implanting impurities at a high dose. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the oxidation-resistant film is a silicon nitride film. (3) A silicon nitride film is formed on the surface of the low concentration diffusion layer by ion-implanting nitrogen using the pattern of the oxidizable conductive film as a mask and then performing heat treatment. A method for manufacturing a semiconductor device.