JP2823819B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a very large scale integrated circuit device (VLSI), attempts are being made to lower the power supply voltage so as to operate with low power consumption. With a decrease in power supply voltage, an increase in delay time due to a decrease in driving force has become a serious problem.

In order to operate a CMOS device having a conventional structure at high speed at a low power supply voltage, it is necessary to (1) make the gate insulating film thinner (2) reduce the effective channel length (using a single drain structure) (3) parasitic effects (4) Reduction of (gate resistance, junction / mirror capacitance, etc.) (4) Reduction of threshold voltage, etc.

When operating at a low power supply voltage, an electric field generated by a gate is reduced, so that a leak current hardly flows. Therefore, a thinner gate insulating film can be used as compared with the case of operating at a normal voltage (1). In addition, the drain voltage is reduced, and deterioration due to hot carriers and the short channel effect are improved. For this reason, a single drain structure can be used instead of the LDD structure conventionally used in a sub-half micron device (2). This leads to a significant improvement of the driving force.

However, if the effects (1) and (2) are increased, the gate-drain overlap capacitance, which is a mirror capacitance, increases, and its ratio to the circuit operation (delay time, power consumption) is very large. Become. Therefore, in low-voltage operation, there is a demand for a device structure incorporating the effects (1) and (2) and having a small gate-drain overlap capacitance (3).

As a structure in which the parasitic capacitance of the gate drain overlap LDD is reduced, IEEE 1991 IEDM
Technical Digest pp541-544 T by K. Kurimoto et al.
Type gate structures have been proposed.

[0007]

However, the above T
A semiconductor device having a gate structure is not suitable for a fine semiconductor device of a sub-half micron region or less. According to the above-described conventional MOSFET device, since the side wall oxide film formed on the side surface of the gate electrode functions as a mask for ion implantation for forming the source / drain, the position of the source / drain is shifted outward. . Therefore, the effective channel length increases, and the driving force of the NchMOSFET transistor decreases.

According to the method of manufacturing a semiconductor device disclosed in the above-mentioned document, a heat treatment at 850 ° C. for 60 minutes is performed in a wet oxygen atmosphere after LDD implantation, thereby forming a polysilicon doped with P (phosphorus). The surface of the gate electrode is oxidized to form a gate bird's beak. This method has the following two problems.

(1) The heat treatment at 850 ° C. for several tens of minutes after the LDD implantation causes the LDD layer to diffuse in the vertical and horizontal directions, thereby easily causing deterioration due to the short channel effect.

(2) It is difficult to apply to dual gate technology.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to reduce the gate overlap capacitance without deteriorating the driving force and increasing the short channel effect. An object of the present invention is to provide an apparatus and a method of manufacturing the same.

[0012]

According to the present invention, there is provided a semiconductor device comprising:
A first conductivity type semiconductor substrate, a gate insulating film formed on a selected region of one main surface of the semiconductor substrate, a gate electrode formed on the gate insulating film, Source formed from two-conductivity type high concentration impurity diffusion layer /
A drain region, wherein both end portions of the gate insulating film are thicker than a center portion of the gate insulating film, and the source / drain region is located below the both end portions of the gate insulating film. A second portion having a thickness greater than or equal to the thickness of the first portion;
The impurity concentration of the portion is substantially equal to the impurity concentration of the second portion, thereby achieving the above object.

The first partial impurity concentration is 1 × 10 ¹⁹ c
It is preferably in the range of m ⁻³ to 1 × 10 ²⁰ cm ⁻³ .

In one embodiment, the semiconductor device further includes an L-shaped side wall formed on a side surface of the gate electrode,
The first portion of the drain region extends below the L-shaped sidewall.

In one embodiment, the thickness of the bottom portion of the L-shaped side wall is larger than the thickness of the side portion.

The gate electrode may be formed of a laminated structure including an amorphous silicon film and a polycrystalline silicon film. The semiconductor substrate may be an SOI substrate.

According to the method of manufacturing a semiconductor device of the present invention, there is provided a step of forming a gate insulating film on a first conductivity type semiconductor substrate, and a step of forming a gate electrode having an upper side portion selectively covered with an insulating film which is hardly permeable to oxidizing species. Forming a thermal oxide film on the exposed portion of the side surface of the gate electrode, and an oxidation step of making the edge of the gate insulating film thicker than the central portion of the gate insulating film; A first portion located below the both ends of the gate insulating film; and a second portion having a thickness equal to or greater than the thickness of the first portion, and the impurity concentration of the first portion is reduced. Forming a source / drain region substantially equal to the impurity concentration of the second portion in the semiconductor substrate, thereby achieving the above object.

The step of forming the gate electrode includes the steps of: depositing a conductive film on the gate insulating film; and forming a photoresist on the conductive film that defines the position and shape of the gate electrode. By etching with strong anisotropy in the vertical direction, using the photoresist as a mask,
A step of selectively removing an exposed portion of the conductive film, a step of removing the photoresist, a step of depositing an insulating film that is hardly permeable to oxidizing species, and etching with strong anisotropy in the vertical direction, Etching back the insulating film and the conductive film, thereby leaving a part of the insulating film on the side surface of the gate electrode.

The step of depositing the conductive film may include a step of depositing a polycrystalline silicon film on the gate insulating film and a step of depositing an amorphous silicon film on the polycrystalline silicon film. .

In one embodiment, the step of selectively removing the exposed portion of the conductive film includes the step of removing a part of the amorphous silicon film and a part of the polycrystalline silicon film.

The step of depositing the conductive film includes the steps of: depositing a first conductive layer on the gate insulating film; forming an oxide film on the first conductive layer; Second
Depositing a conductive layer.

It is preferable that the second conductive layer is formed from amorphous silicon.

The step of depositing the conductive film includes the step of depositing a first conductive layer on the gate insulating film and the step of forming a second conductive layer doped with impurities on the first conductive layer. And depositing a third conductive layer on the second conductive layer.

According to another method of manufacturing a semiconductor device of the present invention, there are provided a method of manufacturing a semiconductor device, a step of forming a gate insulating film on a first conductivity type semiconductor substrate, and a step of forming a gate electrode on the gate insulating film. A first step of oxidizing in an oxygen atmosphere substantially free of water vapor and hydrogen, and a second step of oxidizing in an oxygen atmosphere containing water vapor and hydrogen, wherein the end of the gate insulating film is An oxidation step of making a portion thicker than a central portion of the gate insulating film; a first portion located below the both ends of the gate insulating film; and a second portion having a thickness equal to or greater than the thickness of the first portion. And the first
Forming a source / drain region in the semiconductor substrate wherein the impurity concentration of the portion is substantially equal to the impurity concentration of the second portion, whereby the object is achieved.

According to another method of manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film on a first conductivity type semiconductor substrate, a step of forming a gate electrode on the gate insulating film,
Removing the exposed portion on the semiconductor substrate, and the oxide film present on the side surface of the gate electrode by isotropic etching, and forming a silicon nitride film on the exposed surface by removing the oxide film; An oxidation step of making an end of the gate insulating film thicker than a central portion of the gate insulating film; a first portion located below the both ends of the gate insulating film; and a thickness not less than the thickness of the first portion. Forming a source / drain region in the semiconductor substrate, the source / drain region having an impurity concentration of the first portion substantially equal to the impurity concentration of the second portion. And the above objects are achieved.

[0026] The step of forming the silicon nitride film may include a step of implanting nitrogen ions obliquely to a normal to a main surface of the semiconductor substrate and then annealing in a nitrogen atmosphere.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film having a three-layer structure of a silicon oxide film, a silicon nitride film and a silicon oxide film on a first conductivity type semiconductor substrate; Forming a gate electrode on the gate insulating film without removing at least the silicon nitride film of the gate insulating film formed on the semiconductor substrate; and forming an end of the gate insulating film on the gate insulating film. An oxidation step of making the gate insulating film thicker than a central portion thereof, a first portion located below the both ends of the gate insulating film, and a second portion having a thickness equal to or greater than the thickness of the first portion. And forming a source / drain region in the semiconductor substrate in which the impurity concentration of the first portion is substantially equal to the impurity concentration of the second portion, whereby the object is achieved. .

According to another method of manufacturing a semiconductor device of the present invention, there are provided a step of forming a gate insulating film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film on a first conductivity type semiconductor substrate; Depositing a conductive film on an insulating film, patterning a photoresist at a predetermined position to be a gate electrode on the conductive film, and using the photoresist as a mask, forming the gate insulating film and the conductive film. Selectively etching the multilayer film made of the film by strong anisotropic etching in the vertical direction until the gate insulating film is exposed; oxidizing the film in an oxygen atmosphere; And a second portion having a thickness equal to or greater than the thickness of the first portion, and the impurity concentration of the first portion is substantially equal to the impurity concentration of the second portion. The source / drain region is equal to include the steps of forming in said semiconductor substrate, said object is achieved.

According to another method of manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film on a first conductivity type semiconductor substrate, a step of forming a gate electrode on the gate insulating film,
Forming an L-type conductive film on a side surface of the gate electrode, and an insulating film provided in a concave portion of the L-type conductive film that is hardly permeable to oxidizing species; An oxidation step of oxidizing a portion that is not covered with the insulating film and further making an end of the gate insulating film thicker than a central portion of the gate insulating film; and a first step located below the both ends of the gate insulating film. And a second portion having a thickness equal to or greater than the thickness of the first portion, and the impurity concentration of the first portion is less than the second portion.
Forming a source / drain region in the semiconductor substrate substantially equal to the impurity concentration of the portion, thereby achieving the above object.

In one embodiment, the step of forming the gate electrode includes the steps of: depositing a first conductive film not doped with an impurity on the gate insulating film;
Forming a photoresist defining the position and shape of the gate electrode on the conductive film, and etching with strong anisotropy in the vertical direction using the photoresist as a mask. Selectively removing exposed portions of the semiconductor device, wherein the step of forming the L-type conductive film and the insulating film that is difficult to pass through the oxidizing species includes forming a second conductive film on the gate electrode and the semiconductor substrate. A step of depositing a second conductive film doped with a two-conductivity-type impurity, and a step of depositing an insulating film on the second conductive film that is hard to pass oxidizing species. Etching back the insulating film and the second conductive film that are hard to pass the oxidizing species by etching, and a part of the L-type conductive film and the insulating film that is hard to pass the oxidizing species is formed on the side surface of the gate electrode. And the step of leaving

According to another method of manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film on a semiconductor substrate of a first conductivity type; and a step of forming a first conductive film doped with ions on the gate insulating film. And the second not doped with ions
Forming a gate electrode composed of a multilayer film made of a conductive film, and forming an oxide film growing on a side portion of the first conductive film on a side portion of the gate electrode. Forming an L-type sidewall oxide film that is thicker than an oxide film that grows on the side of the substrate, further oxidizing the edge portion of the gate insulating film to be thicker than a central portion of the gate insulating film; Forming a second-conductivity-type high-concentration diffusion layer in the source / drain region and a second-conductivity-type high-concentration diffusion layer having a shallow junction under the L-type side wall. Is achieved.

According to another method of manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film on a semiconductor substrate of a first conductivity type and a step of forming a first conductive film doped with an impurity of a second conductivity type as a lower layer. Having a second undoped impurity
Forming a gate electrode having a conductive film as an upper layer on the gate insulating film, and thermally oxidizing a gate electrode on a side surface of the first conductive film and a side surface of the second conductive film of the gate electrode. An oxidation step of forming an L-type side wall oxide film and further making an end portion of the gate insulating film thicker than a central portion of the gate insulating film; And a second portion having a thickness greater than or equal to the thickness of the first portion, wherein the impurity concentration of the first portion is substantially equal to the impurity concentration of the second portion. Forming a source / drain region equal to in the semiconductor substrate, whereby the above object is achieved.

According to another method of manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film on a semiconductor substrate of a first conductivity type, a step of forming a first conductive film doped with ions of a first conductivity type, Depositing a second conductive film, which is not doped with, on the gate insulating film; depositing a third conductive film on the second conductive film; The first conductive film, the second conductive film, and the third conductive film;
Forming a photoresist defining a position and a shape of a gate electrode on a multilayer film made of a conductive film of the above, and using the photoresist as a mask, selectively subjecting the multilayer film to strong vertical anisotropic etching Etching the gate insulating film until the gate insulating film is exposed, a step of depositing an insulating film on the semiconductor substrate and the gate electrode, and selectively etching the insulating film in the vertical direction with strong anisotropy. Leaving the oxide film on the side wall of the gate electrode, wherein the oxide film growing on the side of the first conductive film on the side of the gate electrode is more dense than the oxide film growing on the side of the second conductive film. An oxidation step of increasing the thickness of the gate insulating film so that an end of the gate insulating film becomes thicker than a central portion of the gate insulating film; layer A step of forming, by etching with strong anisotropy selectively vertically, the steps of the source / drain regions of the semiconductor substrate is exposed, a step of siliciding the source / drain regions of the semiconductor substrate,
The method includes a step of selectively etching the third conductive film and a step of doping the gate electrode with ions of a second conductivity type by an ion implantation method, thereby achieving the above object.

According to another method of manufacturing a semiconductor device of the present invention, a step of forming an element isolation region on one principal surface of a second conductivity type semiconductor substrate and a step of forming a first island region in a specific island region separated by the element isolation region are performed. Forming a conductive well, and forming a gate insulating film on the second conductive type substrate and the first conductive type well region, and performing ion implantation on the first conductive type substrate. Instead of the step of forming the second conductive type high concentration diffusion layer in the source / drain regions, an ion implantation method is performed using the first ion implantation mask selectively formed on the first conductive type well region as a mask. Forming a high-concentration diffusion layer of a first conductivity type in source / drain regions on the substrate of the second conductivity type, and a second ion implantation mask selectively formed on the substrate of the second conductivity type. Using the first conductivity type wafer as a mask. Includes a step of forming a high concentration diffusion layer of the second conductivity type source / drain region of the region, the object is achieved.

According to another method of manufacturing a semiconductor device of the present invention, a step of forming an element isolation region on one main surface of a first conductivity type semiconductor substrate and a step of forming a second island in a specific island region separated by the element isolation region are performed. Forming a conductivity type well and forming a second conductivity type buried channel layer near the substrate surface and a second conductivity type threshold voltage control layer near the well region surface by ion implantation. Forming a gate insulating film on the substrate and the well region; depositing a first conductive film and a first insulating film on the gate insulating film; Patterning a photoresist at a predetermined position to be a gate electrode of a multilayer film including a first conductive film and the first insulating film; and using the photoresist as a mask, forming the gate insulating film and the first A conductive film and the first
Selectively etching the multilayer film composed of the insulating film by strong anisotropic etching in the vertical direction until the gate insulating film is exposed, and using an ion implantation mask selectively formed on the well region as a mask. Forming a second conductive type high concentration diffusion layer in source / drain regions on the substrate by ion implantation, selectively etching the first insulating film; Depositing a second insulating film on the gate electrode, selectively leaving the second insulating film on the side wall of the gate electrode by vertically strong anisotropic etching, As a result, the first / drain regions on the well region
Forming a conductive-type high-concentration diffusion layer, and simultaneously doping the gate electrode with ions of a first conductive type, thereby achieving the object described above.

Before forming the second conductive type high concentration diffusion layer in the source / drain region on the semiconductor substrate, the first conductivity type low concentration diffusion is formed in the source / drain region of the well region by ion implantation. Forming a first conductive type punch-through stopper layer in the source / drain region of the semiconductor substrate.

According to another method of manufacturing a semiconductor device of the present invention, a step of forming an element isolation region on one main surface of a first conductivity type semiconductor substrate and a step of forming a second island in a specific island region separated by the element isolation region are performed. Forming a conductivity type well and forming a second conductivity type buried channel layer near the substrate surface and a second conductivity type threshold voltage control layer near the well region surface by ion implantation. Forming a gate insulating film on the substrate and the well region; forming a first conductive film on the gate insulating film doped with ions of a first conductivity type; Depositing a first conductive film on the second conductive film, depositing a first insulating film on the second conductive film, forming the gate insulating film, the first conductive film, and the second conductive film on the second conductive film. A predetermined gate electrode of a multilayer film composed of a conductive film and the first insulating film. Patterning a photoresist on the substrate, and using the photoresist as a mask, selecting a multilayer film including the gate insulating film, the first conductive film, the second conductive film, and the first insulating film. A step of etching until the gate insulating film is exposed by strong anisotropic etching in a vertical direction, and an oxide film that grows on the side of the first conductive film on the side of the gate electrode is formed on the side of the second conductive film. An oxidation process in which the oxide film grows thicker than the oxide film grown on the side of the conductive film, and an end portion of the gate insulating film becomes thicker than a central portion of the gate insulating film; Using the ion implantation mask as a mask,
Forming a second conductive type high concentration diffusion layer in the source / drain region on the substrate; selectively etching the first insulating film; Depositing a second insulating film on the side wall of the gate electrode, selectively leaving the second insulating film on the side wall of the gate electrode by strong anisotropic etching in the vertical direction, and forming the well region by ion implantation. Forming a high-concentration diffusion layer of the first conductivity type in the upper source / drain region, and simultaneously doping the gate electrode with ions of the first conductivity type, thereby achieving the object described above.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

(First Embodiment of Semiconductor Device) FIG. 1 is a sectional view of a first embodiment of a semiconductor device according to the present invention. The semiconductor device of FIG. 1 includes a P-type semiconductor substrate 11, a P-type semiconductor substrate 11,
The gate oxide film 12 formed thereon, the gate electrode 13 provided through the gate oxide film 12, the L-type sidewall oxide film 14 formed on the side surface of the gate electrode 13, and the source / source of the P-type semiconductor substrate 11. An N-type high concentration source / drain diffusion layer 15 provided in the drain region is provided.

Both end portions of the gate oxide film 12 are formed thicker than the central portion. For example, the thickness at the center is 6 nm.
In this case, the thickness at both ends is set to about 10 to 50 nm. When the width of the gate electrode (dimension measured along the channel length direction) is, for example, 300 nm, each width (dimension measured along the channel length direction) of the relatively thick ends of the gate oxide film 12 is: 20-7
The width of a flat central part which is about 0 nm and is relatively thin (dimension measured along the channel length direction)
Is 160 to 260 nm.

The junction depth (layer thickness) D1 of the high-concentration source / drain diffusion layer 15 at the thick end portions of the gate oxide film 12 and the lower portion of the L-type sidewall oxide film 14 is the same as the high-concentration source / drain The diffusion layer 15 is formed shallower than the junction depth (layer thickness) D2. Therefore, the spread of the electric field extending from the source / drain diffusion layer 15 in the channel direction is effectively suppressed, and the fine MOSFE
The reduction of the threshold voltage (Vt) specific to T is effectively suppressed. Preferably, the junction depth D1 is in the range of 50 to 100 nm, and the junction depth D2 is 100 to 150 nm.
Is preferably within the range.

The high concentration source / drain diffusion layer 15
Of the portion having the junction depth D1 is 1 × 1
0 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ^−3, which is substantially equal to the impurity concentration at the junction depth D2. Since the impurity concentration of the LDD is usually 1 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ¹⁹ cm ⁻³ or less, the portion of the junction depth D1 is different from the LDD. High concentration source / drain diffusion layer 1 instead of LDD
Since the end portion 5 extends to the lower surface of the thick portion at both ends of the gate oxide film 12, the capacitance between the gate and the drain and the capacitance between the gate and the source can be reduced without lowering the drain current.

(Second Embodiment of Semiconductor Device) FIG. 2 is a sectional view of a second embodiment of the semiconductor device according to the present invention. FIG.
The semiconductor device of the first embodiment includes a P-type semiconductor substrate 21, a gate oxide film 22 formed on the P-type semiconductor substrate 21, and a gate oxide film 2.
2, a gate electrode 23 provided through the gate electrode 2 and an N-type high-concentration source / drain diffusion layer 24 provided in a source / drain region of the P-type semiconductor substrate 21.

A feature of the embodiment shown in FIG. 2 is that the gate electrode 23 is composed of two layers of a polycrystalline silicon film 23b and an amorphous silicon film 23a. The presence of the amorphous silicon film 23a can effectively prevent penetration of B (boron) from the polycrystalline silicon film 23b into the semiconductor substrate 21 which is a problem in the dual gate technology. Note that the gate electrode itself composed of the two layers described above is the same as the 1990 Digest of the Intl. Symposium on
VLSI Technology pp111-112 H.-H. Tseng et al.

In this embodiment, as in the first embodiment, the high-concentration source / drain diffusion layers 24 extend to the lower surfaces of the thick portions at both ends of the gate oxide film 22 so that the gate current can be reduced without reducing the drain current. The capacitance between the drain and the capacitance between the gate and the source can be reduced.

(Embodiment 3 of the Semiconductor Device) FIG. 3 is a sectional view of a third embodiment of the semiconductor device according to the present invention. FIG.
In the semiconductor device of the first embodiment, an SOI substrate 31, a gate oxide film 32 formed on the SOI substrate 31, a gate electrode 33 provided via the gate oxide film 32, and N A high concentration source / drain diffusion layer.

The feature of the embodiment shown in FIG. 3 is that the high concentration source / drain diffusion layer 34 extends to the lower surface of the thick portion at both ends of the gate oxide film 32 so that the gate drain is not reduced without reducing the drain current. The capacitance between the gate and the gate-source can be reduced. In a MOSFET formed on a substrate having an SOI structure, the ratio of the junction capacitance to the delay time is very small compared to the gate capacitance, and the ratio of the gate-drain capacitance, which is a mirror capacitance, to the delay time in low-voltage operation is very small. large. Therefore, when the MOSFET formed on the substrate having the SOI structure adopts the T-type gate structure, the capacitance between the gate and the drain can be reduced, so that the effect of improving the delay time is very large.

(Method 1 of Manufacturing Semiconductor Device) An embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 4 (a) to 4 (g).

First, reference is made to FIG. After forming a gate oxide film 1102 to a thickness of about 8 nm on a P-type semiconductor substrate 1101, an undoped polycrystalline silicon film is formed on the gate oxide film 1102.
1103 is deposited to a thickness of about 330 nm. Thereafter, the gate electrode 11 is formed on the selected region on the polycrystalline silicon film 1103.
A photoresist 1104 having a pattern defining the shape and position of 06 is formed.

Next, as shown in FIG. 4B, an etching step having strong anisotropy in the vertical direction is performed using the photoresist 1104 as a mask. Through this etching step, portions of the polycrystalline silicon film 1103 other than the portion to be the gate electrode 1106 are etched to a thickness of about 90 nm.

As shown in FIG. 4C, a photoresist
After removing 1104, a silicon nitride film (thickness: about 5 nm) 1105 is used as a film that is difficult to pass oxidizing species.
Deposits on 1103.

As shown in FIG. 4D, the gate oxide film 11
The multi-layered film composed of 02, the polycrystalline silicon film 1103, and the silicon nitride film 1105 is etched by an etching step having strong anisotropy in the vertical direction. The etching is performed so that the silicon nitride film 1105 is left on the side surface of the gate electrode 1106 and the gate oxide film 1102 is exposed. As a result, a gate electrode 1106 is formed. At this stage, the gate electrode
The upper part of the side surface of 1106 is covered with the silicon nitride film 1105, but the lower part of the side surface is exposed. The exposed side height is about 90 nm.

Next, a thermal oxidation process is performed at 850 ° C. for 70 minutes in a wet atmosphere, thereby forming a side surface of the gate electrode 1106 which is not covered with the silicon nitride film 1105 as shown in FIG. A thermal oxide film 1107 is grown to a thickness of about 60 nm. The thermal oxide film 1107 grows about 30 nm outward in the horizontal direction from the position of the gate side face before thermal oxidation and 30 n
grow about m. The thermal oxidation process allows the substrate
60n measured along the direction perpendicular to the main surface of 1101
An oxide film 1107 having a thickness of about m also grows on the substrate 1101.
Hereinafter, the thickness of the oxide film formed in this thermal oxidation process is
Defined as "reoxidized film thickness". In this embodiment, the thickness of the re-oxidized film is about 60 nm.

Next, as shown in FIG. 4F, an oxide film 1107 is formed by an etching process having strong anisotropy in the vertical direction.
Is etched from its upper surface by about 60 nm. The thickness (length measured in a direction parallel to the main surface of the substrate) of the oxide film 1107 on the side surface of the gate electrode 1106 under the silicon nitride film 1105 is about 30 nm.

As shown in FIG. 4G, for example, As ions are implanted as N-type impurity ions at an implantation energy of 80 nm.
After implantation into the substrate 1101 at KeV and an implantation dose of about 6 × 15 cm ⁻² , a heat treatment process at 850 ° C. is performed. Thus, an N-type high concentration diffusion layer 1108 is formed in the source / drain region of the P-type substrate 1101. The N-type high concentration diffusion layer 1108 has a shallower junction in the region below the L-type side wall than in other regions. This is because impurity ions that pass through the L-type side wall and reach the substrate 1101 are distributed at a position shallower than impurity ions that pass through the flat and relatively thin portion of the oxide film 1107 and reach the substrate 1101. It is. By the heat treatment after the ion implantation, the impurity ions diffuse in the vertical and horizontal directions, so that the impurity ions that pass through the L-type sidewall and reach the substrate 1101 diffuse toward the region directly below the center of the gate electrode.

Impurity ion implantation for the N-type high-concentration diffusion layer 1108 is simultaneously performed on the gate electrode, and an N-type polysilicon gate electrode 1106 is obtained.

When a doped polycrystalline silicon film is used in place of the undoped polycrystalline silicon film 1103 in the step of FIG. 4A, the oxidation time is shortened in the step of FIG. This is because the oxidation rate of the doped polycrystalline silicon film is higher than the oxidation rate of the undoped polycrystalline silicon film 1103. When the oxidation time becomes shorter,
Since the oxide film on the substrate 1101 grows, for example, only about 15 nm, there is no need to perform the etching step of FIG. When the etching of FIG. 4F is not performed,
The oxide film 1107 located on the side of the gate electrode 1106 which is not covered by the silicon nitride film 1105 is left protruding more laterally than the side of the gate electrode, so that the source / drain offset is large. Become. In order to reduce the amount of the offset, it is necessary to perform etching in the step of FIG. 4B until the thickness of the polycrystalline silicon film 1103 becomes about 40 nm.

According to the above manufacturing method, the semiconductor device of FIG. 1 can be easily manufactured. In particular, a gate oxide film having an increased thickness at both ends and an L-shaped sidewall oxide film for forming a high-concentration impurity diffusion layer having a stepped junction depth can be easily formed in one thermal oxidation step. .

The semiconductor device thus formed and the conventional semiconductor device were evaluated for short channel effect using process / device simulation. Hereinafter, the evaluation results will be described with reference to the drawings.

FIGS. 5A and 5B respectively show
NchMOSFET of the Present Invention and NchMOSF of Conventional Example
For ET, respective impurity concentration profiles are shown.
The gate length is 0.2 μm and the oxide film thickness is 4 nm. The N-type high concentration source / drain diffusion layer is formed by As ion implantation, and the Vt control is formed by B ion implantation also serving as a punch-through stopper.

In FIGS. 5A and 5B, the B density
Degree profile curve is from bottom to top of substrate
And 1 × 10¹⁷, 2 × 10¹⁷, 4 × 10¹⁷, 1 × 1
0¹⁸, 2 × 10¹⁸, 4 × 10¹⁸(Cm^-3) Shows the value
I have. The profile curve of As concentration shows the channel under the gate.
1 × in order from the center of the tunnel to the source / drain diffusion layer.
10 ¹⁷, 2 × 10¹⁷, 4 × 10¹⁷, 1 × 10¹⁸, 2 × 1
0¹⁸, 4 × 10¹⁸, 1 × 10¹⁹, 2 × 10¹⁹, 4 × 10
¹⁹, 1 × 10²⁰(Cm^-3).

As can be seen from FIGS. 5 (a) and 5 (b), in the conventional example, the source and drain diffusion layers are not so far apart at a deep position in the substrate, but in the present invention, is seperated. Furthermore, a high-concentration portion of the source / drain diffusion layer at the gate end (1 × 10 ²⁰ cm ⁻³ )
Are the same, and the effective gate lengths are also substantially equal. As a result, the present invention can dramatically improve the short channel effect while maintaining the same driving force as in the conventional example.

FIG. 6 shows the NchMO of the present invention and the conventional NchMO having the impurity concentration profiles of FIGS. 5 (a) and 5 (b).
A comparison of the sub-threshold characteristics of the SFET is shown. The horizontal axis shows the gate voltage, and the vertical axis shows the drain current when the drain voltage is 0.1 V and 1.5 V. The threshold voltage is a gate voltage at which the drain current becomes 0.25 uA. As can be seen from FIG. 6, in the conventional example, the difference between the threshold voltages of the drain voltage of 0.1 V and 1.5 V is 0.25 V or more and the short channel effect is extremely deteriorated. The difference between the threshold voltages of 0.1 V and 1.5 V is remarkably improved to about 0.10 V.

(Second Embodiment of Semiconductor Device Manufacturing Method)
Another embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 7A to 7G.

First, as shown in FIG. 7A, after a gate oxide film 1202 (thickness: 8 nm) is formed on an N-type semiconductor substrate 1201, an undoped polycrystalline silicon film (thickness: 90 nm)
m) 1203 and an amorphous silicon film (thickness: 240 n)
m) 1204 is deposited on the gate oxide film 1202. afterwards,
A photoresist 1205 having a pattern defining the shape and position of the gate electrode 1207 is formed on a selected region on the polycrystalline silicon film 1203.

As shown in FIG. 7B, a photoresist
With the use of 1205 as a mask, the exposed portions of the amorphous silicon film 1204 and the polycrystalline silicon film 1203 are etched to a thickness of about 90 nm by an etching step having strong anisotropy in the vertical direction.

As shown in FIG. 7C, a photoresist
After removing 1205, a silicon nitride film 1206 is deposited to a thickness of about 5 nm as a film through which oxidized species cannot easily pass.

As shown in FIG. 7D, the gate oxide film 12
The multi-layered film composed of 02, the polycrystalline silicon film 1203 and the silicon nitride film 1206 is etched by an etching step having strong anisotropy in the vertical direction. The etching is performed so that the silicon nitride film 1206 is left on the side surface of the gate electrode 1207 and the gate oxide film 1202 is exposed. Thus, a gate electrode 1207 having the polycrystalline silicon film 1203a and the amorphous silicon film 1204a is formed.

As shown in FIG. 7E, a silicon nitride film
An oxide film 1208 is grown on the side of the gate electrode 1207 in which 1206 is not left, 30 nm each from the gate end to the outside and inside, and a total of about 60 nm, and at the same time, the end of the gate oxide film 1202 is closer to the center of the gate oxide film 1202 than the center. Oxidize in an oxygen atmosphere to increase the thickness. At this time, an oxide film 1208 of about 60 nm grows on the substrate 1201. The oxidation conditions at this time are 850 ° C. for about 70 minutes in a wet atmosphere.

As shown in FIG. 7F, the oxide film 1208 is formed to a thickness of 60 nm by etching having strong anisotropy in the vertical direction.
Etch to the extent. At this time, the thickness of the oxide film 1208 on the side of the gate electrode 1207 where the silicon nitride film 1206 is not left becomes about 30 nm.

As shown in FIG. 7G, for example, BF ₂ ions are implanted as P-type impurity ions at an implantation energy of 4.
After implanting 0 KeV and an implantation dose of about 4 × 15 cm ⁻² , a heat treatment step at 850 ° C. is added. Thus, the P-type high concentration diffusion layer 1209. A silicon nitride film 1206 to form a P-type high-concentration diffusion layer 1209 having a shallow junction under oxide film 1208 side of the gate electrode 1207 which is not leaving, P-type doped with BF ₂ ions into the gate electrode 1207 simultaneously A polysilicon gate electrode 1207 is formed.

When a doped polycrystalline silicon film is used in place of the undoped polycrystalline silicon film 1203 in the step of FIG. 7A, the oxidation time is shortened in the step of FIG. The oxide film grows only about 15 nm. Therefore, it is not necessary to perform the step of FIG. Further, in order to prevent the source / drain offset due to the oxide film 1208 on the side of the gate electrode 1207 where the silicon nitride film 1206 is not left, the polycrystalline silicon film 1203 other than the gate electrode 1207 in the step of FIG.
It is necessary to etch the polycrystalline silicon film 1203 in a state where it is left to the extent.

(Third Embodiment of Semiconductor Device Manufacturing Method)
With reference to FIGS. 8A to 8G, still another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described.

As shown in FIG. 8A, an N-type semiconductor substrate
After a gate oxide film (thickness: about 7 nm) 1302 is formed on 1301, an undoped polycrystalline silicon film (thickness: about 90 nm) 1303 is deposited on the gate oxide film 1302. Next, a natural oxide film 1304 is formed on the polycrystalline silicon film 1303, and an amorphous silicon film 1305 is deposited to a thickness of about 240 nm. The native oxide film 1304 is formed by depositing a polycrystalline silicon film 1303 and then exposing the film to the atmosphere. Desirably, the range of the native oxide film 1304 is between 2 nm and 5 nm.

Next, a photoresist for defining the position and shape of the gate electrode 1308 is formed on the amorphous silicon film 1305.
Form 1306. As shown in FIG. 8B, the polycrystalline silicon film 1303 other than the gate electrode 1308 is left with a thickness of about 70 nm by selective strong anisotropic etching in the vertical direction using the photoresist 1306 as a mask. The amorphous silicon film 1305 and the natural oxide film 1304 are etched. At this time, the amorphous silicon film 1305 and the oxide film
By increasing the etching selectivity of 1304 and detecting SiO2 when etching the oxide film 1304, etching can be performed while leaving only the polycrystalline silicon film 1303.

As shown in FIG. 8C, the photoresist
Silicon nitride film 1307 that removes 1306 and makes it difficult for oxidizing species to pass through
Is deposited to a thickness of about 5 nm. Thereafter, as shown in FIG. 8D, the multilayer film including the gate oxide film 1302, the polycrystalline silicon film 1303, and the silicon nitride film 1307 is selectively etched in the vertical direction with strong anisotropy to form a silicon nitride film. Gate oxide film 13 such that 1307 is left on the side of gate electrode 1308
Etch until the 02 is exposed.
a and an amorphous silicon film 1305a are formed.

As shown in FIG. 8E, a silicon nitride film
On the side of the gate electrode 1308 where the 1307 is not left, an oxide film 1309 of about 60 nm in total is grown on the outside and the inside from the gate end to a total of about 60 nm, and at the same time, the end of the gate oxide film 1302 is located from the center of the gate oxide film 1302. Oxidize in an oxygen atmosphere to increase the thickness. At this time, an oxide film 1309 of about 60 nm grows on the substrate 1301. The oxidation conditions at this time are 850 ° C. for about 70 minutes in a wet atmosphere.

As shown in FIG. 8 (f), the oxide film 1309 grown on the substrate in the step of FIG. 8 (e) is etched by about 90 nm by selective strong anisotropic etching in the vertical direction. At this time, the thickness of the oxide film 1309 on the side of the gate electrode 1308 where the silicon nitride film 1307 is not left becomes about 30 nm.

As shown in FIG. 8G, for example, BF ₂ ions are implanted as P-type impurity ions at an implantation energy of 4.
After implanting 0 KeV and an implantation dose of about 4 × 15 cm ⁻² , a heat treatment step at 850 ° C. is added. Thus, a P-type high concentration diffusion layer 1310 is formed on the N-type semiconductor substrate 1301, and at the same time, BF ₂ ions are doped into the gate electrode 1308 to form a P-type polysilicon gate electrode 1308. P-type high concentration diffusion layer
1310 has the same profile as the N-type high concentration diffusion layer 15 of the embodiment of FIG.

When a doped polycrystalline silicon film is used instead of the undoped polycrystalline silicon film 1303 in the step of FIG. 8A, the oxidation time is shortened in the step of FIG. Since the oxide film grows only about 15 nm in thickness, there is no need to perform the step of FIG. In order to prevent the source / drain offset due to the oxide film 1309 on the side of the gate electrode 1308 where the silicon nitride film 1307 is not left, the polycrystalline silicon film 1303 other than the gate electrode 1308 has a thickness of 40 nm in the step of FIG. It is necessary to etch the polycrystalline silicon film 1303 in a state where it is left to such an extent.

According to the manufacturing method of this embodiment, (1) the driving force is increased by preventing the reduction of the effective channel length because the oxide film does not grow on the entire surface of the gate electrode, and (2) the short channel is formed by the L-type side wall structure. Monitoring of SiO2 detected at the time of etching a semiconductor device that can be expected to have three effects of suppressing effects and (3) effectively preventing penetration of B from P-type polysilicon into bulk, which is a problem in dual gate technology. And can be easily manufactured in a self-aligned manner.

(Fourth Embodiment of Semiconductor Device Manufacturing Method)
With reference to FIGS. 9A to 9D, still another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described.

First, reference is made to FIG. After forming a gate oxide film 1402 on the P-type semiconductor substrate 1401 to a thickness of about 8 nm, an undoped polycrystalline silicon film is deposited on the gate oxide film 1402 to a thickness of about 330 nm. Thereafter, a photoresist having a pattern defining the shape and position of the gate electrode 1406 is formed on a selected region on the polycrystalline silicon film, and the gate oxide film 1402 is exposed by strong anisotropic etching in the vertical direction. The polycrystalline silicon film is etched until a gate electrode 1403 is formed.

Next, as shown in FIG. 9B, the gate electrode 1403 is placed in a dry oxygen atmosphere containing neither water vapor nor hydrogen.
Is oxidized at 850 ° C. for about 20 minutes. By this oxidation step, the side wall oxide film 14 is formed on the upper surface and both side surfaces of the gate electrode 1403.
04 is formed, and both ends of the gate oxide film 1402 become thicker. As a result, the lower surface end of the gate electrode 1403 has a round shape. Oxidation in a dry oxygen atmosphere is suitable for sharply increasing both end portions of the gate oxide film 1402.

Next, the gate electrode 1403 is oxidized at 850 ° C. for about 10 minutes in a wet oxygen atmosphere containing water vapor and hydrogen. By this second oxidation step, FIG.
As shown in (1), the lower surface end of the gate electrode 1403 is further oxidized to exhibit a shape like a bird's beak of LOCOS.
This is because oxygen is supplied through the gate oxide film 1402 to the gate electrode 14.
03 because it is supplied to the bottom. Oxidation in a wet oxygen atmosphere promotes oxidation in a direction parallel to the main surface of the substrate, and widens a thicker portion than both ends of the gate oxide film 1402. In other words, the “bird's beak” extends toward the center of the lower surface of the gate electrode 1403.

Next, as shown in FIG. 9D, for example, As ions are implanted as N-type impurity ions at an implantation energy of 80 KeV and an implantation dose of about 6 × 15 cm ^−2.
After being injected into 1401, a heat treatment step at 850 ° C. is performed. Thus, an N-type high concentration diffusion layer 1405 is formed in the source / drain region of the P-type substrate 1401. By this ion implantation,
The gate electrode 1402 is also doped with impurity ions.

According to the present manufacturing method, the height of the bird's beak oxide film below the gate electrode is increased by dry oxidation, and the bird's beak oxide film is extended inside by wet oxidation. Therefore, a semiconductor device having a T-type gate structure can be manufactured with high yield.

(Fifth Embodiment of Semiconductor Device Manufacturing Method)
Referring to FIGS. 10A to 10E, still another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described.

First, reference is made to FIG. A gate electrode (thickness: about 330 nm) 1503 made of an undoped polycrystalline silicon film is formed on a P-type semiconductor substrate 1501 via a gate oxide film (thickness: about 8 nm) 1502.

As shown in FIG. 10B, the gate electrode 15 is formed by isotropic wet etching using hydrofluoric acid.
The gate oxide film 1502 at the end of 03 is etched.

Next, as shown in FIG.
Nitrogen ions are implanted into the source / drain regions on the surface 01 and the surface of the gate electrode 1503 at an implantation energy of 2 KeV and an implantation dose of about 4 × 13 cm ⁻² . Thereafter, by performing a heat treatment at 850 ° C. in a nitrogen atmosphere, silicon reacts with nitrogen, and as a result, a silicon nitride film 1504 is formed on the surface of the source / drain region on the substrate 1501 and the surface of the gate electrode 1503. Is done. Next, in an oxygen atmosphere, the gate electrode
By oxidizing 1503, both ends of the gate oxide film 1502 become thicker than the center of the gate oxide film 1502, as shown in FIG.

As shown in FIG. 10E, for example, As ions are implanted as N-type impurity ions at an implantation energy of 80 nm.
After implanting KeV and an implantation dose of about 6 × 15 cm ⁻² ,
By heat treatment at 850 ° C., an N-type high concentration diffusion layer 1505 is formed in the source / drain region on the P-type 1501 substrate. Through these steps, As ions are doped into the gate electrode 1503 at the same time, and an N-type polysilicon gate electrode 1503 is formed.

According to the manufacturing method of this embodiment, since the silicon nitride film is formed on the side wall of the gate electrode, the oxide film does not grow on the entire side surface of the gate electrode. For this reason,
The reduction of the effective channel length is prevented, and the driving force can be increased. Further, since a silicon nitride film is formed on the substrate surface, no oxide film grows on the substrate surface. Therefore, an oxide film etching step is not required before ion implantation for forming the source / drain, and it is possible to prevent the element isolation oxide film (LOCOS film) from being thinned by the oxide film etching step.

(Sixth Embodiment of Semiconductor Device Manufacturing Method)
Another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

As shown in FIG. 11A, a gate oxide film 1602 composed of three layers of a silicon oxide film / silicon nitride film / silicon oxide film was formed on a P-type semiconductor substrate 1601 to a thickness of about 8 nm in terms of an oxide film. After that, a polycrystalline silicon film 1603 is deposited on the gate oxide film 1602 to a thickness of about 330 nm. Next, a photoresist 1604 that defines the position and shape of the gate electrode on the polycrystalline silicon film 1603 is formed.

Next, as shown in FIG. 11B, using the photoresist 1604 as a mask, the polycrystalline silicon film 1603 is etched by an etching step having strong anisotropy in the vertical direction to form a gate electrode 1605. . This etching is performed until the gate oxide film 1602 is exposed. Care is taken not to etch until the substrate 1601 is exposed.

As shown in FIG. 11C, the gate electrode 1605 is oxidized in an oxygen atmosphere so that both ends of the gate oxide film 1602 are thicker than the center of the gate oxide film 1602.
In this oxidation step, an oxide film 1606 is formed on the side and upper surfaces of the gate electrode 1605.

As shown in FIG. 11D, for example, As ions are implanted as N-type impurity ions at an implantation energy of 8 nm.
After implanting 0 KeV and an implantation dose of about 6 × 15 cm ⁻² , a heat treatment step at 850 ° C. is added. Thus, the N-type high concentration diffusion layer 1607 is formed in the source / drain region of the P-type substrate 1601.
Is formed and the gate electrode 1605 is doped with As ions to form an N-type polysilicon gate electrode 1605.

According to the manufacturing method of this embodiment, the gate oxide film 1602 including the silicon nitride film is formed on the substrate surface.
To have an oxide film does not grow on the substrate surface. For this reason, an oxide film etching step before ion implantation for source / drain formation becomes unnecessary. A decrease in the thickness of the device isolation film (LOCOS film) due to the oxide film etching process can be prevented.

(Seventh Embodiment of Semiconductor Device Manufacturing Method)
With reference to FIGS. 12A to 12E, still another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described.

First, as shown in FIG. 12A, a gate oxide film (thickness: about 8 nm) 1702 is formed on a P-type semiconductor substrate 1701.
Through the first undoped polycrystalline silicon film (thickness: 3
A gate electrode 1703 of 30 nm) is formed.

Next, as shown in FIG. 12B, a second polycrystalline silicon film 1704 doped with P ions and a silicon nitride film 1705 which is hard to pass oxidizing species are formed in this order on the gate electrode 1703. And deposited on the substrate 1701.

As shown in FIG. 12C, a silicon nitride film is formed by an etching process having strong anisotropy in the vertical direction.
The 1705 and the polycrystalline silicon film 1704 are etched back. Through this step, a part (L-shaped) of second polycrystalline silicon film 1704 is left on the side surface of gate electrode 1703. Second
The side of the polycrystalline silicon film 1704 has a silicon nitride film 17
Part of 05 is left behind.

Next, an oxidation step is performed in an oxygen atmosphere. As shown in FIG. 12D, an oxide film grows on a portion of the L-shaped portion of the second polycrystalline silicon film 1704 which is not covered with the silicon nitride film 1705. The oxide film is a silicon nitride film
From the boundary surface between 1705 and the second polycrystalline silicon film 1704 (the surface extending perpendicular to the main surface of the substrate), laterally outside and inside, respectively, 3
Grow by 0 nm. As a result, both ends of the gate oxide film 1702 are thicker than the central portion of the gate oxide film 1702, and an oxide film 1706 having a thickness of about 10 nm grows on the substrate. Oxide film 1706 becomes thicker at a portion adjacent to gate oxide film 1702, and substantial L-type sidewall oxide film 1706 is formed.

Thereafter, as shown in FIG. 12 (e), for example, As ions are implanted as N-type impurity ions at an implantation energy of 80 KeV and an implantation dose of about 6 × 15 cm ⁻² , and then a heat treatment at 850 ° C. Add a process. In this way, the N-type high concentration diffusion layer 1707 is formed on the P-type substrate 1701 and the gate electrode 1703 is doped with As ions,
An N-type polysilicon gate electrode 1703a is formed. The N-type high-concentration diffusion layer 1707 has a shallower junction under the L-type sidewall oxide film than other portions.

According to the manufacturing method of this embodiment, the gate electrode
Oxidation of the side surface of 1703 is partially prevented by the silicon nitride film 1705, and a portion of the second polycrystalline silicon film 1704 that is not oxidized forms the gate electrode 1703a. As a result, the width (gate length) of the gate electrode 1703 is
The width is larger than the width (gate length) of the gate electrode 1703 shown in FIG. The gate electrode 1703 shown in FIG.
(Gate length) is determined by a mask layer that defines the planar layout of the gate electrode. Since the final gate width of the gate electrode 1703a is larger than the mask size, the gate electrode 1703a can be formed without increasing the area of the gate oxide film 1702 (without increasing the gate capacitance).
Can reduce the electrical resistance.

(Eighth Embodiment of Semiconductor Device Manufacturing Method)
With reference to FIGS. 13A to 13D, still another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described.

As shown in FIG. 13A, a gate oxide film (thickness: about 8 nm) 1802 and a P-type semiconductor substrate 1801 are formed on a P-type semiconductor substrate 1801.
A first polycrystalline silicon film (thickness: about 50 nm) 1803 doped with ions and an undoped second polycrystalline silicon film (thickness: about 280 nm) 1804 are deposited in this order. Thereafter, a photoresist 1805 defining the position and shape of the gate electrode 1806 is deposited on the gate oxide film 1802,
Polycrystalline silicon film 1803 and second polycrystalline silicon film 18
It is formed on a multilayer film made of 04.

As shown in FIG. 13B, the gate oxide film 1802, the first polycrystalline silicon film 1803, and the second The multilayer film including the polycrystalline silicon film 1804 is etched until the gate oxide film 1802 is exposed. Thus, the gate electrode 1806 including the first polycrystalline silicon film 1803a and the second polycrystalline silicon film 1804a
To form

Next, as shown in FIG. 13C, the first oxidation of the gate electrode 1806 is performed by a thermal oxidation process in an oxygen atmosphere.
An oxide film 1807 is grown on the side surface of the polycrystalline silicon film 1803a by 30 nm on the outside and on the inside, respectively, for a total of about 60 nm.
By this thermal oxidation step, simultaneously, 7 nm each on the outer and inner sides of the second polycrystalline silicon film 1804a, for a total of 1 nm.
An oxide film 1807 of about 4 nm grows. The oxide film forms an L-shaped side wall oxide film 1807 having an L-shape, and has both ends of the gate oxide film 1802 thicker than a central portion of the gate oxide film 1802. Note that an oxide film 1807 having a thickness of about 10 nm also grows on the substrate 1801.

As shown in FIG. 13D, for example, As ions are implanted as N-type impurity ions at an implantation energy of 8 nm.
After implanting 0 KeV and an implantation dose of about 6 × 15 cm ⁻² , a heat treatment process at 850 ° C. is performed. Thus, while forming the N-type high concentration diffusion layer 1808 on the P-type substrate, at the same time,
The gate electrode 1806 is doped with As ions to form an N-type polysilicon gate electrode 1806a. N-type high concentration diffusion layer
1808 has a shallow junction under the L-type sidewall oxide film.

According to the manufacturing method of this embodiment, (1) the driving force is maintained by preventing the increase of the effective channel length because the oxide film does not grow thickly on the entire side wall of the gate electrode, and (2) the short circuit is caused by the L-type side wall structure. A semiconductor device that can be expected to have two effects of suppressing the channel effect can be easily manufactured in a self-aligned manner using current LSI technology.

(Ninth Embodiment of Semiconductor Device Manufacturing Method)
A method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 14A, a gate oxide film (thickness: about 8 nm) 19 is formed on an N-type semiconductor substrate 1901.
02, a first polycrystalline silicon film (thickness: about 50 nm) 1903 doped with P ions on the gate oxide film 1902
And an undoped second polycrystalline silicon film (thickness: about 2
80 nm) 1904 and a TiN film (thickness: about 50 nm) 1905
Are deposited in this order. A photoresist 1906 for defining the position and shape of the gate electrode 1907 is formed on the TiN film 1905.

Next, as shown in FIG. 14B, the gate oxide film 1902, the first polycrystalline silicon film 1903, The multilayer film including the second polycrystalline silicon film 1904 and the TiN film 1905 is etched until the gate oxide film 1902 is exposed to form a gate electrode 1907.

As shown in FIG. 14C, the gate side wall 19 is formed.
08 HTO film (thickness: 30 nm)
And deposited on the substrate 1901.

As shown in FIG. 14D, the above multilayer film is etched by an etching step having strong anisotropy in the vertical direction.
The gate sidewall 1908 is formed with the TO film left.

Next, an oxide film is selectively grown on the side surface of the first polycrystalline silicon film 1903a in the gate electrode 1907 by a thermal oxidation process in an oxygen atmosphere. This oxide film grows about 30 nm inward from the side. On the side surface of the second polycrystalline silicon film 1904a, an oxide film grows about 7 nm inward from the side surface. As a result, the end of the gate oxide film 1902 is
It is thicker than the center. In this thermal oxidation step, an oxide film of about 10 nm grows on the substrate.

As a P-type impurity ion, for example, BF
₂ ions implantation energy 40 KeV, implantation dose 4
Implantation is performed at about × 15 cm ⁻² to form a P-type high concentration diffusion layer 1909 in the source / drain region of the N-type substrate 1901. Next, the etching process with strong anisotropy in the vertical direction
The oxide film on 1901 is removed to expose the surface of the P-type high concentration diffusion layer 1909.

[0120] Thereafter, as shown in FIG. 14 (e), silicided surface of the P-type high-concentration diffusion layer 1909, CoSi ₂ 1
Form 910.

As shown in FIG. 14F, the TiN film 1905
Is selectively etched. As N-type impurity ions, for example, P ions are implanted at an implantation energy of 20 KeV and an implantation dose of about 6 × 10 ¹⁵ cm ⁻² , and 850 is further implanted.
By adding a heat treatment step at a temperature of about 1100 ° C., the P-type high-concentration diffusion layer 1909 is formed.
Activate. At this time, at the same time, P
Doping with ions, the N-type polysilicon gate electrode 19
07b is formed.

Since the silicide layer CoSi ₂ 1910 functions as a mask for P ions, the P-type high concentration diffusion layer 19
During 09, no P ions are implanted.

According to the manufacturing method of this embodiment, the type of dopant for the high concentration diffusion layer and the polysilicon gate electrode can be made different.

(Tenth Embodiment of Semiconductor Device Manufacturing Method) Still another embodiment of a semiconductor device manufacturing method according to the present invention will be described with reference to FIGS. 15 (a) to 15 (f).

In this embodiment, a semiconductor device having a CMOS structure is manufactured.

First, as shown in FIG. 15A, an element isolation film (LOCOS) 2003 is formed on one main surface of a P-type semiconductor substrate 2001.
Is formed, an N-type well 2002 is formed in a specific island region separated by the LOCOS 2003.

Further, by implanting, for example, P ions as N-type impurity ions at an implantation energy of 20 KeV and an implantation dose of about 6 × 11 cm ⁻² , the N-type buried channel layer 2004 a is formed near the surface of the P-type semiconductor substrate 2001. At the same time, an N-type threshold voltage control layer 2004b is formed near the surface of the N-type well 2002 region.

As shown in FIG. 15B, after a gate oxide film (thickness: 8 nm) 2005 is formed on a P-type semiconductor substrate 2001, a polycrystalline silicon film serving as a gate electrode 2006 is formed on the gate oxide film 2005. (Thickness: about 330 nm) and an HTO film (thickness: about 50 nm) 2007 are deposited. Next, HTO
A photoresist that defines the position and shape of the gate electrode 2006 is formed on the film. Using the photoresist as a mask, the HTO film and the polycrystalline silicon film are removed from the gate oxide film 20 by an etching process having strong anisotropy in the vertical direction.
The gate electrode 2006 is formed by etching until 05 is exposed.

As shown in FIG. 15C, protection oxidation before LDD is performed. Thereby, the P-type substrate 2001 and the N-type well
An L-type oxide film 2008 having a thickness of about 7 nm on 2002 and a thickness of about 10 nm on the gate electrode 2006 is formed.

As shown in FIG. 15D, for example, BF ₂ ions are implanted as P-type impurity ions at an implantation energy of 20 KeV and an implantation dose of about 6 × 12 cm ^−2, so that N-type well regions 2002 are implanted. P-type low concentration diffusion layer
2009b, a P-type punch-through stopper layer 2009a is formed on a P-type semiconductor substrate 2001.

As shown in FIG. 15E, the well region 20
For example, As ions are implanted as N-type impurity ions at an implantation energy of 60 KeV and an implantation dose of 6 × 15 cm using an ion implantation mask 2010 selectively formed on the substrate.
^{About -2} implanted, N-type high concentration diffusion layer on P-type semiconductor substrate 2001
Form 2011. During this ion implantation, the gate electrode
Since the HTO film 2007 is provided on the substrate 2006, As ions are not implanted into the gate electrode 2006.

As shown in FIG. 15F, the HTO film 2007
Is selectively etched. Next, on the gate electrode 2006 and the substrate 2001, an HTO film (thickness:
(About 30 nm), and an etching process having strong anisotropy in the vertical direction is used to form H on the side of the gate electrode 2006.
With the TO film left, a gate sidewall 2012 is formed. Further, as P-type impurity ions, for example, BF ₂ ions are implanted at an implantation energy of 40 KeV and an implantation dose of 3 × 15 cm ^−2.
About 850 ° C. to form a P-type high-concentration diffusion layer 2013 in the N-type well 2002 and to form a P-type polysilicon gate electrode 2006 by doping BF ₂ ions into the gate electrode 2006. Form. On this occasion,
Since the implantation energy and implantation dose of As ions implanted into the P-type semiconductor substrate 2001 are high, the effects of BF ₂ ions are canceled.

According to the method of manufacturing a semiconductor device of the present embodiment, a complementary semiconductor device having a P-type polysilicon single gate can be easily manufactured.

(Eleventh Embodiment of Semiconductor Device Manufacturing Method) Still another embodiment of a semiconductor device manufacturing method according to the present invention will be described with reference to FIGS. 16 (a) to 16 (f).

As shown in FIG. 16A, first, a LOCOS 2103 is formed on one main surface of a P-type semiconductor substrate 2101,
N-type well 2102 in a specific island area separated by COS 2103
To form

Further, as the N-type impurity ions, for example, P ions are implanted at an implantation energy of 20 KeV and an implantation dose of about 6 × 11 cm ⁻² , thereby forming the P-type substrate 21.
An N-type buried channel layer 2104a is formed near the surface of 01, and an N-type threshold voltage control layer 2104b is formed near the surface of the N-type well 2102.

As shown in FIG. 16B, after forming a gate oxide film (thickness: 8 nm) 2105 on a P-type semiconductor substrate 2101, a first polycrystalline silicon film (thickness) doped with B ions is formed. : About 50 nm) 2106, an undoped second polycrystalline silicon film (thickness: about 280 nm) 2107, and an HTO film (thickness: about 50 nm) 2108 are deposited on the gate oxide film 2105. Next, a photoresist that defines the position and shape of the gate electrode 2109 is formed on the multilayer film including the HTO film 2108. Using the photoresist as a mask, the first polysilicon film 2106, the second polysilicon film 2107 and the HT
The O film 2108 is etched by an etching step having strong anisotropy in the vertical direction until the gate oxide film 2105 is exposed to form a gate electrode 2109.

As shown in FIG. 16 (c), the thermal oxidation process in an oxygen atmosphere causes the side surface of the first polycrystalline silicon film 2106 of the gate electrode 2109 to be 30 nm outside and inside from the gate end, respectively, for a total of 60 nm. An oxide film 2110 having a thickness of about the same is grown. An oxide film 2110 is formed on the side surface of the second polycrystalline silicon film 2107 by 7 nm from the side surface to the outside and inside, respectively, for a total of about 14 nm.
Grow. At this time, the grown oxide film 2110 becomes an L-shaped side wall oxide film 2110 having an L shape, and at the same time, the edge of the gate oxide film 2105 is thicker than the center of the gate oxide film 2105. At this time, an oxide film 2110 of about 10 nm grows on the substrate.

As shown in FIG. 16D, for example, BF ₂ ions are implanted as P-type impurity ions at an implantation energy of 20 KeV and an implantation dose of about 6 × 12 cm ^−2, so that the N-type well 2102 region is formed. P-type low concentration diffusion layer 21
11b is formed, and a P-type punch-through stopper layer is formed on the substrate 2101.
2111a is formed.

As shown in FIG. 16E, the well region 21
Using an ion implantation mask 2112 selectively formed on the mask 02 as a mask, for example, As ions are implanted as N-type impurity ions at an implantation energy of 60 KeV and an implantation dose of 6 × 1.
Implant about 5 cm ^-2 and N-type high concentration diffusion layer on P-type substrate 2101
Form 2113. At this time, HTO is formed on the gate electrode 2109.
Since the film 2108 is provided, As ions are not implanted into the gate electrode 2109.

As shown in FIG. 16F, the HTO film 2108
Is selectively etched. Next, an HTO film serving as a gate sidewall 2114 is formed on the gate electrode 2109 and the substrate 2101 by a thickness of 30 n.
The gate side wall 2114 is formed by depositing about m and selectively performing an etching process having strong anisotropy in the vertical direction so that the HTO film is left on the side of the gate electrode 2109. Further, as a P-type impurity ion, for example, BF
₂ ion implantation energy 40 KeV, implantation dose 3
After ion implantation of about × 15 cm ⁻² , a heat treatment process at 850 ° C. is performed to form a P-type high concentration diffusion layer 2115 in the N-type well 2102 and dope BF ₂ ions in the gate electrode 2109 to form a P-type impurity. Form a polysilicon gate electrode 2109. At this time, the A implanted into the P-type semiconductor substrate 2101
Since the implantation energy and implantation dose of s ions are high, the influence of BF ₂ ions is canceled.

According to the method of manufacturing a semiconductor device of this embodiment, a semiconductor device having a P-type polysilicon single gate can be easily manufactured.

(Twelfth Embodiment of Semiconductor Device Manufacturing Method) FIGS. 17A to 17G illustrate still another embodiment of a semiconductor device manufacturing method according to the present invention.

First, as shown in FIG. 17A, an element isolation film (LOCOS) 2203 is formed on one main surface of a P-type semiconductor substrate 2201.
Is formed, an N-type well 2202 is formed in a specific island region separated by the LOCOS 2203. After forming a gate oxide film (thickness: 8 nm) 2204 on a P-type semiconductor substrate 2201, an undoped polycrystalline silicon film (thickness: about 330 nm) 2205 is deposited on the gate oxide film 2204, and a photoresist 22
Using 06, a part of the undoped polycrystalline silicon film is thinly etched.

Next, as shown in FIG. 17B, a silicon nitride film 2207 is deposited on the entire upper surface of the semiconductor substrate 2201.

As shown in FIG. 17C, by etching back the silicon nitride film 2207 and the undoped polycrystalline silicon film, a gate electrode 2208 whose upper side is covered with the silicon nitride film 2207 is formed.

As shown in FIG. 17D, an L-type side wall oxide film 2209 is formed on the side surface of the gate electrode 2208 by thermal oxidation.

As shown in FIG. 17E, the oxide film grown on the substrate 2201 is etched thinly.

As shown in FIG. 17F, the well region 22
02 using an ion implantation mask selectively formed on
As N-type impurity ions, for example, As ions are implanted at an implantation energy of 40 KeV and an implantation dose of 6 × 10 ¹⁵ cm ^−2.
To the P-type semiconductor substrate 2201,
Form 10.

As shown in FIG. 17G, the gate sidewall 22
After the formation of 11, BF ₂ ions, for example, are implanted as P-type impurity ions at an energy of 40 K using an ion implantation mask selectively formed on the P-type semiconductor substrate 2201.
eV, implantation dose 4 × 10 ^{1 5} After cm ^-2 order of injection,
A heat treatment step at 850 ° C. is added. Thus, N-type well
A P-type high concentration diffusion layer 2212 is formed in 2202, and BF ₂ ions are doped in the gate electrode 2208 to form a P-type polysilicon gate electrode. By adjusting the thickness of the gate side wall 2211, the effective channel length of the NchMOSFET (distance between the high concentration source / drain diffusion layers 2210) and P
The effective channel length (the distance between the high concentration source / drain diffusion layers 2212) of the chMOSFET can be made substantially the same.

The semiconductor device thus formed,
The device characteristics and the CMOS circuit characteristics of a conventional semiconductor device (a semiconductor device manufactured by a conventional semiconductor device manufacturing method) were compared using a process / device / circuit simulation system.

The oxide film grown on the side surface of the gate electrode 2208 has the same thickness on both sides of the side surface of the gate electrode 2208. Therefore, the width of the gate side wall 2211 is 60 nm in the present invention and the re-oxidized film thickness is 0 nm, and the re-oxidized film thickness is 2 nm.
The thickness is set to 50 nm for 0 nm, 40 nm for a re-oxidized film thickness of 40 nm, and 30 nm for a re-oxidized film thickness of 30 nm.

FIGS. 18A and 18B show Nch
And the saturation current of the present example and the conventional example of the Pch MOSFET. The horizontal axis shows the re-oxidized film thickness, and the vertical axis shows the saturation current value per 1 μm gate width. As can be seen from FIG. 18A, in the NchMOSFET, the saturation current value does not depend on the re-oxidized film thickness in the present invention, whereas in the conventional example, the saturated current value decreases as the re-oxidized film thickness increases. . This is because, in the conventional example, the source / drain implantation position is shifted outward by the side wall oxide film formed on the side wall of the gate electrode to increase the effective channel length, whereas in the present invention, the side wall oxide film is not formed on the side wall of the gate electrode. It is.

FIGS. 19A and 19B show Nch
4 shows a comparison of the gate-drain capacitance of the present invention and the conventional example for each of the PchMOSFET and the PchMOSFET. The horizontal axis represents the re-oxidized film thickness, and the vertical axis represents the gate-drain capacitance per 1 μm gate width. The value when drain voltage / gate voltage = 0.0 / 1.5 V and the drain voltage / gate voltage = 1. 5 / 0.0V
The average of the values in the case of is shown. As can be seen from FIG. 19, the gate-drain capacitance is reduced in proportion to the re-oxidized film thickness in both the present invention and the conventional example.

FIGS. 20A and 20B show a comparison of the delay time between the present invention and the conventional example. The horizontal axis is the reoxidized film thickness,
The vertical axis indicates the delay time in a ring oscillator with a fan-in / out of 1. FIG. 20A shows a case where the wiring load capacitance is small, and FIG. 20B shows a case where the wiring load capacitance is large. As can be seen from FIG. 20A, the delay time decreases in proportion to the re-oxidized film thickness in both the present invention and the conventional example. However, in the conventional example, the improvement rate is 10% when the re-oxidized film thickness is 60 nm. On the other hand, in the present invention, it is as large as 20%. Further, as can be seen from FIG. 20B, when the wiring load capacitance is large, the delay time is reduced in the present invention by increasing the re-oxidized film thickness, but the delay time is increased in the conventional example.

(Thirteenth Embodiment of Semiconductor Device Manufacturing Method) Still another embodiment of a semiconductor device manufacturing method according to the present invention will be described with reference to FIGS. 21 (a) to 21 (f).

First, as shown in FIG. 21A, an element isolation film (LOCOS) 2303 is formed on one main surface of a P-type semiconductor substrate 2301.
Is formed, an N-type well 2302 is formed in a specific island region separated by the LOCOS 2303. After forming a gate oxide film (thickness: 7 nm) 2304 on a P-type semiconductor substrate 2301, an undoped polycrystalline silicon film (thickness: about 50 nm) 2305 and an amorphous silicon film (thickness: 280 nm) are formed on the gate oxide film 2304. ) Deposit 2306.

Next, as shown in FIG. 21B, a part of the amorphous silicon film 2306 and a part of the undoped polycrystalline silicon film 2305 are removed using a photoresist 2307.

After removing the photoresist 2307, a silicon nitride film is deposited to a thickness of about 10 nm as a film that does not easily pass oxidizing species. After that, gate oxide film 2304 and polycrystalline silicon film
The multilayer film including 23051203 and the silicon nitride film 1206 is etched by an etching step having strong anisotropy in the vertical direction. The etching is performed so that the silicon nitride film 2309 is left on the side surface of the gate electrode 2308 and the gate oxide film 2304 is exposed. Thus, as shown in FIG. 21C, the polycrystalline silicon film 2305a and the amorphous silicon film
2306a is formed.

As shown in FIG. 21D, an oxide film 1208 is grown on the side of the gate electrode 2308 where the silicon nitride film 2309 is not left, about 30 nm each from the gate end to the outside and inside, and a total of about 60 nm. The gate oxide film 2304 is oxidized in an oxygen atmosphere such that the end portion is thicker than the center portion of the gate oxide film 2304.

As shown in FIG. 21E, the well region 23
02 using an ion implantation mask selectively formed on
As N-type impurity ions, for example, As ions are implanted at an implantation energy of 40 KeV and an implantation dose of 6 × 10 ¹⁵ cm ^−2.
To the P-type semiconductor substrate 2301,
Form 10.

As shown in FIG. 21F, the gate side wall 23 is formed.
After the formation of 11, BF ₂ ions, for example, are implanted as P-type impurity ions at an energy of 30 K using an ion implantation mask selectively formed on the P-type semiconductor substrate 2301.
eV, implantation dose 4 × 10 ^{1 5} After cm ^-2 order of injection,
A heat treatment step at 850 ° C. is added. Thus, N-type well
A P-type high concentration diffusion layer 2312 is formed in 2302, and BF ₂ ions are doped in the gate electrode 2308 to form a P-type polysilicon gate electrode. By adjusting the thickness of the gate side wall 2311, the effective channel length of the NchMOSFET (the distance between the high concentration source / drain diffusion layers 2310) and P
The effective channel length (the distance between the high concentration source / drain diffusion layers 2312) of the chMOSFET can be made substantially the same.

The oxide film grown on the side surface of the gate electrode 2308 has the same thickness on both sides of the side surface of the gate electrode 2308. Therefore, the width of the gate side wall 2311 is 60 nm in the present invention and the re-oxidized film thickness is 0 nm, and the width of the re-oxidized film is 2 nm.
The thickness is set to 50 nm for 0 nm, 40 nm for a re-oxidized film thickness of 40 nm, and 30 nm for a re-oxidized film thickness of 30 nm.

Device characteristics and CMOS of a semiconductor device manufactured by the manufacturing method of this embodiment and a conventional semiconductor device (a semiconductor device manufactured by omitting the step of FIG. 21C in the manufacturing method of this embodiment). The comparison of the circuit characteristics was actually made and performed.

FIG. 22 shows NchMOSF actually measured.
7 shows a comparison between the transconductance of the present invention and the conventional example of ET. The horizontal axis indicates the re-oxidized film thickness, and the vertical axis indicates the transconductance per 1 mm gate width when the drain voltage and the gate voltage are 1.5V. As can be seen from FIG. 22, in the NchMOSFET, the transconductance value does not depend on the reoxidized film thickness in the present invention, whereas in the conventional example, the transconductance value is degraded as the reoxidized film thickness increases. This is because, in the conventional example, the source / source electrode is formed by a sidewall oxide film formed on the sidewall of the gate electrode.
Whereas the drain injection position shifts outward and the effective channel length increases, the gate oxide film at the source / drain junction becomes extremely thick and the parasitic resistance increases. On the other hand, in the present invention, the sidewall oxide film is formed on the side wall of the gate electrode. This is because they are not formed.

FIG. 23 shows NchMOSF actually measured.
A comparison between the gate-drain capacitance of the present invention and the conventional example of ET is shown. The horizontal axis represents the re-oxidized film thickness, the vertical axis represents the gate-drain capacitance per 1 μm gate width, and the drain voltage and the gate voltage are 0.0V. As can be seen from FIG. 23, the gate-drain capacitance is reduced in proportion to the re-oxidized film thickness in both the present invention and the conventional example.

FIGS. 24A and 24B show a comparison of the SIMS concentration profiles of boron and fluorine between the present invention and the conventional example. The horizontal axis is the PchMOS in the wafer section
The depth (unit: μm) of the FET in the gate depth direction is shown, and the vertical axis shows the concentrations of boron and fluorine. As can be seen from FIGS. 24A and 24B, in the conventional example, boron considerably seeps into the Si substrate, whereas in the present invention, a natural oxide film at the interface between amorphous silicon and polysilicon is used. For this reason, seepage of fluorine which promotes seepage of boron into the Si substrate can be suppressed, and seepage of boron into the Si substrate is scarcely observed.

FIG. 25 shows actually measured sub-threshold characteristics in the present invention. The horizontal axis is the gate voltage,
The vertical axis indicates the drain current per 1 μm gate width. The drain voltage of the NchMOSFET is 0.1 V and 1.5 V, respectively, and the drain voltage of the PchMOSFET is -0.1 V and -1.5 V, respectively. FIG.
As can be seen from the drawings, the present invention shows very good sub-threshold characteristics for both Nch and Pch, and its sub-threshold coefficient is 78 mV / de for Pch.
c, a very small value of 83 mV / dec for Nch, and a low threshold voltage of 0.45 V for Nch and 0.30 V for Pch could be set. Also, from the two points that the actually measured threshold voltage almost coincided with the value obtained by the simulation and that no shift of the flat band was observed by the CV measurement, it was concluded that boron bleeding hardly occurred. You.

FIG. 26 shows a comparison between the actually measured delay times of the present invention and the conventional example. The horizontal axis indicates the re-oxidized film thickness, and the vertical axis indicates the delay time in the ring oscillator having the fan-in / out of 1. As can be seen from FIG. 26, in the conventional example, when the re-oxidized film thickness is 20 nm, the minimum delay time is 10
In contrast to 6 ps / stage, in the present invention, when the re-oxidized film thickness is 40 nm, the minimum delay time is 93 ps / stage.
Take stage.

[0170]

According to the semiconductor device of the present invention, the following effects can be obtained.

(1) The junction depth D1 of the high-concentration source / drain diffusion layer below the L-type gate sidewall oxide film is equal to the junction depth D2 of the high-concentration source / drain diffusion layer other than the bottom of the L-type sidewall.
Since it is formed shallower, the spread of the potential from the source / drain diffusion layers in the channel direction is effectively suppressed, and a decrease in Vt peculiar to the fine MOSFET is effectively suppressed.

(2) Since the high concentration source / drain diffusion layers are diffused under the thick gate oxide film at both ends of the gate oxide film, the gate-drain capacitance and the gate-source capacitance can be reduced without reducing the drain current. Can be reduced.

(3) Since the gate electrode is composed of two layers of polycrystalline silicon and amorphous silicon, the penetration of B from the P-type polysilicon into the bulk, which is a problem in the dual gate technology, is effectively prevented. .

(4) By employing a T-type gate structure in a MOSFET having an SOI structure, the capacitance between the gate and the drain can be reduced, so that the effect of improving the delay time is very large.

According to the method of manufacturing a semiconductor device of the present invention, (1) an increase in driving force due to prevention of a reduction in the effective channel length (2) suppression of a short channel effect by an L-type side wall structure (3) a problem with the dual gate technology (4) Effective production of T-type gate structure by forming gate bird's beak using dry oxidation and wet oxidation (5) Oxidation of substrate surface (6) The gate length is longer than the mask dimension and the oxide film thickness at the enlarged gate is thicker by preventing the film growth, thereby reducing the oxide film capacitance. Gate resistance can be reduced without increasing (7) Difference in dose type between high concentration diffusion layer and polysilicon gate electrode (8) P-type single polysilicon It can be easily manufactured in a self-aligned manner by using the current LSI technology a semiconductor device can be expected effects such as over gate electrode.

[Brief description of the drawings]

FIG. 1 is a structural sectional view showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a structural sectional view showing a second embodiment of the semiconductor device of the present invention.

FIG. 3 is a structural sectional view showing a third embodiment of the semiconductor device of the present invention.

FIGS. 4A to 4G are cross-sectional views illustrating a first embodiment of a method of manufacturing a semiconductor device according to the present invention; FIGS.

5 (a) and 5 (b) show Nch of the present invention and a conventional example.
Diagram showing comparison of MOSFET profiles

FIG. 6 is a diagram showing a comparison of sub-threshold characteristics between the present invention and a conventional example.

FIGS. 7A to 7G are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention; FIGS.

FIGS. 8A to 8G are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a third embodiment of the present invention; FIGS.

FIGS. 9A to 9D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a fourth embodiment of the present invention; FIGS.

FIGS. 10A to 10E are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a fifth embodiment of the present invention.

FIGS. 11A to 11D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a sixth embodiment of the present invention. FIGS.

FIGS. 12A to 12E are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a seventh embodiment of the present invention.

13 (a) to 13 (d) are cross-sectional views showing a manufacturing process of an eighth embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIGS. 14A to 14F are cross-sectional views illustrating a ninth embodiment of a method of manufacturing a semiconductor device according to the present invention; FIGS.

FIGS. 15A to 15F are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a tenth embodiment of the present invention.

FIGS. 16A to 16F are cross-sectional views showing a manufacturing process of an eleventh embodiment of the method for manufacturing a semiconductor device according to the present invention; FIGS.

FIGS. 17A to 17G are cross-sectional views showing a manufacturing process of a twelfth embodiment of the method of manufacturing a semiconductor device according to the present invention; FIGS.

FIGS. 18 (a) and (b) are diagrams showing a comparison of the saturation current between the present invention and the conventional example.

FIGS. 19A and 19B are diagrams showing a comparison between the gate-drain capacitance of the present invention and a conventional example.

FIG. 20 is a diagram showing a comparison of delay times between the present invention and a conventional example.

FIGS. 21A to 21F are cross-sectional views showing a manufacturing process in a thirteenth embodiment of the method for manufacturing a semiconductor device according to the present invention; FIGS.

FIG. 22 is a diagram showing transconductance capacitances of the present invention and a conventional example.

FIG. 23 is a diagram showing a comparison between the gate-drain capacitance of the present invention and a conventional example.

FIGS. 24A and 24B are diagrams showing boron and fluorine concentration profiles of the present invention and a conventional example.

FIG. 25 is a diagram showing a sub-threshold characteristic of the present invention.

FIG. 26 is a diagram showing a comparison of delay times between the present invention and a conventional example.

[Explanation of symbols]

11 P-type semiconductor substrate 21 P-type semiconductor substrate 31 P-type semiconductor substrate 1101 P-type semiconductor substrate 1401 P-type semiconductor substrate 1501 P-type semiconductor substrate 1601 P-type semiconductor substrate 1701 P-type semiconductor substrate 1801 P-type semiconductor substrate 2001 P-type semiconductor substrate 2101 P-type semiconductor substrate 12 Gate oxide film 22 Gate oxide film 32 Gate oxide film 1102 Gate oxide film 1202 Gate oxide film 1302 Gate oxide film 1402 Gate oxide film 1502 Gate oxide film 1702 Gate oxide film 1802 Gate oxide film 1902 Gate oxide film 2005 Gate oxide film 2105 Gate oxide film 13,23,33,1106 Gate electrode 1207,1308,1403,1503,1605,1703,1806,1907,20
06, 2109 Gate electrode 14, 1107, 1208, 1309, 1807, 2008, 2110 L-type sidewall oxide film 15, 24, 34 N-type high concentration diffusion layer 1108, 1405, 1505, 1607, 1707, 1808, 2011, 2113 N
Type high concentration diffusion layer 1908, 2012, 2114 Gate side wall 2002, 2102 N type well 2003, 2103 LOCOS 1404, 1606 Side wall oxide film 1104 Photo resist 1205 Photo resist 1306 Photo resist 1604 Photo resist 1805 Photo resist 1906 Photo resist 2010 Photo resist 2112 Photoresist 1209, 1310, 1909, 2013, 2115 P type high concentration diffusion layer 1103, 1203, 1303, 1804, 2107 Undoped polysilicon 1105, 1206, 1307, 1504, 1705, 1904 Silicon nitride film 1201, 1301, 1901 N type Semiconductor substrate 1204, 1305 Amorphous silicon 1304 Natural oxide film 1602 Gate oxide film 1603 Polysilicon 1704, 1803, 1903 N-type doped polysilicon 1706 Oxide film 1905 TiN 1910 CoSi ₂ 2004a, 2004b Buried channel layer / threshold voltage control layer 2104a , 2104b Buried channel layer / threshold voltage control layer 2007, 2108 HTO 2009a, 2009b Pocket pan Through stopper / P-type low concentration diffusion layers 2111a, 2111b pocket punch-through stopper / P-type low concentration diffusion layer 2106 P-type doped polysilicon

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Hiroyuki Umimoto 1006 Kazuma Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-7-38092 (JP, A) JP-A-61 −112379 (JP, A)

Claims (23)

(57) [Claims] A semiconductor substrate; a gate insulating film formed on a selected region of one main surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; A source / drain region formed from a high-concentration impurity diffusion layer, wherein both end portions of the gate insulating film are thicker than a central portion of the gate insulating film; A first portion located below the both ends of the gate insulating film, and a second portion having a thickness equal to or greater than the thickness of the first portion, the tip of the first portion being the gate The first portion extends in the direction of the insulating film, is located below the gate electrode and inside the thick portions at both ends of the gate insulating film, and has an impurity concentration of 1 × 10 ¹⁹ cm. from ^-3 1 × 10 ²⁰ range cm ^-3
The semiconductor device inside . 2. The semiconductor device according to claim 1 , further comprising an L-shaped side wall formed on a side surface of the gate electrode, wherein the first portion of the source / drain region extends below the L-shaped side wall. 3. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein a film thickness at a bottom portion of said L-shaped side wall is larger than a film thickness at a side portion. Wherein said gate electrode is formed from the stacked structure including the amorphous silicon film and a polycrystalline silicon film, a semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein the semiconductor substrate is an SOI substrate.
The semiconductor device according to claim 1. 6. A step of forming a gate insulating film on a semiconductor substrate; and a step of forming a gate electrode on the gate insulating film, the upper side of which is selectively covered with an insulating film that is hardly permeable to oxidizing species. Growing a thermal oxide film on an exposed portion of the side surface of the gate electrode;
An oxidation step of making an end of the gate insulating film thicker than a central portion of the gate insulating film; a first portion located below the both ends of the gate insulating film;
A second portion having a thickness equal to or greater than the thickness of the first portion, and the impurity concentration of the first portion is 1 × 10 ¹⁹
forming a source / drain region in the semiconductor substrate within the range of cm ⁻³ to 1 × 10 ²⁰ cm ^{−3 in} the semiconductor substrate. 7. The step of forming the gate electrode includes the steps of: depositing a conductive film on the gate insulating film; and forming a photoresist defining the position and shape of the gate electrode on the conductive film. A step of selectively removing exposed portions of the conductive film using the photoresist as a mask by etching having strong anisotropy in a vertical direction; a step of removing the photoresist; Depositing an insulating film that is difficult to pass through, and etching back the insulating film and the conductive film by etching having strong anisotropy in the vertical direction, whereby a part of the insulating film is formed on the side surface of the gate electrode. The method of manufacturing a semiconductor device according to claim 6 , further comprising: 8. Depositing the conductive film includes a step of depositing a polycrystalline silicon film on the gate insulating layer, depositing an amorphous silicon film on the polycrystalline silicon film, including The method for manufacturing a semiconductor device according to claim 7 , wherein 9. The method of manufacturing a semiconductor device according to claim 6 , wherein the step of selectively removing an exposed portion of the conductive film includes a step of removing a part of the amorphous silicon film and a part of the polycrystalline silicon film. Method. 10. A step of depositing the conductive film, the first
Depositing a conductive layer on the gate insulating film, forming an oxide film on the first conductive layer, and depositing a second conductive layer on the oxide film. Claims
8. The method for manufacturing a semiconductor device according to item 7 . Wherein said second conductive layer is formed of amorphous silicon, a method of manufacturing a semiconductor device according to claim 10. 12. A step of depositing the conductive film, the first
Depositing a conductive layer on the gate insulating film, forming a second conductive layer doped with impurities on the first conductive layer, and forming a third conductive layer on the second conductive layer. The method of manufacturing a semiconductor device according to claim 7 , further comprising: depositing on a layer. 13. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, an exposed portion on the semiconductor substrate, and a side surface of the gate electrode. Removing the oxide film by isotropic etching; forming a silicon nitride film on the surface exposed by removing the oxide film; and making an end portion of the gate insulating film thicker than a central portion of the gate insulating film. An oxidation step; a first portion located below the both ends of the gate insulating film;
A second portion having a thickness equal to or greater than the thickness of the first portion, and the impurity concentration of the first portion is 1 × 10 ¹⁹
forming a source / drain region in the semiconductor substrate within the range of cm ⁻³ to 1 × 10 ²⁰ cm ^{−3 in} the semiconductor substrate. 14. step of forming the silicon nitride film, after injecting nitrogen ions obliquely with respect to the normal of the main surface of said semiconductor substrate, comprising the step of annealing in a nitrogen atmosphere, claim 13 The production method described in 1. 15. A step of forming a gate insulating film having a three-layer structure of a silicon oxide film, a silicon nitride film and a silicon oxide film on a semiconductor substrate, and forming at least one of the gate insulating films formed on the semiconductor substrate. A step of forming a gate electrode on the gate insulating film without removing the silicon nitride film; an oxidizing step of making an end portion of the gate insulating film thicker than a central portion of the gate insulating film; A first portion located below said opposite ends of
A second portion having a thickness equal to or greater than the thickness of the first portion, and the impurity concentration of the first portion is 1 × 10 ¹⁹
forming a source / drain region in the semiconductor substrate within the range of cm ⁻³ to 1 × 10 ²⁰ cm ^{−3 in} the semiconductor substrate. 16. A step of forming a gate insulating film composed of three layers of a silicon oxide film, a silicon nitride film and a silicon oxide film on a semiconductor substrate; a step of depositing a conductive film on the gate insulating film; Patterning a photoresist at a predetermined position to be a gate electrode on the conductive film; and selectively using the photoresist as a mask to selectively form a multilayer film including the gate insulating film and the conductive film in a vertical direction. Etching the gate insulating film until the gate insulating film is exposed by anisotropic etching, oxidizing in an oxygen atmosphere, and a first portion located under the both ends of the gate insulating film;
A second portion having a thickness equal to or greater than the thickness of the first portion, and the impurity concentration of the first portion is 1 × 10 ¹⁹
forming a source / drain region in the semiconductor substrate within the range of cm ⁻³ to 1 × 10 ²⁰ cm ^{−3 in} the semiconductor substrate. 17. A step of forming a gate insulating film on a semiconductor substrate; a step of forming a gate electrode on the gate insulating film; an L-type conductive film on a side surface of the gate electrode; Forming an insulating film provided in the concave portion of the conductive film through which oxidizing species are not easily passed; oxidizing a portion of the side surface of the L-type conductive film which is not covered with the insulating film; An oxidation step of making an end of the film thicker than a central part of the gate insulating film; a first portion located below the both ends of the gate insulating film;
A second portion having a thickness equal to or greater than the thickness of the first portion, and the impurity concentration of the first portion is 1 × 10 ¹⁹
forming a source / drain region in the semiconductor substrate within the range of cm ⁻³ to 1 × 10 ²⁰ cm ^{−3 in} the semiconductor substrate. 18. The method according to claim 18, wherein the step of forming the gate electrode comprises : depositing a first conductive film not doped with an impurity on the gate insulating film; and forming the gate electrode on the first conductive film. Forming a photoresist that defines the position and shape of the first conductive film, and selectively removing the exposed portion of the first conductive film by using the photoresist as a mask and etching with strong anisotropy in the vertical direction. Forming the L-type conductive film and the insulating film that is difficult to pass through the oxidizing species, wherein the gate electrode and the semiconductor substrate are doped with an impurity having a predetermined conductivity type. Depositing an insulating film, which is hardly permeable to oxidizing species, on the second conductive film; and etching with strong anisotropy in the vertical direction to form the oxidizing species. Through Etching back the insulating film and the second conductive film, and leaving a part of the L-type conductive film and the insulating film that is difficult to pass through the oxidizing species on the side surface of the gate electrode. The method for manufacturing a semiconductor device according to claim 17 , wherein 19. A step of forming a gate insulating film on a semiconductor substrate, and forming a first doped ion on the gate insulating film.
Forming a gate electrode composed of a multilayer film composed of a conductive film of a second type and a second conductive film not doped with ions; and a side of the first conductive film on a side portion of the gate electrode. Forming an L-type side wall oxide film such that an oxide film growing in a portion is thicker than an oxide film growing on a side portion of the second conductive film; An oxidizing step that is thicker than a central portion; and a high-concentration diffusion layer having a predetermined conductivity type included in the source / drain region and a shallow junction under the L-type sidewall in the source / drain region on the substrate. Forming another high-concentration diffusion layer having the predetermined conductivity type. 20. A step of forming a gate insulating film on a semiconductor substrate, comprising a first conductive film doped with an impurity having a predetermined conductivity type as a lower layer, and a second impurity-doped second film. Forming a gate electrode having a conductive film as an upper layer on the gate insulating film; and thermally oxidizing the gate electrode on a side surface of the first conductive film and a side surface of the second conductive film of the gate electrode. An oxidation step of forming an L-type side wall oxide film and further making an end of the gate insulating film thicker than a central part of the gate insulating film; And a second portion having a thickness equal to or greater than the thickness of the first portion, wherein the first portion has an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ to 1 ×. The range of 10 ²⁰ cm ^-3
Forming a source / drain region in an enclosure in the semiconductor substrate. 21. A step of forming a gate insulating film on a first semiconductor substrate, a first conductive film doped with ions of a first conductivity type and a second conductive film not doped with ions. Depositing a third conductive film on the second conductive film, depositing a third conductive film on the second conductive film, forming the second conductive film on the gate insulating film, the first conductive film, and the second conductive film. Forming a photoresist that defines the position and shape of the gate electrode on a multilayer film composed of the conductive film and the third conductive film, and selectively vertically using the photoresist as a mask. Etching the multilayer film by strong anisotropic etching until the gate insulating film is exposed; and depositing an insulating film on the first semiconductor substrate and the gate electrode; Insulation by etching with anisotropy Remaining on the side wall of the gate electrode; and an oxide film growing on the side of the first conductive film on the side of the gate electrode and growing on the side of the second conductive film. An oxidation step of making the gate insulating film thicker and an end portion of the gate insulating film thicker than a central portion of the gate insulating film;
Forming a second conductive type high concentration diffusion layer in the drain region, selectively exposing the source / drain region of the first semiconductor substrate by etching having strong anisotropy in a vertical direction; A step of silicidizing the source / drain region of the first semiconductor substrate; a step of selectively etching the third conductive film; and a step of ion-implanting ions of the second conductivity type into the gate electrode. Doping a semiconductor device. 22. A step of forming an element isolation region on one main surface of a second semiconductor substrate having a predetermined conductivity type, and forming a first conductivity type well in a specific island region separated by the element isolation region. And forming a gate insulating film on the second semiconductor substrate and on the first conductivity type well region. The method further comprises: ion-implanting a source on the first semiconductor substrate. Instead of the step of forming the second conductive type high concentration diffusion layer in the / drain region, the first ion implantation mask selectively formed on the first conductive type well region is used as a mask to perform ion implantation. Forming a first conductive type high concentration diffusion layer in source / drain regions on the second semiconductor substrate; and forming a second ion implantation mask selectively formed on the second semiconductor substrate. The first conductivity type well region is used as a mask. Comprising forming a high concentration diffusion layer of the second conductivity type source / drain regions of the above, a method of manufacturing a semiconductor device according to claim 21. 23. A step of forming an element isolation region on one main surface of a semiconductor substrate of a first conductivity type; a step of forming a second conductivity type well in a specific island region separated by the element isolation region; Forming a buried channel layer of the second conductivity type near the surface of the substrate by implantation, and forming a threshold voltage control layer of the second conductivity type near the surface of the well region; Forming a gate insulating film over the region, and forming a first conductive film doped with ions of the first conductivity type and a second conductive film not doped with ions on the gate insulating film. Depositing a first insulating film on the second conductive film; forming the gate insulating film, the first conductive film, the second conductive film, and the first Photo-resist in a predetermined position to be the gate electrode of a multilayer film consisting of an insulating film Patterning, and using the photoresist as a mask, selectively vertically align the multilayer film including the gate insulating film, the first conductive film, the second conductive film, and the first insulating film. Etching by a strong anisotropic etching in the direction until the gate insulating film is exposed; and forming an oxide film on the side of the first conductive film on the side of the gate electrode by the second conductive film. An oxidation step in which the oxide film grows thicker than the oxide film grown on the side of the film, and an edge of the gate insulating film becomes thicker than a central portion of the gate insulating film; and ions formed selectively on the well region Forming a second conductive type high concentration diffusion layer in the source / drain region on the substrate by ion implantation using the implantation mask as a mask; and selectively etching the first insulating film; The semiconductor substrate, the well And a step of depositing a second insulating film on the gate electrode;
Forming a first conductive type high-concentration diffusion layer in the source / drain region on the well region by ion implantation, and simultaneously forming a first conductive film on the gate electrode by ion implantation. A method of manufacturing a semiconductor device, comprising: doping conductive type ions.