JPS61242469A - Density correcting circuit - Google Patents

Abstract

PURPOSE:To set widely a correction range, and also to set finely each correction level by processing an amplification factor for amplifying an image signal to a reference level at every digit of a decimal number in accordance with an inputted image density correction command signal. CONSTITUTION:Data which have been outputted to a memory output bus 30 from memories 3a-3c are converted to analog signals by D/A converters 4a-4c, respectively. These analog signals are attenuated in accordance with each digit (1/1, 1/10, and 1/100) of decimal number by attenuators 7a-7c, respectively, and thereafter, added by an adder 8. That is to say, an output of the adder 8 becomes 2.58, and by multiplying this signal and a converted signal analog input (image signal) by a multiplier 5, an image density is corrected. Also, by forming the memory, the D/A converter and the attenuator to three stages, 1,000 kinds of correction ranks can be set. In this way, since the amplification factor is processed by a BCD code, the correction range can be set widely, and also each correction level can be set finely.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a density correction circuit for an input signal of an image scanner.

BACKGROUND OF THE INVENTION Conventionally, this type of circuit has been used for numeric keypad 1, as shown in FIG.
When you specify the white density light and black density medium) of the original, the CPU
2 is based on this specified combination of white density and black density,
The correction coefficient is output with reference to the ROM 3 in which the degree of amplification necessary to amplify the image signal to the reference level is written in advance.

This circuit then converts the output of the ROMa into an analog signal by the D/A converter 4, and the multiplier 5 multiplies this analog signal by the analog converted input, ie the input signal of the image scanner, thus converting the converted input into an analog signal. was configured to perform level conversion.

Note that in the above circuit, the multiplier 6 may directly multiply the digital output signal of the ROM 3 and the analog converted input without using the D/A converter 4.

Problems to be Solved by the Invention However, this density correction circuit has the disadvantage that the number of density correction levels that can be specified is limited by the number of bits of the pass line 6 of the system, and proper density correction cannot be performed. Specifically, if the system bus is 8 bits, only 256 levels can be specified, and since bias adjustment is actually performed in addition to density correction, the number of density correction levels is even smaller.

If the pass line is 8 bits, the input of D/A converter 4 is in the range from "O" to "256', so other ranges (for example, 32.9 or 2.66) cannot be specified. In this case, it is possible to adjust the number of bits that can be specified by the CPU 2 and ROM 3 by placing an attenuator or the like after the D/A converter 4, but if the specified number is not divisible, Accuracy cannot be improved unless rounding up is performed.

To solve this problem, increase the number of bits of the pass line,
Or, set the white density and black density correction range narrowly,
This problem can be solved by roughly defining the range of each correction level. However, in the former case, the device is expensive, and in the latter case, it is not practical because the circuit purpose is to widen the correction range and set each correction level range finely.

An object of the present invention is to solve the above-mentioned conventional problems by making it possible to set a wide correction range for white density and black density without increasing the number of pass line bits, and to set each correction level finely. An object of the present invention is to provide a density correction circuit that can perform the following steps.

Means for Solving the Problems In order to solve the above problems, the present invention sets an amplification rate for amplifying an image signal to a reference level for each digit of a decimal number in accordance with an input image density correction command signal. It is characterized by processing.

Since the present invention processes the amplification rate using the BCD code, the correction range can be widened and each correction level can be set finely.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a density correction circuit according to an embodiment of the present invention, and blocks having the same configuration as those in FIG. 2 are given the same reference numerals.

The circuit shown in Figure 1 consists of a numeric keypad 1 for specifying white density (c) and black density (middle) to correct the density of the original, and a CPU 2 that controls the entire circuit based on signals from the numeric keypad 1.
and memories 3a, 3b, and 3c.

Memories 3a, 3b, and 3c are memories for each 3-digit decimal number, and are used to amplify the image signal to the reference level depending on the combination of white density and black density input using the numeric keypad 1. The necessary amplification degree is written in advance for each digit.

This circuit further includes D/A converters 4a, 4b, 4 which convert signals from the memos 1J3a, 3b, 3c for each of the three decimal digits from digital signals to analog signals.
an attenuator 7a that outputs an amplification factor corresponding to each digit, such as c and 1 times, - times, and - times.

7b, 7C, an adder 8, and a multiplier 5.

To explain the operation of the above embodiment, first, in order to correct the document density, the operator operates the numeric keypad 1 to adjust the white density and black density (for example, W = 0.52, B = 1.36). input.

The CPU 2 runs a program that calculates a shim matrix based on the values of W and B input using the numeric keypad 1, and outputs address signals for each of the memories 3a, 3b, and 3c to the CPU bus 2o. Memory 3a.

3b and 3c, in response to the value entered with the numeric keypad 1, memory 3a is "2", memo IJ3b is "5", memory 3
c outputs a value of '8''.

The data output from the memories 3a, 3b, 3a to the memory output bus 30 is transferred to the D/A converters 4a, 4b, respectively.
, 40 into a digital analog signal. These analog signals are respectively attenuated by attenuators 7a and 7b.

7c, each digit of the decimal number (1/1, 1/10.1/1
oo) and then added by the adder 5. In other words, the output of the adder 8 is 2.58, and this signal and the analog input signal to be converted (image signal) are added to the multiplier 5.
The image density is corrected by multiplying by .

In the configuration of the above embodiment, 1000 correction ranks can be set by providing three stages of memory, D/A converter, and attenuator. Furthermore, if the number of stages of circuits below the memory is increased, even more correction ranks can be set.

In the above embodiment, the attenuation factors (
1/1.1/1o, 1/10o), but in this case, the number of significant digits differs depending on whether the conversion level is large (for example, 1.00) or small (for example, 0.01). In order to specify 01 to 0.010 or 0.0100, additional hardware must be installed. In this case, the amount of attenuation of the attenuators 7a, 7b, and 7c is changed in accordance with the value of the conversion level. in particular,
The information of the attenuator 7C is written in advance in the least significant bit of the least significant digit and its upper bit, or the information is configured to be outputted in advance to the output of the CPU 2 or the output of the memory 3c.

In other words, if you want the attenuation amount to be 1.00, for example, the attenuation rate of each stage should be 1/1.1 /10.1 /10
0, and the other 0.01, 1 /100.1 /
1000.

Make it 1/10000.

Further, in the embodiment, the D/A converters 7a and 7b
.

7C conversion error may have an effect. In particular, when inputting '1'', the conversion error is usually 1/2 LSB (Leas
t51gn1ficant bit; that is, the bit with the least weight among multiple bits), so the output may be 0.5 or 1.5.
This error cannot be ignored. In this case, the set values (0°1.2...
Write the value obtained by multiplying 9) by the largest possible number. This correction is then performed by an adder 8. When writing to the memories 3a, 3b, and 3cK, if the pass line is 8 bits, write as follows.

Specified decimal number , , ・2.1.0 Memory output (D/A input) FC, Eo, ・-38, 1c
. As shown by the dotted line in FIG.
This can be done either by inputting a value into the multiplier 1 and setting the magnification of the multiplier 1 to "1", or by not using the multiplier 6.

DETAILED DESCRIPTION OF THE INVENTION As described above, since the present invention processes the amplification rate using a BCD code, it is possible to set a wide correction range and to set each correction level finely.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a density correction circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 1...Numeric keypad, 2...-CPU, 3a, 3b
, 3c...Memory, 4a, 4b, 4c...
・D/A converter, 6... Multiplier, 7a, 7b, 7
c: Attenuator, 8: Adder. Name of agent: Patent attorney Toshio Nakao and 1 other person
2t! 1

Claims (1)

[Claims] A plurality of memories each store an amplification rate for amplifying an image signal to a reference level in accordance with an input image density correction command signal for each decimal digit, and the output signals of the plurality of memories are each converted into an analog signal. A plurality of D/A converters for converting the outputs of the plurality of D/A converters into signals of the corresponding digit, and a plurality of attenuators for converting the outputs of the plurality of D/A converters into signals of the corresponding digits, and the outputs of the plurality of attenuators are added together. and an adder for converting the amplification factor into the amplification factor.