JPS61242175A - Comb-line filter - Google Patents

Comb-line filter

Info

Publication number
JPS61242175A
JPS61242175A JP60083513A JP8351385A JPS61242175A JP S61242175 A JPS61242175 A JP S61242175A JP 60083513 A JP60083513 A JP 60083513A JP 8351385 A JP8351385 A JP 8351385A JP S61242175 A JPS61242175 A JP S61242175A
Authority
JP
Japan
Prior art keywords
signal
circuit
output
input
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60083513A
Other languages
Japanese (ja)
Inventor
Sumio Kato
純雄 加藤
Shoichi Sugihara
杉原 正一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60083513A priority Critical patent/JPS61242175A/en
Priority to US06/852,207 priority patent/US4684976A/en
Priority to GB8609529A priority patent/GB2175166B/en
Publication of JPS61242175A publication Critical patent/JPS61242175A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the need for signal capacity normalization circuits and to vary easily the coefficients of a coefficient multiplier by obtaining a circulating delay signal input from the output of the coefficient multiplier. CONSTITUTION:If the signal of a video signal input terminal 1 is Vi; the input signal of the coefficient multiplier 5 is V1; the output signal of its coefficient multiplier 5 is V2; the output of a signal output terminal 9 is V0; the feedback coefficient of the coefficient multiplier 5 is K; the transfer function of 1H delay circuit 3 is G, two equations are established as follows; V0=V1-V2=(1-K)V1, V1=Vi+GV2=Vi+KGV1. If V1 is eliminated from the above equation, the relation of the equation 1 is established between an input and output. Equation 2 shows a comb-line filter which has a venter at the integer magnification portion of a horizontal frequency. At this time, the signal level of the venter is 1 irrespective of the value of K.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明はくし形フィルタに関し、とくに映像信号のS
/N改善等に用いられる循環型くし形フィルタの構成に
関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a comb filter, and in particular, the present invention relates to a comb filter.
The present invention relates to the configuration of a circulating comb filter used for /N improvement, etc.

工従来の技術] 第2図は、昭和43年4月NHK技研月報rくし形フィ
ルタによる映像信号のプロセスと画質」に記載された循
環型くし形フィルタを示している0図において、(1)
は映像信号入力端子、(2)は演算回路、(3)はl水
平時間遅延回路(以下。
(1)
is a video signal input terminal, (2) is an arithmetic circuit, and (3) is a horizontal time delay circuit (hereinafter referred to as a horizontal time delay circuit).

rlH遅延回路」と称する) 、 (4)は加算回路。(rlH delay circuit), (4) is an adder circuit.

(5)は系数器、(6)は信号出力端子、(7)は信号
量正規化回路である。
(5) is a multiplier, (6) is a signal output terminal, and (7) is a signal amount normalization circuit.

つぎに、第2図におけるS/N改善動作について説明す
る。いま、映像信号入力端子(1)の信号をVi、IH
遅延回路(3)の入力信号をvh、信号出力端子(6)
の信号をVOとし、系数器(5)の帰還系数をに、IH
遅延回g (3)の伝達関数をGとすれば、次式が成立
する。
Next, the S/N improvement operation in FIG. 2 will be explained. Now, the signal of the video signal input terminal (1) is connected to Vi, IH.
input signal of delay circuit (3) to vh, signal output terminal (6)
Let the signal of
If the transfer function of delay circuit g (3) is G, then the following equation holds true.

V h x V i + K V o    ・・・■
Vo−Vi+GVh    =・@ ■、■式からvhを消去すると、出力信号V。
V h x Vi + K Vo...■
Vo-Vi+GVh =・@ ■, ■ When vh is deleted from the equation, the output signal V is obtained.

と入力信号Vlの関係は■式となる。The relationship between the input signal Vl and the input signal Vl is expressed by the formula (2).

であり、IHil!!延回路(3)の伝達関数Gは、ラ
イン相関の大きいテレビ信号を扱う場合、τh−1/f
h  (fhはライン周波数)とすればよく。
And IHil! ! The transfer function G of the spreading circuit (3) is τh-1/f when dealing with a television signal with a large line correlation.
h (fh is the line frequency).

G=e”” =cos ωτh −Js+n ωτbと
表わされる。したがって、■式の伝達関数は、■式のよ
うに表わすことができる。
It is expressed as G=e""=cos ωτh −Js+n ωτb. Therefore, the transfer function of equation (2) can be expressed as equation (2).

・・・■ nを正の整数とすると、■式は、f m n * fh
のは、第2図のフィルタが水平周波数の整数倍の所に腹
部がでさるくし形フィルタであり、帰還率Kを変えるこ
とにより、フィルタの振幅周波数特性の尖鋭さが変わる
ためにS/N改善度が自由に設定できることを表わして
いる。
...■ If n is a positive integer, then the formula is f m n * fh
The reason for this is that the filter in Figure 2 is a comb-shaped filter that has a belly at an integer multiple of the horizontal frequency, and changing the feedback rate K changes the sharpness of the amplitude-frequency characteristic of the filter, so the S/N ratio increases. This indicates that the degree of improvement can be set freely.

また、信号量正規化回路(7)は出力信号がKの関数と
なるため、信号を(1−K)倍してやり、Kの変化によ
り出力娠輻変化が発生しないように411成されている
Further, since the output signal of the signal amount normalization circuit (7) is a function of K, the signal is multiplied by (1-K) to prevent output convergence changes from occurring due to changes in K.

[発明が解決しようとする問題点] 上記従来の回路においては、S/N改善度を変化させる
ために、系数器(5)の系aKを変化させると、信号量
正規化回路(7)の乗数もKに比例させて変化させなけ
ればならず1両回路の整合性を得るのが難かしく、実質
的にKを可変することは困難であった。
[Problems to be Solved by the Invention] In the conventional circuit described above, when the system aK of the multiplier (5) is changed in order to change the S/N improvement degree, the signal amount normalization circuit (7) changes. The multiplier must also be changed in proportion to K, making it difficult to obtain consistency between both circuits, and it has been difficult to substantially vary K.

この発明は上記のような問題点を解消するためになされ
たもので、系数器の系数を容易に変化することのできる
くし形フィルタ回路を提供することを目的としている。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a comb filter circuit that can easily change the coefficient of the coefficient.

[問題点を解決するための手段] この発明によるくし形フィルタは、循環遅延信号入力を
系数器の出力から得ることにより、信号量正規化回路を
不要とした。
[Means for Solving the Problems] The comb filter according to the present invention eliminates the need for a signal amount normalization circuit by obtaining the cyclically delayed signal input from the output of the multiplier.

[作用〕 この発明においては、信号量正規化回路が不要となるた
め、系数器の系数のみを変化させることで、希望のS/
N改善度が信号量変、化を伴なうことなく容易に得られ
る。
[Operation] This invention eliminates the need for a signal amount normalization circuit, so by changing only the coefficient of the coefficient generator, the desired S/
N improvement degree can be easily obtained without any change in signal amount.

[実施例] 以下、この発明の実施例を図面にしたがって説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.

第1図において、第2図と同一符号は同一部分を示し、
(1)は映像信号入力端子、(2)は演算回路、(3)
はIH1i延回路、i5)は系数器、(8)は減算回路
、(S)は信号出力端子である。
In FIG. 1, the same symbols as in FIG. 2 indicate the same parts,
(1) is a video signal input terminal, (2) is an arithmetic circuit, (3)
is an IH1i extension circuit, i5) is a multiplier, (8) is a subtraction circuit, and (S) is a signal output terminal.

映像信号入力端子(1)゛は演算回路(2)の一方の入
力へ接続され、演算回路(2)の出力は系数器(5)へ
入力されるとともに減算回路(8)の被減算入力端子に
も入力される。系数器(5)の出力は減算回路(8)の
減算入力端子に入力されるとともに1)I遅延回路(3
)へ入力される。また、IH遅延回路(3)の出力は演
算回路(2)の他方の入力に接続される。さらに、減算
回路(8)の出力は信号出力端子(9)に接続されてい
る。なお、演算回路(2)は、2入力を加算する加算回
路で構成されている。
The video signal input terminal (1) is connected to one input of the arithmetic circuit (2), and the output of the arithmetic circuit (2) is input to the multiplier (5) and also serves as the subtracted input terminal of the subtraction circuit (8). is also entered. The output of the multiplier (5) is input to the subtraction input terminal of the subtraction circuit (8), and is also input to the subtraction input terminal of the subtraction circuit (8).
). Further, the output of the IH delay circuit (3) is connected to the other input of the arithmetic circuit (2). Further, the output of the subtraction circuit (8) is connected to a signal output terminal (9). Note that the arithmetic circuit (2) is composed of an adder circuit that adds two inputs.

次に動作について説明する。第1図において、映像信号
入力端子(1)の信号をVi、系数器(5)の入力信号
をVl、系数器(5)の出力信号をV2、信号出力端子
(9)の出力を■O1系数系数5)の帰還系数をに、l
Hi延回路(3)の伝達関数をGとすると■、■式が成
立する。
Next, the operation will be explained. In Figure 1, the signal of the video signal input terminal (1) is Vi, the input signal of the multiplier (5) is Vl, the output signal of the multiplier (5) is V2, and the output of the signal output terminal (9) is ■O1. Let the feedback system of the system 5) be, l
When the transfer function of the Hi extension circuit (3) is G, equations (1) and (2) hold true.

VO=Vl −V2 = (1−K)Vl  ・・・■
V 1 = V i + G V 2 = V i 十
K G V 1−・・(li■、0式よりvlを消去す
ると、入出力間には■式の関係が成立する。
VO=Vl -V2 = (1-K)Vl...■
V 1 = Vi + G V 2 = Vi 10 K G V 1- (li ■, When vl is deleted from the equation 0, the relationship of the equation (■) is established between the input and output.

■式の伝達関数は0式で表わされる・ ・・・■ 0式は、nが正の整数とすれば、f wt−n e r
bのは第2図と同じく、水平周波数の整数倍の所に腹部
ができるくし形フィルタであることを示している。この
とき、a部の信号レベルは1であり、Kの値とは無関係
となっている。したがって、にの値を可変しても、第2
図の信号振幅の信号量正規化回路(7)は不要となる。
■The transfer function of formula is expressed by formula 0...■ Formula 0 is f wt-n e r if n is a positive integer.
Similarly to FIG. 2, part b shows a comb-shaped filter in which the abdomen is formed at an integer multiple of the horizontal frequency. At this time, the signal level of section a is 1 and is unrelated to the value of K. Therefore, even if the value of is varied, the second
The signal amplitude normalization circuit (7) shown in the figure becomes unnecessary.

なお、系数器(5)の系数には外部から任意に設定可能
としである。
Note that the coefficient of the coefficient unit (5) can be arbitrarily set from the outside.

上記実施例では水平周波数の整数倍の所に腹部が、奇数
倍の所にくし部ができるY形くし形フィルタについて説
明したが、81図中の演算回路(2)を、映像信号入力
端子(1)の信号を被減算信号とし、IH,l延回路(
3)の出力信号を減算信号として減算する減算回路で構
成すれば、水平周波数の整数倍の所にくし部が、奇数倍
の所に腹部ができるC形くし形フィルタになることは容
易に推察され、上記実施例と同様の効果を奏することは
明らかである。
In the above embodiment, a Y-shaped comb filter was described in which the abdomen is located at an integer multiple of the horizontal frequency and the comb section is located at an odd multiple of the horizontal frequency. 1) is the signal to be subtracted, and the IH, l extension circuit (
If it is configured with a subtraction circuit that subtracts the output signal of 3) as a subtraction signal, it is easy to infer that it will become a C-shaped comb filter with comb parts at integral multiples of the horizontal frequency and abdomens at odd number multiples. It is clear that the same effect as the above embodiment can be achieved.

[発明の効果] 以上のように、この発明によれば、系数器出力から循環
遅延信号入力を得るように構成したので、信号量正規化
回路が不要となり、系数器系数を容易に可変することの
できる循環型くし形フィルタが得られる。
[Effects of the Invention] As described above, according to the present invention, since the cyclic delay signal input is obtained from the output of the system, there is no need for a signal amount normalization circuit, and the system number of the system can be easily varied. A circulating comb filter is obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明によるくし形フィルタの実施例を示す
ブロック図、第2図は従来のくし形フィルタを示すブロ
ック図である。 (1)・・・映像信号入力端子、(2)・・・演算回路
、(3)・・・IH遅延回路、(5)・・・系数器、(
8)・・・減算回路、(S)・・・信号出力端子。 なお、図中、同一符号は同一または相当部分を示す。 第1図 第2図 手続補正書(自発) 6キ724 昭和     月  日 国
FIG. 1 is a block diagram showing an embodiment of a comb filter according to the present invention, and FIG. 2 is a block diagram showing a conventional comb filter. (1)...Video signal input terminal, (2)...Arithmetic circuit, (3)...IH delay circuit, (5)...Mathometer, (
8)...Subtraction circuit, (S)...Signal output terminal. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1 Figure 2 Procedural amendment (voluntary) 6ki724 Showa Month Japan

Claims (4)

【特許請求の範囲】[Claims] (1)2入力を有する演算回路の第1の入力端子には映
像入力信号が印加され、上記演算回路の出力は系数器の
入力端子と、2入力を有する減算回路の被減算入力端子
にそれぞれ接続され、系数器の出力は、上記減算回路の
減算入力端子と、1水平時間遅延回路の入力端子にそれ
ぞれ接続され、上記1水平時間遅延回路の出力は上記演
算回路の第2の入力端子に接続され、上記減算回路の出
力端子から出力信号を得るように構成されたことを特徴
とするくし形フィルタ。
(1) A video input signal is applied to a first input terminal of an arithmetic circuit having two inputs, and the output of the arithmetic circuit is applied to an input terminal of a series generator and an input terminal to be subtracted of a subtraction circuit having two inputs, respectively. The output of the multiplier is connected to the subtraction input terminal of the subtraction circuit and the input terminal of one horizontal time delay circuit, and the output of the one horizontal time delay circuit is connected to the second input terminal of the arithmetic circuit. A comb filter connected to the subtractor circuit and configured to obtain an output signal from an output terminal of the subtraction circuit.
(2)演算回路は、2入力を加算する加算回路である特
許請求の範囲第1項記載のくし形フィルタ。
(2) The comb filter according to claim 1, wherein the arithmetic circuit is an adder circuit that adds two inputs.
(3)演算回路は、映像入力信号を被減算信号とし、1
水平時間遅延回路の出力信号を減算信号として減算する
減算回路である特許請求の範囲第1項記載のくし形フィ
ルタ。
(3) The arithmetic circuit uses the video input signal as the signal to be subtracted, and 1
The comb filter according to claim 1, which is a subtraction circuit that subtracts the output signal of the horizontal time delay circuit as a subtraction signal.
(4)系数器の系数を、外部から任意に設定可能とした
特許請求の範囲第1項記載のくし形フィルタ。
(4) The comb filter according to claim 1, wherein the coefficient of the coefficient unit can be arbitrarily set from the outside.
JP60083513A 1985-04-18 1985-04-18 Comb-line filter Pending JPS61242175A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP60083513A JPS61242175A (en) 1985-04-18 1985-04-18 Comb-line filter
US06/852,207 US4684976A (en) 1985-04-18 1986-04-15 Feedback comb-type filter
GB8609529A GB2175166B (en) 1985-04-18 1986-04-18 Feedback comb-type filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60083513A JPS61242175A (en) 1985-04-18 1985-04-18 Comb-line filter

Publications (1)

Publication Number Publication Date
JPS61242175A true JPS61242175A (en) 1986-10-28

Family

ID=13804564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60083513A Pending JPS61242175A (en) 1985-04-18 1985-04-18 Comb-line filter

Country Status (1)

Country Link
JP (1) JPS61242175A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57185773A (en) * 1981-05-04 1982-11-16 Philips Nv Noise suppressing circuit for video signal
JPS58111520A (en) * 1981-12-23 1983-07-02 エヌ ベー フィリップス フルーイランペンファブリケン Circulation type digital filter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57185773A (en) * 1981-05-04 1982-11-16 Philips Nv Noise suppressing circuit for video signal
JPS58111520A (en) * 1981-12-23 1983-07-02 エヌ ベー フィリップス フルーイランペンファブリケン Circulation type digital filter

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