JPS6235782A - Comb line filter - Google Patents

Comb line filter

Info

Publication number
JPS6235782A
JPS6235782A JP60174485A JP17448585A JPS6235782A JP S6235782 A JPS6235782 A JP S6235782A JP 60174485 A JP60174485 A JP 60174485A JP 17448585 A JP17448585 A JP 17448585A JP S6235782 A JPS6235782 A JP S6235782A
Authority
JP
Japan
Prior art keywords
signal
circuit
output
filter
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60174485A
Other languages
Japanese (ja)
Inventor
Sumio Kato
純雄 加藤
Shoichi Sugihara
杉原 正一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60174485A priority Critical patent/JPS6235782A/en
Priority to US06/852,207 priority patent/US4684976A/en
Priority to GB8609529A priority patent/GB2175166B/en
Publication of JPS6235782A publication Critical patent/JPS6235782A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the need for a signal quantity normalizing circuit, to easily vary the coefficient of a coefficient multiplier, and to prevent a false signal from being generated by cutting of a circulation signal unless there is vertical correlation while obtaining the circulation signal from the output of the coefficient multiplier. CONSTITUTION:A circulation delay signal input is obtained from the output of the coefficient multiplier 5 to eliminate the need for the signal quantity normalizing circuit and a killer circuit 9 is provided in a circulation loop to prevent a false signal from being generated. The signal quantity normalizing circuit is unneeded, so the desired degree of SN ratio improvement is obtained by varying only the coefficient K of the coefficient multiplier 5 without any variation in signal quantity. Further, the killer circuit 9 cuts off the circulation loop of the signal unless there is vertical correlation, thereby suppressing the generation fo a false signal.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はくし形フィルタに係り、とくに、映像信号の
信号/雑音(SIN)比改善等に用いられる循環型くし
形フィルタの構成に関するものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a comb filter, and particularly relates to the configuration of a circulating comb filter used for improving the signal/noise (SIN) ratio of a video signal. .

〔従来の技術〕[Conventional technology]

循環型くし形フィルタは映像信号のSハ比改善等に用い
られている。−例として第2図に昭和43年4月NHK
技研月報“くし形フィルタによる映像信号のプロセスと
画質″に記載された循環型くし形フィルタを示し、 S
/N比改善動作について説明する。第2図において、(
1)は映像信号入力端子、(2)は演算回路、(3)は
1水平時間(以下の説明ではIHと略記する)遅延回路
、(4)は加算回路、(5)は系数器、(6)は信号出
力端子、(7)は信号量正規化回路、(8)は正規化信
号出力端子である。
Circulating comb filters are used to improve the S/C ratio of video signals. -As an example, Figure 2 shows NHK in April 1962.
The circulating comb filter described in the Giken monthly report “Video signal process and image quality using comb filter” is shown.
/N ratio improvement operation will be explained. In Figure 2, (
1) is a video signal input terminal, (2) is an arithmetic circuit, (3) is a one horizontal time (abbreviated as IH in the following explanation) delay circuit, (4) is an addition circuit, (5) is a multiplier, ( 6) is a signal output terminal, (7) is a signal amount normalization circuit, and (8) is a normalized signal output terminal.

欠番こ動作について説明する。今、映像信号入力端子+
1)の信号をVi、IH遅延回路(3)の入力信号をv
H1信号出力端子(6)の信号をVoとし、系数器(5
)の帰還系数をK、IH遅延回路(3)の伝達関数をG
とすれば、〔1〕、〔2〕式が成立する。
The missing number operation will be explained. Now, video signal input terminal +
The signal of 1) is Vi, and the input signal of IH delay circuit (3) is v.
The signal of the H1 signal output terminal (6) is set to Vo, and the
) is the feedback system number K, and the transfer function of the IH delay circuit (3) is G.
If so, equations [1] and [2] hold true.

VH−Vi = KVo  ・・=・[13Vo = 
Vi ” GVH−−[2](x〕、  (2〕式から
、vHを消去すると出力信号V。
VH-Vi=KVo...=・[13Vo=
Vi ” GVH--[2](x) From equation (2), when vH is eliminated, the output signal V is obtained.

と入力信号Vtとの関係は〔3〕式となる。The relationship between the input signal Vt and the input signal Vt is expressed by equation [3].

■。=1+G 、ヨ。Vi  ・・−・・〔3〕 1+G 〔3〕式の−「コテ−が第2図のフィルタの伝達関数で
あり、IH遅延回路の伝達関数Gは、ライン相関の大き
いテレビ信号を扱う場合、τL =1/11(f、はラ
イン周波数)とすればよ(。
■. =1+G, yo. Vi...--[3] 1+G In equation [3], -' is the transfer function of the filter in Figure 2, and the transfer function G of the IH delay circuit is, when dealing with television signals with large line correlation, Let τL = 1/11 (f is the line frequency).

1  ′″jωτ = LJ = e   1CO1k+3f、 −jliln
ωr、と表わされる。
1 ′″jωτ = LJ = e 1CO1k+3f, -jliln
It is expressed as ωr.

したがって、〔3〕式の伝達関数は、〔4〕式のように
表わすことが出来る。
Therefore, the transfer function of equation [3] can be expressed as equation [4].

nを正の整数とすると、〔4〕式はf=nf1のとき、
7、”  ’ = ”””)fX、のとき0となり、こ
れは第2図のフィルタが、ライン周波数の整数倍の所に
腹部ができる(し形フィルタであり、帰還率Kを変える
ことによって、フィルタの振幅周波数等性の尖鋭さが変
わるので、 S/N比改善度が自由に設定できることを
表わしている。
When n is a positive integer, formula [4] becomes when f=nf1,
7. `` ' = ``'''') When f This shows that the degree of S/N ratio improvement can be freely set because the sharpness of the amplitude-frequency equality of the filter changes.

又、信号量正規化回路(7)は、信号出力端子(6)の
′信号VoがKの関数となるので、Voを(1−K)倍
することで、正規化信号出力端子(8)に、Kの変化に
より出力振幅変化を伴なわない信号を出力するために設
けられている。
In addition, since the signal Vo at the signal output terminal (6) is a function of K, the signal amount normalization circuit (7) multiplies Vo by (1-K), so that the normalized signal output terminal (8) It is provided in order to output a signal that does not involve a change in output amplitude due to a change in K.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の回路の場合、S/N比改善度を変化させるために
系数器の系数Kを変化させると、信号量正規化回路の乗
数もKに比例させて変化させなければならず1両回路の
整合性を得るのが難かしく。
In the case of conventional circuits, when the coefficient K of the multiplier is changed in order to change the degree of improvement of the S/N ratio, the multiplier of the signal amount normalization circuit must also be changed in proportion to K. Difficult to achieve consistency.

実質的にKを可変することは困難であった。また垂直相
関のない映像信号が入力された場合、にせ信号か発生す
るなどの問題点があった。
It has been difficult to substantially vary K. Furthermore, when a video signal without vertical correlation is input, there is a problem that a false signal is generated.

この発明は上記のような問題点を解消するためになされ
たもので、系数器の系数Kを容易に変化することが出来
、又、にせ信号が発生しない循環型(し形フィルタ回路
を提供することを目的とするO 〔問題点を解決1−ルための手段〕 この発明に係る循環型くし形フィルタは循環遅延信号入
力を系数器出力から取ることによって。
This invention was made in order to solve the above-mentioned problems, and provides a circular filter circuit in which the coefficient K of the coefficient generator can be easily changed, and in which no false signals are generated. [Means for Solving the Problems] The cyclic comb filter according to the present invention takes the cyclic delay signal input from the output of the multiplier.

信号量正規化回路を不要とし、又、循環ループ内にキラ
ー回路を設けて、にせ信号か発生しないよう暮こ構成し
たものである。
This eliminates the need for a signal amount normalization circuit, and a killer circuit is provided in the circulation loop to prevent the generation of false signals.

〔作 用〕[For production]

この発明6コ2いて(コ、信号量正規化回路が不要とな
るので、系数器の系数にのみを変化させることで希望の
S/N比〔友雪度が、1d号)量変化を伴なわずに得ら
れる。又、垂直相関かrlい場合はキラー回路により信
号の循環ループを遮断して、にせ信号の発生を抑圧する
With this invention, the signal amount normalization circuit is not required, so by changing only the coefficient of the coefficient generator, the desired S/N ratio [Yukiyuki degree is 1d] can be achieved with a change in the amount. You can get it without asking. Furthermore, if the vertical correlation is low, a killer circuit interrupts the signal circulation loop to suppress the generation of false signals.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を図について説明する。第1
図において、(1)は映像信号入力端子、(2)は演算
回路、[3)はIH遅延回路、(5)は系数器、(9)
はキラー回路、(10は減算回路、(ロ)は信号出力端
子である。1よお、第1図中第2図と同等部分には同一
記号を用いている。
An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a video signal input terminal, (2) is an arithmetic circuit, [3] is an IH delay circuit, (5) is a multiplier, and (9)
1 is a killer circuit, (10 is a subtraction circuit, and (b) is a signal output terminal. 1 and 1, the same symbols are used for parts in FIG. 1 that are equivalent to those in FIG. 2.

次に動作について説明する。今、垂直相関のある映像信
号が入力されCいる場合、キラー回路(9)はバッファ
として、信号に何ら形番を及ばざない。
Next, the operation will be explained. Now, when a video signal with vertical correlation is input, the killer circuit (9) acts as a buffer and does not affect the signal in any way.

この時、映像信号入力端子(1)の信号をvi、キラー
回路(9)の出力信号をvl、系数器(5)の出力信号
をv2、信号出力端子(ロ)の出力をVoとすると、式
〔5]、 (6]が成立する。
At this time, if the signal of the video signal input terminal (1) is vi, the output signal of the killer circuit (9) is vl, the output signal of the multiplier (5) is v2, and the output of the signal output terminal (b) is Vo, Equations [5] and (6) hold true.

Vo = V、 −V、 = (1−K)V、  −・
・−・−(5]V、 == Vl 4 GV、 == 
Vi + KGV、 ・−・−・・[6)(5] 、 
[61式から、vIを消去すると、入出力の関係には、
〔7〕式が成立する。
Vo = V, -V, = (1-K)V, -・
・−・−(5]V, == Vl 4 GV, ==
Vi + KGV, ・−・−・・[6)(5],
[If vI is deleted from equation 61, the input/output relationship becomes
[7] Formula holds true.

Vo−二二監Vi  ・・・・・・〔7〕1−KG 〔7〕式の伝達関数は(1−K)/(1−KG)であり
、これは〔8〕式のように表わされる。
Vo - Nijikan Vi ...... [7] 1-KG The transfer function of equation [7] is (1-K)/(1-KG), which can be expressed as equation [8]. It will be done.

〔8〕式はnが正の侵数とずれは、f=nf1のときに
1、f = (n++/x)fI、のとき、(1−K 
)/(14K )となり、これは第2図のフィルタと同
じ(、ライン周波数の整数倍の所に腹部か出来るくし形
フィルタであることを示している。f=nfzのときの
信号レベルは1であり、にの値とは無関係となっている
ので、Kの値を可変しても、信号振幅の正規化回路は不
要である。
[8] Equation shows that the invasion number and deviation for which n is positive is 1 when f = nf1, and (1-K when f = (n++/x)fI).
)/(14K), which is the same as the filter in Figure 2 (, indicating that it is a comb-shaped filter with a belly at an integer multiple of the line frequency.When f=nfz, the signal level is 1 is independent of the value of K, so even if the value of K is varied, a signal amplitude normalization circuit is not required.

次に垂直相関がない映像信号か入力された場合について
考える。この時は、前記〔5〕〜〔8〕式は成りたたす
、にせ信号か発生する。したかつて。
Next, consider the case where a video signal without vertical correlation is input. At this time, the above-mentioned formulas [5] to [8] are satisfied, and a false signal is generated. Once upon a time.

垂直相関かfぽい場合は、キラー回路(9)によって。If there is a vertical correlation or something like f, use the killer circuit (9).

系数器(5)、IH遅延回路(3)で溝成さnる帰還ル
ープをa断し、信号入力端子(1)から入力された信号
を、信号出力端子Ql)に出力しないようにすれば、に
せ信号は発生しない。
If the feedback loop formed by the multiplier (5) and the IH delay circuit (3) is cut off, the signal input from the signal input terminal (1) is not output to the signal output terminal Ql). , no false signals are generated.

なお、上記実施例では、ライン周波数の整数倍の所に腹
部か、奇数倍の所にくし部が出来るY形くし形フィルタ
について説明したが、第1図中の演算回路(2)に8い
て信号入力端子(1)の信号がらlH遅延回路(3)の
出力が減算すれば、ライン周波数の整数倍の所にくし部
が、奇数倍の所に腹部が出来るC形くし形フィルタにな
ることは、本発明1こよるフィルタの構成上、容易に推
察され、上記実施例と同様の効果を奏することは明らか
である。
In the above embodiment, a Y-shaped comb filter is described in which a comb portion is formed at an integral multiple of the line frequency or at an odd multiple of the line frequency. If the output of the lH delay circuit (3) is subtracted from the signal at the signal input terminal (1), a C-shaped comb filter will be created, with comb parts at integral multiples of the line frequency and abdomens at odd number multiples. This can be easily inferred from the structure of the filter according to the present invention 1, and it is clear that the same effect as the above embodiment is achieved.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、系数器出力から、循
環信号を得ると同時に、垂直相関がない場合は前記循環
信号をS断するように(し形フィルタを構成したので信
号量正規化回路が不要で。
As described above, according to the present invention, a cyclic signal is obtained from the output of the multiplier, and at the same time, when there is no vertical correlation, the cyclic signal is cut off (since the square filter is configured, the signal amount is normalized). No circuit required.

系数器系数を容易に可変することが出来ると同時に、に
せ信号が発生しない循環型くし形フィルタが得られる。
A circulating comb filter can be obtained in which the system number can be easily varied and at the same time, no false signals are generated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例に1よるくし形フィルタを
示すブロック図、第2図は従来のくし形フィルタを示す
ブロック図である。 図に2いて、C1)は映像信号入力端子、(2)は演算
回路、(3)はIH遅延回路、〔5)は系数器、(9)
はキラー回路、αQは減算回路、(ロ)は信号出力端子
である0なお、図中同一符号は同一、又は相当部分を示
す0
FIG. 1 is a block diagram showing a comb filter according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional comb filter. In Figure 2, C1) is a video signal input terminal, (2) is an arithmetic circuit, (3) is an IH delay circuit, [5] is a multiplier, and (9)
0 is the killer circuit, αQ is the subtraction circuit, and (b) is the signal output terminal.0 Note that the same symbols in the figures indicate the same or equivalent parts.

Claims (5)

【特許請求の範囲】[Claims] (1)第1の入力端子に映像入力信号が入力される演算
回路、この演算回路の出力が入力されるキラー回路、こ
のキラー回路の出力が入力される系数器、この系数器の
出力を1水平時間遅延させて上記演算回路の第2の入力
端子に供給する1水平時間遅延回路、及び上記キラー回
路の出力から上記系数器の出力を減算して所要のフィル
タ出力信号を得る減算回路を備えたことを特徴とするく
し形フィルタ。
(1) An arithmetic circuit to which a video input signal is input to the first input terminal, a killer circuit to which the output of this arithmetic circuit is input, a multiplier to which the output of this killer circuit is input, and an output of this multiplier to 1 a horizontal time delay circuit that delays the horizontal time and supplies the signal to a second input terminal of the arithmetic circuit; and a subtraction circuit that subtracts the output of the multiplier from the output of the killer circuit to obtain a desired filter output signal. A comb-shaped filter characterized by:
(2)演算回路は、2入力を加算する加算回路であるよ
うにしたことを特徴とする特許請求の範囲第1項記載の
くし形フィルタ。
(2) The comb filter according to claim 1, wherein the arithmetic circuit is an adder circuit that adds two inputs.
(3)演算回路は、映像入力信号を被減算信号とし、1
水平時間遅延回路の出力信号を減算信号として減算する
減算回路であるようにしたことを特徴とする特許請求の
範囲第1項記載のくし形フィルタ。
(3) The arithmetic circuit uses the video input signal as the signal to be subtracted, and 1
2. The comb filter according to claim 1, wherein the comb filter is a subtraction circuit that subtracts the output signal of the horizontal time delay circuit as a subtraction signal.
(4)系数器の系数を、外部から任意に設定可能とした
ことを特徴とする特許請求の範囲第1項ないし第3項の
いずれかに記載のくし形フィルタ。
(4) The comb filter according to any one of claims 1 to 3, characterized in that the coefficient of the coefficient generator can be arbitrarily set from the outside.
(5)キラー回路は所定の制御信号により、フィルタの
出力信号を減衰または遮断状態にするようにしたことを
特徴とする特許請求の範囲第1項ないし第4項のいずれ
かに記載のくし形フィルタ。
(5) The comb according to any one of claims 1 to 4, wherein the killer circuit is configured to attenuate or cut off the output signal of the filter by a predetermined control signal. filter.
JP60174485A 1985-04-18 1985-08-08 Comb line filter Pending JPS6235782A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP60174485A JPS6235782A (en) 1985-08-08 1985-08-08 Comb line filter
US06/852,207 US4684976A (en) 1985-04-18 1986-04-15 Feedback comb-type filter
GB8609529A GB2175166B (en) 1985-04-18 1986-04-18 Feedback comb-type filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60174485A JPS6235782A (en) 1985-08-08 1985-08-08 Comb line filter

Publications (1)

Publication Number Publication Date
JPS6235782A true JPS6235782A (en) 1987-02-16

Family

ID=15979305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60174485A Pending JPS6235782A (en) 1985-04-18 1985-08-08 Comb line filter

Country Status (1)

Country Link
JP (1) JPS6235782A (en)

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