JPS61242139A - Clock return control system - Google Patents

Clock return control system

Info

Publication number
JPS61242139A
JPS61242139A JP60082263A JP8226385A JPS61242139A JP S61242139 A JPS61242139 A JP S61242139A JP 60082263 A JP60082263 A JP 60082263A JP 8226385 A JP8226385 A JP 8226385A JP S61242139 A JPS61242139 A JP S61242139A
Authority
JP
Japan
Prior art keywords
clock
transmission
speed
transmitting
transmission line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60082263A
Other languages
Japanese (ja)
Inventor
Kazuo Yamane
一雄 山根
Yuji Miyaki
裕司 宮木
Takemi Endo
遠藤 竹美
Masanori Arai
荒井 雅典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60082263A priority Critical patent/JPS61242139A/en
Publication of JPS61242139A publication Critical patent/JPS61242139A/en
Pending legal-status Critical Current

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  • Synchronisation In Digital Transmission Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To transfer a low-speed clock obtained by giving the 1/n division to a clock extracted at a transmission/reception part of one side at the side of a nondefect transmission line to a transmission/reception part of the other side through an adjacent intermediate repeater station when a fault occurs on the transmission line and to give n-multiplication to said low-speed clock to apply it to a transmission part as a transmission clock of an original speed. CONSTITUTION:If faults occurs on the transmission lines 17 and 26, a control part 30 controls a switch part 22 to apply a clock to a transmission part 23 via a multiplier 25. Thus the clock extracted through a reception part 11 of a transmission/reception part 10 of one side at the side of a nondefect transmission line 16 is divided into 1/n by a clock divider 14 and transferred to a transmission/reception part 20 of the other side via a transfer line 18 in the form of a low-speed clock. This clock is multiplied by (n) by a multiplier 25 of the part 20 and turned into the clock of the original speed. This clock is applied to the part 23 via the part 22 as a transmission clock and the fault information, etc. are sent to a transmission line 27. Thus the speed similar to a normal transmission clock is secured for transmission of the fault information to a nondefective transmission line.

Description

【発明の詳細な説明】 〔概要〕 伝送路断障害時に、中間中継局でその障害伝送路側と逆
方向の健全な伝送路側の受信部でクロックを抽出し、そ
のクロックを1/Hに分周して低速クロックとし、その
低速クロックを送信部側へ転送し、n逓倍して送信クロ
ックとするもので、廉価な構成でクロックの転送を可能
とするものである。
[Detailed Description of the Invention] [Summary] When a transmission line failure occurs, a clock is extracted at an intermediate relay station on a healthy transmission line side opposite to the failed transmission line side, and the clock is divided into 1/H. The low-speed clock is transferred to the transmitter side, multiplied by n, and used as the transmit clock, making it possible to transfer the clock with an inexpensive configuration.

〔産業上の利用分野〕[Industrial application field]

本発明は、伝送路の障害時に、健全な伝送路側からクロ
ックを抽出し、そのクロックを障害情報等を送出する為
に健全な伝送路側の送信部へ転送するクロックリターン
制御方式に関するものである。
The present invention relates to a clock return control method that extracts a clock from a healthy transmission line when a transmission line fails, and transfers the clock to a transmitter on the healthy transmission line in order to send failure information and the like.

長距離伝送に於いては、複数の中間中継局が端局間に設
けられ、各中間中継局は、波形整形、識別再生、タイミ
ング抽出の3R機能を備えているのが一般的である。又
主信号の伝送回線のみでな(、各中間中継局の動作状態
情報を端局へ転送する為の監視回線や、端局間、端局と
中間中継局間或いは中間中継局相互間の打金回線等を設
けることが多いものである。この場合、主信号の伝送回
線とは別の回線とするのではなく、主信号に動作状態情
報や打金情報を時分割等により重畳して同一回線で伝送
するのが一般的であり、特に光伝送システムに多く採用
されている。このような伝送システムに於いては、障害
情報等を送出する場合にも、主信号伝送用のクロックが
必要となる。
In long-distance transmission, a plurality of intermediate relay stations are generally provided between terminal stations, and each intermediate relay station is generally equipped with the 3R functions of waveform shaping, identification reproduction, and timing extraction. In addition, it is not only the transmission line for the main signal (but also the monitoring line for transferring the operating status information of each intermediate relay station to the terminal station, the communication between terminal stations, between the terminal station and intermediate relay stations, or between intermediate relay stations). In this case, rather than using a separate line from the main signal transmission line, operating status information and credit information are superimposed on the main signal by time division, etc. It is common to transmit over lines, and it is especially often used in optical transmission systems.In such transmission systems, a clock for main signal transmission is required even when transmitting fault information etc. becomes.

〔従来の技術〕[Conventional technology]

伝送路障害時には、中間中継局から健全な伝送路側の端
局へ障害情報を送出するものであり、その場合に送信ク
ロ7りが必要であるから、各中間中継局に予めクロック
発生器を設けて、障害情報送出時に起動させる方式が知
られている。しかし、総ての中間中継局にクロック発生
器を設けることは経済的でない欠点がある。そこで、障
害伝送路側と逆方向の健全な伝送路側の受信信号からク
ロックを抽出し、そのクロックを健全な伝送路側の送信
部へ転送して、障害情報を送出する為の送信クロックと
するクロックリターン方式が知られている。
When a transmission path failure occurs, fault information is sent from the intermediate relay station to the terminal station on the healthy transmission path side. In this case, a transmission clock is required, so a clock generator is installed in each intermediate relay station in advance. A method is known in which the system is activated when failure information is sent. However, providing a clock generator at every intermediate relay station has the disadvantage that it is not economical. Therefore, the clock is extracted from the received signal on the healthy transmission line side in the opposite direction to the faulty transmission line side, and the clock is transferred to the transmitter on the healthy transmission line side, and is used as the transmission clock for sending out the fault information. The method is known.

例えば、第3図に示すように、端局31,32間に複数
の中間中継局33−1〜33−nが配置され、端局31
から端局32へ伝送する為の伝送路34と、その反対方
向の伝送路35とを設けている場合に、A、B点の伝送
路に障害が発生すると、中間中継局33−1では、健全
な伝送路側の受信部36(送信部の図示を省略)でクロ
ックを抽出して端局31方向への送信部37(受信部の
図示を省略)へ転送し、送信部37はそのクロックによ
り障害情報等を健全な伝送路側の端局31へ送出し、文
中間中継局33−2では、健全な伝送路側の受信部38
(送信部の図示を省略)でクロックを抽出して送信部3
9(受信部の図示を省略)へ転送し、送信部39はその
クロックにより障害情報等を健全な伝送路側の端局32
へ送出するものである。従って、クロック発生器を設け
なくても、受信信号から抽出したクロックを送信側にリ
ターンして、障害情報等の送出が可能となるものである
For example, as shown in FIG. 3, a plurality of intermediate relay stations 33-1 to 33-n are arranged between terminal stations 31 and 32, and
When a transmission path 34 for transmitting data from the terminal station 32 to the terminal station 32 and a transmission path 35 in the opposite direction are provided, if a failure occurs in the transmission path at points A and B, the intermediate relay station 33-1 will: The receiving section 36 (the transmitting section is not shown) on the side of the healthy transmission path extracts the clock and transfers it to the transmitting section 37 (the receiving section is not shown) toward the terminal station 31, and the transmitting section 37 uses the clock. Fault information, etc. is sent to the terminal station 31 on the side of the healthy transmission line, and at the intermediate relay station 33-2, it is sent to the receiving unit 38 on the side of the healthy transmission line.
(The illustration of the transmitter is omitted) extracts the clock and transmits the clock to the transmitter 3.
9 (receiving unit not shown), and the transmitting unit 39 uses its clock to transmit fault information, etc. to the terminal station 32 on the side of the healthy transmission path.
It is to be sent to. Therefore, even without providing a clock generator, it is possible to return the clock extracted from the received signal to the transmitting side and send out fault information, etc.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

各中間中継局、例えば、中間中継局33−1に於ける一
方の伝送路に対する受信部36と図示を省略した送信部
とは同一ユニット内に構成されているとしても、他方の
伝送路に対する送信部37とは、同一のユニット内に構
成されているものではないので、クロックリターン方式
を適用した場合に、受信部36と送信部37との間に、
クロック転送用の接続構成が必要となるものである。又
高速光伝送システムに於いては、数GHz程度或いはそ
れ以上の高速送信クロックを用いるものであるから、受
信部36.38で抽出したクロックを電気信号レベルで
送信部37.39へ転送する構成が複雑となり、且つ高
価なコネクタ等を用いる必要が生じる欠点がある。
Even if the receiving section 36 for one transmission path and the transmitting section (not shown) in each intermediate relay station, for example, the intermediate relay station 33-1, are configured in the same unit, the transmission for the other transmission path is Since the parts 37 and 37 are not configured in the same unit, when the clock return method is applied, there is a
This requires a connection configuration for clock transfer. Furthermore, since a high-speed optical transmission system uses a high-speed transmission clock of several GHz or more, the clock extracted by the receiving section 36.38 is transferred to the transmitting section 37.39 at an electrical signal level. This method has disadvantages in that it is complicated and requires the use of expensive connectors.

本発明は、抽出したクロックの転送を廉価な構成で行う
ことを目的とするものである。
An object of the present invention is to transfer extracted clocks with an inexpensive configuration.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のクロックリターン制御方式は、第1図を参照し
て説明すると、端局1.2間に複数の中間中継局3を配
置し、中間中継局3の一方の送受信部4の受信部5で抽
出したクロックを1 / nに分周して転送する為の分
周手段7と、他方の送受信部4の送信部6へ1週倍して
送信クロックを加える為の逓倍手段8とを設け、x印で
示すような位置の伝送路の障害時に、その障害個所に隣
接する中間中継局3に於いて、障害個所とは逆方向の健
全な伝送路側の一方の送受信部4の受信部5で抽出した
クロックを、分周手段7により1 / nに分周し、分
周された低速クロックを他方の送受信部4に転送し、そ
の低速クロックを逓倍手段8により1週倍して送信部6
の送信クロックとするものである。
The clock return control method of the present invention will be explained with reference to FIG. A frequency dividing means 7 is provided for dividing the frequency of the clock extracted by 1/n and transmitting the frequency, and a multiplying means 8 is provided for multiplying the frequency by one week and adding the transmission clock to the transmitting section 6 of the other transmitting/receiving section 4. , when there is a fault in the transmission line at the position indicated by the x mark, the receiving section 5 of one of the transmitter/receivers 4 on the side of the healthy transmission line in the opposite direction from the fault point in the intermediate relay station 3 adjacent to the fault point. The frequency of the extracted clock is divided by 1/n by the frequency dividing means 7, the divided low-speed clock is transferred to the other transmitting/receiving section 4, and the low-speed clock is multiplied by one week by the multiplying means 8 and sent to the transmitting section. 6
This is the transmission clock.

〔作用〕[Effect]

受信部5で抽出したクロックを分周手段7により1 /
 nに分周することにより、低速クロックとして転送す
ることができ、一方の送受信部から他方の送受信部へク
ロックを転送する為の実装構成が簡単となり、廉価なコ
ネクタ等の使用が可能となる。又他方の送受信部では、
逓倍手段8によって低速クロックをn逓倍することによ
り、元の速度の送信クロックとして送信部6に加えるこ
とができる。
The clock extracted by the receiving section 5 is divided into 1/
By dividing the frequency by n, it can be transferred as a low-speed clock, and the mounting structure for transferring the clock from one transmitting/receiving section to the other transmitting/receiving section is simple, and inexpensive connectors and the like can be used. In the other transmitter/receiver section,
By multiplying the low-speed clock by n using the multiplier 8, it can be applied to the transmitter 6 as a transmission clock at the original speed.

〔実施例〕〔Example〕

以下図面を参照して本発明の実施例について詳細に説明
する。
Embodiments of the present invention will be described in detail below with reference to the drawings.

第2図は本発明の実施例のブロック図であり、中間中継
局内の要部を示すものである。同図に於いて、10.2
0は送受信部、11.21は受信部、12.22は切換
部、13.23は送信部、14.24は分周器、15.
25は逓倍器、16.17.26.27は伝送路、18
.28はクロックの転送線、30は制御部である。
FIG. 2 is a block diagram of an embodiment of the present invention, showing main parts within an intermediate relay station. In the same figure, 10.2
0 is a transmitting/receiving section, 11.21 is a receiving section, 12.22 is a switching section, 13.23 is a transmitting section, 14.24 is a frequency divider, 15.
25 is a multiplier, 16.17.26.27 is a transmission line, 18
.. 28 is a clock transfer line, and 30 is a control section.

受信部11.21は、端局或いは中間中継局から伝送路
16.26を介して伝送された信号を受信し、受信信号
からクロックを抽出すると共にデータを識別再生し、切
換部12.22を介してクロックとデータとを送信部1
3.23へ転送する、送信部13.23は転送されたク
ロックを送信クロックとして、転送されたデータを伝送
路17.27に送出する。なお、光伝送システムに於い
ては、伝送路16.17,26.27は光ファイバ等に
より構成され、受信部11.21は受信光信号を電気信
号に変換する光電変換部を備え、又送信部13.23は
電気信号を光信号に変換する電光変換部を備えるもので
ある。
The receiving section 11.21 receives the signal transmitted from the terminal station or the intermediate relay station via the transmission path 16.26, extracts the clock from the received signal, identifies and reproduces the data, and switches the switching section 12.22. The clock and data are transmitted through the unit 1
The transmitter 13.23 sends the transferred data to the transmission path 17.27 using the transferred clock as a transmission clock. In the optical transmission system, the transmission lines 16, 17 and 26, 27 are composed of optical fibers, etc., and the receiving section 11.21 is equipped with a photoelectric conversion section that converts the received optical signal into an electrical signal, and the transmitting section 11. The sections 13 and 23 are provided with an electro-optical conversion section that converts electrical signals into optical signals.

切換部12.22は制御部30から制御され、正常時は
、前述のように、受信部11.21からのクロックとデ
ータとを送信部13.23に転送するように切換えられ
ている。又制御部30は障害監視機能を備え、伝送路の
障害時に切換部12.22を制御すると共に、障害情報
の送出制御等も行うものである。
The switching section 12.22 is controlled by the control section 30, and is normally switched to transfer the clock and data from the receiving section 11.21 to the transmitting section 13.23, as described above. The control section 30 also has a fault monitoring function, and controls the switching section 12.22 in the event of a fault in the transmission path, as well as controlling the transmission of fault information.

例えば、伝送路17.26側に障害が発生した場合、制
御部30は切換部22を制御して、逓倍器25を介した
クロックを送信部23に加えるように切換える。それに
よって、健全な伝送路16側の一方の送受信部10の受
信部11で抽出したクロックが分周器14で1 / n
に分周され、低速クロックとして転送線18により他方
の送受信部20に転送され、この低速クロックは他方の
送受信部20の逓倍器25によりn逓倍されて元の速度
のクロックとなり、切換部22を介して送信部23に送
信クロックとして加えられ、この送信クロックに従って
障害情報等が伝送路27に送出される。
For example, if a failure occurs on the transmission line 17.26 side, the control unit 30 controls the switching unit 22 to switch so that the clock via the multiplier 25 is applied to the transmitting unit 23. As a result, the clock extracted by the receiving section 11 of one of the transmitting/receiving sections 10 on the healthy transmission line 16 side is divided into 1/n by the frequency divider 14.
The low-speed clock is transferred to the other transmitter/receiver 20 via the transfer line 18 as a low-speed clock, and this low-speed clock is multiplied by n by the multiplier 25 of the other transmitter/receiver 20 to become the clock at the original speed. It is added as a transmission clock to the transmitter 23 via the transmission clock, and fault information etc. are sent to the transmission path 27 in accordance with this transmission clock.

又伝送路16.27側に障害が発生した場合も前述と同
様に、制御部30は切換部12を制御して、逓倍器15
を介したクロックを送信部13に加えるように切換える
。それによって、他方の送受信部20の受信部21で伝
送路26を介した受信信号から抽出したクロックが分周
器24で1/nに分周され、低速クロックとして転送線
28により一方の送受信部10に転送され、この低速ク
ロックは逓倍器15によりn逓倍されて元の速度の送信
クロックとなり、切換部12を介して送信部13に送信
クロックとして加えられ、この送信クロックに従って障
害情報等が伝送路17に送出される。
Also, if a failure occurs on the transmission line 16 or 27 side, the control unit 30 controls the switching unit 12 to switch the multiplier 15
The clock is switched to be applied to the transmitter 13 via the transmitter 13. As a result, the clock extracted from the received signal via the transmission line 26 by the receiving unit 21 of the other transmitting/receiving unit 20 is frequency-divided by 1/n by the frequency divider 24, and is transferred to the one transmitting/receiving unit as a low-speed clock by the transfer line 28. This low-speed clock is multiplied by n by the multiplier 15 to become the original speed transmission clock, which is added as a transmission clock to the transmission section 13 via the switching section 12, and fault information etc. is transmitted according to this transmission clock. 17.

伝送路の障害時に、一方の送受信部から他方の送受信部
へ転送される□クロックは、分周器14゜24により1
/nに分周された低速クロックであるから、転送線18
.28は同軸線を用いることが可能となり、又そのコネ
クタは廉価なSPコネクタ等を用いることが可能となる
。例えば、光伝送システムに於ける送信クロックが1.
6 G Hzの場合、n=4とすると、分周器14.2
4により1/4に分周されて400MHzのクロックと
なるから、1.6 G Hzのクロックをそのまま転送
する場合に比較して、実装が簡単となり、廉価な構成と
なる。
When there is a failure in the transmission path, the □clock transferred from one transmitter/receiver to the other transmitter/receiver is
Since it is a low-speed clock whose frequency is divided by /n, the transfer line 18
.. 28 can use a coaxial line, and its connector can be an inexpensive SP connector or the like. For example, in an optical transmission system, the transmission clock is 1.
For 6 GHz, if n=4, the frequency divider 14.2
Since the frequency is divided by 1/4 by 4 to obtain a 400 MHz clock, the implementation becomes simpler and cheaper than when the 1.6 GHz clock is directly transferred.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、伝送路の障害時に、中
間中継器3では、健全な伝送路を介して受信部11.2
1で受信した信号から抽出したクロックを、分周器14
.24等の分周手段7により1/nに分周して低速クロ
ックとし、その、低速クロックを送信部13.23側へ
転送するものであり、転送線18.28は低速クロック
の転送を行うものであるから、同軸線等を使用すること
が可能となり、高速クロックを転送する場合に比較して
実装構成が簡単となる共に、廉価なコネクタ等を使用す
ることが可能となる。又低速クロックを転送するもので
あるから、クロック波形の歪を生じることが少なく、送
信部13.23に於ける動作に悪影響を及ぼすことがな
い利点がある。
As explained above, in the present invention, when there is a failure in the transmission path, the intermediate repeater 3 connects the receiving units 11.2 to 11.2 through the healthy transmission path.
1, the clock extracted from the signal received at frequency divider 14
.. The low-speed clock is divided by 1/n by frequency dividing means 7 such as 24, and the low-speed clock is transferred to the transmitter 13.23 side, and the transfer line 18.28 transfers the low-speed clock. This makes it possible to use coaxial lines, etc., which simplifies the mounting structure compared to the case of transferring high-speed clocks, and allows the use of inexpensive connectors. Furthermore, since a low-speed clock is transferred, distortion of the clock waveform is less likely to occur, and there is an advantage that there is no adverse effect on the operation of the transmitting section 13, 23.

又送信部13.23は、逓倍器15.25等の逓倍手段
8により低速クロックをn逓倍した送信クロックが加え
られるから、通常の送信クロックと同じ速度となり、障
害情報等を健全な伝送路側へ送出することができる。
In addition, since the transmitting unit 13.23 receives a transmitting clock obtained by multiplying the low-speed clock by n by the multiplier 8 such as the multiplier 15.25, it has the same speed as the normal transmitting clock and transmits fault information etc. to the healthy transmission line side. Can be sent.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理ブロック図、第2図は本発明の実
施例のブロック図、第3図は従来例のブロック図である
。 1.2は端局、3は中間中継局、4は送受信部、5は受
信部、6は送信部、7は分周手段、8は逓倍手段、10
.20は送受信部、11.21は受信部、12.22は
切換部、13.23は送信部、14.24は分周器、1
5.25は逓倍器、16.1?、26.27は伝送路、
18.28は転送線である。
FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional example. 1.2 is a terminal station, 3 is an intermediate relay station, 4 is a transmitting/receiving section, 5 is a receiving section, 6 is a transmitting section, 7 is a frequency dividing means, 8 is a multiplying means, 10
.. 20 is a transmitting/receiving section, 11.21 is a receiving section, 12.22 is a switching section, 13.23 is a transmitting section, 14.24 is a frequency divider, 1
5.25 is a multiplier, 16.1? , 26.27 is the transmission line,
18.28 is a transfer line.

Claims (1)

【特許請求の範囲】 端局(1、2)間の伝送路に複数の中間中継局(3)が
設けられ、前記伝送路の障害時に、障害個所に隣接する
中間中継局に於いて該障害個所と逆方向の健全な伝送路
側からの受信信号からクロックを抽出し、該クロックを
健全な伝送路側へ情報を送出する為の送信クロックとし
て転送するクロックリターン制御方式に於いて、 前記中間中継局(3)の一方の送受信部(4)の受信部
(5)で抽出したクロックを1/nに分周する分周手段
(7)と、他方の送受信部(4)の送信部(6)へn逓
倍したクロックを加える逓倍手段(8)とを設け、 クロックリターン時に前記受信部(5)で抽出したクロ
ックを前記分周手段(7)により1/nに分周した低速
クロックを前記他方の送受信部へ転送し、該低速クロッ
クを前記逓倍手段(8)によりn逓倍して前記送信部(
6)の送信クロックとして加えること を特徴とするクロックリターン制御方式。
[Claims] A plurality of intermediate relay stations (3) are provided on the transmission path between the terminal stations (1, 2), and when a failure occurs in the transmission path, the failure occurs at an intermediate relay station adjacent to the failure point. In the clock return control method, a clock is extracted from a received signal from a healthy transmission line side in the opposite direction to the intermediate relay station, and the clock is transferred as a transmission clock for sending information to the healthy transmission line side. Frequency dividing means (7) for frequency dividing the clock extracted by the receiving section (5) of one transmitting/receiving section (4) to 1/n in (3), and a transmitting section (6) of the other transmitting/receiving section (4) and a multiplier (8) for adding a clock multiplied by n to the other clock, and when the clock returns, the low-speed clock obtained by dividing the clock extracted by the receiving section (5) to 1/n by the frequency dividing means (7) is provided. The low-speed clock is multiplied by n by the multiplier means (8) and transmitted to the transmitter/receiver section (8).
6) A clock return control method characterized in that it is added as a transmission clock.
JP60082263A 1985-04-19 1985-04-19 Clock return control system Pending JPS61242139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60082263A JPS61242139A (en) 1985-04-19 1985-04-19 Clock return control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60082263A JPS61242139A (en) 1985-04-19 1985-04-19 Clock return control system

Publications (1)

Publication Number Publication Date
JPS61242139A true JPS61242139A (en) 1986-10-28

Family

ID=13769579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60082263A Pending JPS61242139A (en) 1985-04-19 1985-04-19 Clock return control system

Country Status (1)

Country Link
JP (1) JPS61242139A (en)

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