JPS61242030A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS61242030A JPS61242030A JP60085014A JP8501485A JPS61242030A JP S61242030 A JPS61242030 A JP S61242030A JP 60085014 A JP60085014 A JP 60085014A JP 8501485 A JP8501485 A JP 8501485A JP S61242030 A JPS61242030 A JP S61242030A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- semiconductor element
- ceramic substrate
- semiconductor device
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15162—Top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高周波用半導体素子等をセラミック基板上に装
着した半導体装置及びその製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a high frequency semiconductor element or the like is mounted on a ceramic substrate, and a method for manufacturing the same.
一般にこの種の半導体装置は９図に示す如く円柱形のセ
ラミック基板５１の表面及び側面にわたってバターニン
グされた電極５２ａ、 ５２ｂ、 ５２ｃ、 ５２ｄを
形成し、セラミック基板５１の側面に位置する各電極５
２ａ、 ５２ｂ、 ５２ｃ、 ５２ｄの端部にＬ型をな
す外部リード板５５ａ、５５ｂ、５５ｃ、５５ｄを銀ろ
う等を用いて接続し、またセラミック基板５１の上面中
央には半導体素子５３を装着し、前記電極５２ａ、５２
ｂ、５２ｃ、５２ｄと接続すると共に図示しないセラミ
ック製のキャンプ５６を被着して構成される。Generally, in this type of semiconductor device, as shown in FIG. 9, patterned electrodes 52a, 52b, 52c, and 52d are formed over the surface and side surfaces of a cylindrical ceramic substrate 51, and each electrode 5 is located on the side surface of the ceramic substrate 51.
L-shaped external lead plates 55a, 55b, 55c, and 55d are connected to the ends of 2a, 52b, 52c, and 52d using silver solder or the like, and a semiconductor element 53 is mounted at the center of the top surface of the ceramic substrate 51. , the electrodes 52a, 52
b, 52c, and 52d, and a ceramic camp 56 (not shown) is attached thereto.
そしてこのような半導体装置の製造は、先ず必要な形状
、例えば円柱状にセラミック基板５１を図示しないセラ
ミックシートから切出し、このセラミ７り基板５１の表
面及び側面にわたるよう複数の電極５２ａ、５２ｂ、５
２ｃ、５２ｄを付着形成した後、第１０図に示す如きリ
ードフレーム５０の外部リード板５５ａ。To manufacture such a semiconductor device, first, a ceramic substrate 51 is cut into a required shape, for example, a columnar shape, from a ceramic sheet (not shown), and a plurality of electrodes 52a, 52b, 5 are cut out from the ceramic sheet so as to cover the surface and side surfaces of the ceramic substrate 51.
2c and 52d, the outer lead plate 55a of the lead frame 50 as shown in FIG.
５５ｂ、５５ｃ、５５ｄの先端部間に装着する。リード
フレーム５０は打抜きによって４本の外部リード板５５
ａ。It is attached between the tips of 55b, 55c, and 55d. The lead frame 50 has four external lead plates 55 formed by punching.
a.
５５ｂ、 ５５ｃ、 ５５ｄが空域５８の四隅から中央
部に向けて延在するよう形成されており、四本の外部リ
ード板５５ａ、５５ｂ、５５ｃ、５５ｄ夫々の先端をセ
ラミック基板５１の側面に位置する各電極５２ａ、５２
ｂ、５２ｃ、５２ｄと接合させた状態でろう付けした後
、セラミック基板５１表面に半導体素子５３を装着し、
半導体素子５３と各電極とを接続しくボンディング工程
）、更にその表面にキャップ５６を被せ（キャンピング
工程）、組立を終了するとリードフレーム５０から外部
リード板５５ａ、５５ｂ、５５ｃ、５５ｄを切断して半
導体装置を切り離し、第１１図に示す如く各外部リード
板５５ａ 、 ５５ｂ、 ５５ｃ、 ５５ｄをクリップ
５７ａ、 ５７ｂ、 ５７ｃ、 ５７ｄで挟み、測定器
５７にて半導体装置の接続の存否、或いは特性を測定し
く計測工程）で製造されている。55b, 55c, and 55d are formed to extend from the four corners of the air space 58 toward the center, and the tips of the four external lead plates 55a, 55b, 55c, and 55d are located on the side surface of the ceramic substrate 51. Each electrode 52a, 52
b, 52c, and 52d are brazed together, and then the semiconductor element 53 is mounted on the surface of the ceramic substrate 51.
The semiconductor element 53 and each electrode are connected (bonding process), and the surface thereof is covered with a cap 56 (camping process). When the assembly is completed, the external lead plates 55a, 55b, 55c, and 55d are cut from the lead frame 50 to form the semiconductor. The device is separated, and the external lead plates 55a, 55b, 55c, and 55d are held between clips 57a, 57b, 57c, and 57d as shown in FIG. (measurement process).
ところで上述した如き従来の半導体装置及びその製造方
法にあっては、セラミックシートの各セラミック基板を
構成する領域の表面にはプリント等の手段で電極を形成
するが、側面に対してはセラミックシートを各セラミッ
ク基板毎に分割した後にメッキ等の手段で付着形成して
おり、作業性が低く、また形成したセラミック基板はリ
ードフレーム５０に固着し、リードフレーム５０に固着
した状態で半導体素子の装着、ボンディング工程、キャ
ンピング工程を行うが、リードフレーム５０自体その面
積が比較的大きいために、半導体装置全体としての固有
面積も大きく、必然的に送りのストロークも大となり、
処理速度の向上に限界がある。By the way, in the conventional semiconductor device and its manufacturing method as described above, electrodes are formed on the surface of the region constituting each ceramic substrate of the ceramic sheet by means such as printing, but the electrodes are formed on the side surface of the ceramic sheet. Each ceramic substrate is divided and then adhered by means such as plating, which has low workability.Furthermore, the formed ceramic substrate is fixed to the lead frame 50, and while it is fixed to the lead frame 50, semiconductor elements are not mounted. The bonding process and the camping process are performed, but since the area of the lead frame 50 itself is relatively large, the specific area of the semiconductor device as a whole is also large, and the feeding stroke is inevitably large.
There are limits to improving processing speed.
またリードフレーム等にはそりが発生し易く、位置ずれ
等による誤動作を招くおそれがあり、更に計測工程に先
立って、各半導体装置を分離する必要があるが、分離後
の取扱いは煩わしく、測定用具等の治具への装着は自動
化が雛しく手作業に依らざるを得ないがハンドリングミ
スによって人体の静電気等で半導体素子を破壊すること
がまま生じ、製品のコストアップを免れ得ないという問
題があった。In addition, lead frames are prone to warping, which can lead to malfunctions due to misalignment, etc.Furthermore, each semiconductor device must be separated prior to the measurement process, but handling after separation is cumbersome, and measurement tools are difficult to handle. The mounting on jigs such as these is highly automated and must be done manually, but there is a problem in that handling errors can cause the semiconductor elements to be destroyed by static electricity from the human body, which inevitably increases the cost of the product. there were.
本発明はかかる事情に鑑みなされたものであって、その
目的とするところはセラミックシートに定めたセラミッ
ク基板とすべき領域に沿って複数の方形、又は円形の打
抜孔を形成し、この打抜孔の周面を経て領域の表、裏両
面にわたって複数本の電極を付着形成し、また半導体素
子を装着し、これと電極とを接続し、更にその特性等の
計測を行った後、セラミックシートを分割して組立てら
れた状態の半導体装置を得られるようにし、外部リード
板の装着が不必要で、大幅な工程の省略が図れ、そのう
え製造過程での取扱いも容易となり、生産能率が高く製
品のコストダウンも図れるようにした半導体装置及びそ
の製造方法を提供するにある。The present invention has been made in view of the above circumstances, and its purpose is to form a plurality of rectangular or circular punched holes along a region defined in a ceramic sheet that is to be a ceramic substrate, and to form a plurality of square or circular punched holes. After forming multiple electrodes on both the front and back sides of the area through the circumferential surface of the area, attaching a semiconductor element, connecting this to the electrodes, and measuring its characteristics, etc., the ceramic sheet is By making it possible to obtain a semiconductor device that is assembled in parts, there is no need to attach an external lead plate, and a large number of steps can be omitted.In addition, handling in the manufacturing process is easy, and the production efficiency is high, resulting in improved product quality. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can reduce costs.
本発明に係る半導体装置はセラミック基板の側面を経て
、表、裏両面にわたるよう１又は複数本の電極を付着形
成し、前記表面又は裏面に半導体素子を装着し、該半導
体素子と前記１又は複数の電極とを金属線にて接続した
ことを特徴とする。In the semiconductor device according to the present invention, one or more electrodes are formed on the side surface of a ceramic substrate so as to cover both the front and back surfaces, a semiconductor element is attached to the front or back surface, and the semiconductor element and the one or more electrodes are attached to the front and back sides of the ceramic substrate. It is characterized in that it is connected to the electrode by a metal wire.
以下本発明をその実施例を示す図面に基づき具体的に説
明する。第１図は本発明に係る半導体装ｔ（以下本発明
装置という）をマイクロストリップ線路に固定した状態
を示す断面構造図、第２図はキャップを外した半導体装
置の表面側からみた斜視図、第３図は同じく裏面側から
みた斜視図であり、図中１はセラミック基板、２ａ、２
ｂ、２ｃ、２ｄは電極、３は半導体素子、４ａ＋４ｂ、
４ｃは金属細線、５はキャップ、６はマイクロストリッ
プ線路を示している。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof. FIG. 1 is a cross-sectional structural diagram showing a state in which a semiconductor device t according to the present invention (hereinafter referred to as the device of the present invention) is fixed to a microstrip line, and FIG. 2 is a perspective view of the semiconductor device seen from the front side with the cap removed. FIG. 3 is a perspective view similarly seen from the back side, in which 1 is a ceramic substrate, 2a, 2
b, 2c, 2d are electrodes, 3 is a semiconductor element, 4a+4b,
4c is a thin metal wire, 5 is a cap, and 6 is a microstrip line.
セラミック基板ｌは８角形の板状に形成され、その１つ
おきの辺と対応する側面及びこの側面に連なる表面１ａ
、裏面１ｂの各一部にわたって４本の電極２ａ、２ｂ、
２ｃ、２ｄがプリントメッキ等の手段で付着形成されて
いる。電極２ａ＋２ｂ、２ｃ、２ｄは第２．３図に示す
如くいずれもセラミック基板１の側面においてはその全
面にわたるよう形成され、また、表面１ａ、表面１ｂに
おいては夫々表面１ａ、表面１ｂの中央部に向けて夫々
舌状に延在させであるが、特に電極２ａは表面１ａにお
いてはその中央部に迄延在させてその先端は半導体素子
３を装着すべく若干面積を広く形成しである。なお、こ
の電極の本数は装着すべき半導体素子３の構造によって
適宜設定されることは勿論である。The ceramic substrate l is formed into an octagonal plate shape, and has a side surface corresponding to every other side and a surface 1a continuous to this side surface.
, four electrodes 2a, 2b over each part of the back surface 1b,
2c and 2d are attached and formed by means such as print plating. As shown in FIG. 2.3, the electrodes 2a+2b, 2c, and 2d are all formed on the side surface of the ceramic substrate 1 so as to cover the entire surface thereof, and on the surfaces 1a and 1b, they are formed in the center of the surfaces 1a and 1b, respectively. In particular, the electrode 2a extends to the center on the surface 1a, and its tip is formed with a slightly wider area so that the semiconductor element 3 can be mounted thereon. It goes without saying that the number of electrodes is appropriately set depending on the structure of the semiconductor element 3 to be mounted.
半導体素子３は下面に１の電極との接続部を備えており
、セラミック基板１０表面側に位置する電極２ａの端部
にろう付は等にて接着することにより、電極２ａと接続
され、また電極２ｂ、２ｃとは金属細線４ ａ ＋ ４
ｂにて接続されている。The semiconductor element 3 has a connection part with the electrode 1 on the lower surface, and is connected to the electrode 2a by adhering to the end of the electrode 2a located on the surface side of the ceramic substrate 10 by brazing or the like. Electrodes 2b and 2c are thin metal wires 4a + 4
It is connected at b.
キャンプ５はセラミック製であって、中央部を凹ませて
形成してあり、半導体素子３、金属細線４ａ、４ｂを覆
うようセラミック基板１の表面１ａに接着剤にて固定さ
れている。The camp 5 is made of ceramic, has a recessed center portion, and is fixed to the surface 1a of the ceramic substrate 1 with an adhesive so as to cover the semiconductor element 3 and the thin metal wires 4a and 4b.
このようにして組立てられた半導体装置は例えばストリ
ップ線路６等に対して、セラミック基板１の裏面に位置
する電極２ａ、２ｂ、２ｃ、２ｄの端部を半ば金属７．
７にて直接接続され、従来における如き外部リード板は
全く不要となる。In the semiconductor device assembled in this way, the ends of the electrodes 2a, 2b, 2c, and 2d located on the back surface of the ceramic substrate 1 are partially connected to the strip line 6, etc. by a metal 7.
7, and there is no need for an external lead plate as in the past.
次に上述した如き本発明装置の製造方法（以下本発明方
法という）について第４図〜７図に基づき説明する。第
４図はセラミックシートＩＯの平面図であり、１１ばセ
ラミック基板１に形成すべき領域、１２は打抜孔を示し
ている。打抜孔１２は四角形状であってその対角線方向
が一直線上に位置するようにして縦、横に一定間隔で形
成されており、相隣する４個の打抜孔１２の頂点を結ぶ
破線で示す領域１１がセラミック基板１に形成される部
分であり、破線に沿ってグイシングすることにより８角
形のセラミック基板１に形成される。セラミックシート
１０に対する打抜孔１２の形成はセラミックシート形成
時でもよいし、またセラミックシート１０の形成後適宜
の治具を用いて行ってもよい。Next, a method of manufacturing the device of the present invention as described above (hereinafter referred to as the method of the present invention) will be explained based on FIGS. 4 to 7. FIG. 4 is a plan view of the ceramic sheet IO, in which reference numeral 11 indicates a region to be formed on the ceramic substrate 1, and 12 indicates a punched hole. The punched holes 12 have a rectangular shape and are formed at regular intervals both vertically and horizontally so that the diagonal lines of the punched holes 12 are aligned in a straight line. Reference numeral 11 denotes a portion to be formed on the ceramic substrate 1, and the octagonal ceramic substrate 1 is formed by guising along the broken line. The punched holes 12 in the ceramic sheet 10 may be formed during the formation of the ceramic sheet, or may be formed after the formation of the ceramic sheet 10 using an appropriate jig.
セラミック基板ｌの形状については特に上述した如き８
角形状に限るものではなく、例えば第５図（イ）に示す
如く打抜孔１２を四角形とする代わりに円形とすると第
５図は（ロ）に示す如く四角形の四隅部を円弧状に切欠
いたセラミック基板１が得られる。また第５図（ロ）、
（ハ）に示す如く、打抜孔を破線で示す基盤目状の交叉
点の１つおきに四角形又は円形に形成すれば夫々６角形
状、或いは四角形の対角線上の２隅部を円形に切除した
状態のセラミック基板１が夫々得られることとなる。こ
れらの形状は必要に応じて選択すればよい。Regarding the shape of the ceramic substrate l, in particular, as mentioned above,
The punching hole 12 is not limited to a rectangular shape, but for example, if the punched hole 12 is made circular instead of square as shown in FIG. A ceramic substrate 1 is obtained. Also, Figure 5 (b),
As shown in (c), if punched holes are formed in a square or circular shape at every other intersection point of the base grid shown by the broken line, a hexagonal shape is obtained, or two diagonal corners of the square are cut out in a circular shape. Ceramic substrates 1 in the respective states are obtained. These shapes may be selected as necessary.
第４図に示す如き打抜孔１２を形成したセラミックシー
ト１０ｔ−得た後、このセラミックシート１０のセラミ
ック基板１とすべき領域１１に対し第７．８図に示す如
く電極２ａ、 ２ｂ、 ２ｃ、 ２ｄの形成を行う。電
極２ａ＋２ｂ、２ｃ、２ｄの形成はセラミックシートＩ
Ｏの表面１ａ、裏面１ｂに対しては主としてプリントに
よって、また打抜孔１２の周面に対しては主としてメッ
キ（スルーホールメッキ法）によって行われる。After obtaining a ceramic sheet 10t having punched holes 12 as shown in FIG. 4, electrodes 2a, 2b, 2c, as shown in FIG. 2d is formed. The electrodes 2a+2b, 2c, 2d are formed using ceramic sheet I.
The front surface 1a and back surface 1b of O are mainly printed, and the peripheral surface of the punched hole 12 is mainly plated (through-hole plating method).
即ち、先ず第６図（イ）、（ロ）に示す如くセラミック
シート１０の表面１ａ： 裏面１ｂに対しプリントによ
ってＡｕ等を素材とする電極を形成し、次いでスルーホ
ールメッキ法にて、打抜孔１２の周面の全面にわたして
メッキを施し、表面１ａ＋裏面１ｂに形成した電極部分
と接続する。これによって、各打抜孔１２から延在する
電極は打抜孔１２の周面に対するメッキにより相互に接
続状態となる。That is, first, as shown in FIGS. 6(a) and 6(b), electrodes made of Au or the like are formed on the front surface 1a and back surface 1b of the ceramic sheet 10 by printing, and then punched holes are formed by through-hole plating. Plating is applied to the entire circumferential surface of 12 and connected to the electrode portions formed on the front surface 1a and the back surface 1b. As a result, the electrodes extending from each punched hole 12 are connected to each other by plating the circumferential surface of the punched hole 12.
電極２ａ、２ｂ、２ｃ、２ｄの形成が終了すると、セラ
ミックシート１０の表面１ａにおける各領域１１におけ
る電極２ａの端部に半導体素子３を装着し、次いでボン
ディング工程に入って半導体素子３と各電極２ｂ。When the formation of the electrodes 2a, 2b, 2c, and 2d is completed, the semiconductor element 3 is attached to the end of the electrode 2a in each region 11 on the surface 1a of the ceramic sheet 10, and then a bonding process is performed to bond the semiconductor element 3 and each electrode. 2b.
ｄとを金属細線４ａ、４ｂにて接続する。ボンディング
工程が終了するとキャンピング工程に入り、セラミック
製のキャップ５を半導体素子３及び金属細線４ａ、４ｂ
を覆うように被せて接着剤にて接着し、組立工程を終了
する。d with thin metal wires 4a and 4b. After the bonding process is completed, a camping process begins, in which the ceramic cap 5 is attached to the semiconductor element 3 and the thin metal wires 4a, 4b.
Cover it and adhere it with adhesive to complete the assembly process.
各半導体装置の組立が終了したセラミックシーＨＯは計
測工程に移され、各半導体素子３と電極２ａ〜２ｄとの
接続状態を検査し、或いはその他特性を知るため第７図
に示す如き態様で計測が行われる。The ceramic sea HO after the assembly of each semiconductor device is moved to the measurement process, and measurement is performed in the manner shown in FIG. 7 in order to inspect the connection state between each semiconductor element 3 and the electrodes 2a to 2d, or to find out other characteristics. will be held.
第７図は計測態様を示す模式図であり、図示しない計測
器本体と連なる板状治具２１における中央の孔２１ａを
通してリード線２２ａ、 ２２ｂ、 ２２ｃ、 ２２ｄ
をセラミックシート１０の裏面に位置する各領域１１毎
の電極２ａ、２ｂ、２ｃ、２ｄに接続して行う。各半導
体装置について個々に、また複数個ずつ同時的に測定を
行い、計測が終了すると、破線で示した如き各領域１１
に沿うようセラミックシート１０を分割し、第１図に示
した如き半導体装置を得ることとなる。FIG. 7 is a schematic diagram showing a measurement mode, in which lead wires 22a, 22b, 22c, 22d are passed through a central hole 21a in a plate-like jig 21 connected to a measuring instrument main body (not shown).
This is performed by connecting the electrodes 2a, 2b, 2c, and 2d of each region 11 located on the back surface of the ceramic sheet 10. Each semiconductor device is measured individually or simultaneously, and when the measurement is completed, each area 11 as shown by the broken line
The ceramic sheet 10 is divided along the lines to obtain a semiconductor device as shown in FIG.
第８図（イ）、（ロ）は本発明方法における電極パター
ンの他の例を示すセラミックシートの表面、裏面図であ
り、セラミックシート１０に対する打抜孔１２の形成態
様は、前述した第４図に示す場合と同じである。FIGS. 8(A) and 8(B) are front and back views of a ceramic sheet showing other examples of electrode patterns in the method of the present invention, and the manner in which punched holes 12 are formed in the ceramic sheet 10 is shown in FIG. This is the same as the case shown in .
そして電極は前記した場合と同様にセラミックシーＨＯ
の表面１ａ、裏面１ｂに対してはプリントにより形成す
るが、表面１ａに対しては第８図（イ）に示す如く、セ
ラミックシート１０の一側縁にＸ字形にメッキ用電極部
２１ｍを形成し、また相隣する４個の打抜孔１２で囲わ
れる領域のうち、横方向及び縦方向に対し、セラミック
基板１とすべ（電極２ａ＋ ２ｂ＋ ２ｃ、 ２ｄを形
成した領域１１ｒと、メッキ用の電極２ｎを形成した領
域１１ｂとを交互に形成し、更に打抜孔１２の３行目と
４行目毎、換言すれば領域の３行目毎に電極を形成しな
い無電極の領域１１ｃを設けである。領域１１ａの電極
２ａ、２ｂ、２ｃ、２ｄは第６図（イ）、（ロ）に示す
のと同じであり、また領域１１ｂにおけるメッキ用の電
極２ｎは領域１１ｂに面して位置する打抜孔１２の相対
向する辺間を結ぶようＸ字形に形成されている。The electrodes are ceramic sea HO as in the case described above.
The front side 1a and the back side 1b are formed by printing, and for the front side 1a, an X-shaped plating electrode part 21m is formed on one side edge of the ceramic sheet 10, as shown in FIG. 8(A). In addition, among the areas surrounded by four adjacent punched holes 12, in the horizontal and vertical directions, there is a region 11r where the ceramic substrate 1 and the electrodes (electrodes 2a+ 2b+ 2c, 2d are formed), and an electrode for plating. 2n are formed alternately, and an electrode-free region 11c in which no electrode is formed is provided every third and fourth row of punched holes 12, in other words, every third row of regions. The electrodes 2a, 2b, 2c, and 2d in the region 11a are the same as those shown in FIGS. The punch hole 12 is formed in an X shape so as to connect opposing sides.
一方セラミックシートｌＯの裏面１ｂには前記セラミッ
ク基板ｌとすべき領域１１ａに対応する裏面にのみ電極
２ａ〜２ｄの各一端部を前記第６図（ロ）におけると同
様に形成しである。On the other hand, one end of each of the electrodes 2a to 2d is formed on the back surface 1b of the ceramic sheet 1O, in the same manner as in FIG. 6(b), only on the back surface corresponding to the area 11a to be the ceramic substrate 1.
そして打抜孔１２の周面に対するスルーホールメッキは
前記した如きメッキ用電極２ａ＋、２ｎを利用して次の
如くに行う。即ちセラミ７クシート１０の表面１ａにお
けるメッキ用電極２Ｉ１１にメッキ用の−の電極を接続
し、次いでスルーホール用金属材に他の電極を接続し、
前記メッキ用電極２１１を形成した側からスルーホール
用金属材を順次打抜孔１２に挿入してゆく。メッキ用電
極２ｇ＋、２１１は相互に接続されているから左端側の
打抜孔１２の列にスルーホール用金属材を挿入すると、
メッキ用電極２ｎとスルーホール用金属材との接触によ
って通電され、熔融金属が打抜孔１２の周面に接着せし
められることとなる。セラミックシート１０における左
端側の打抜孔１２の列から順次右側の打抜孔１２にスル
ーホール用金属材を挿入してゆけば、スルーホール用金
属材は常にメッキ用電極２ｎと接触状態となり、通電手
段が容易となる利点を有する。Through-hole plating on the peripheral surface of the punched hole 12 is performed as follows using the plating electrodes 2a+ and 2n as described above. That is, a - electrode for plating is connected to the plating electrode 2I11 on the surface 1a of the ceramic sheet 10, and then another electrode is connected to the metal material for the through hole,
Metal materials for through holes are sequentially inserted into the punched holes 12 from the side on which the plating electrodes 211 are formed. Since the plating electrodes 2g+ and 211 are connected to each other, when the through-hole metal material is inserted into the row of punched holes 12 on the left end side,
Electricity is applied by contact between the plating electrode 2n and the metal material for the through hole, and the molten metal is bonded to the circumferential surface of the punched hole 12. If the metal material for through holes is inserted into the punched holes 12 on the right side in sequence from the row of punched holes 12 on the left end side of the ceramic sheet 10, the metal material for through holes will always be in contact with the plating electrode 2n, and the current supply means This has the advantage that it is easy to
このようにして電極形成工程を終了した後は前述したの
と同様に半導体素子３を装着し、また金属細線４ａ、４
ｂで半導体素子３と電極２ｂ、２ｄとを接続するボンデ
ィング工程、キャンプを被せるキャッピング工程を経て
計測工程に移るが、計測に先立って先ず領域１１ｂにお
けるメッキ用電極２ｎの交叉点部を破線で示す如くに打
抜き、半導体素子相互の接続状態を遮断する＝これによ
り領域１１ａは３行目毎に無電極の領域１１ｃに形成し
ているのと相俟って、相隣する他の半導体素子等の影響
が低減され、正確な特性の測定を行い得る。なお前記メ
ッキ用電極２ｎの交叉点部を打ち懐くことによって半導
体素子相互の接続状態を遮断する代わりにレーザービー
ムを用いてメッキ用電極２ｎを切除することにより遮断
してもよい。After completing the electrode forming process in this manner, the semiconductor element 3 is mounted in the same manner as described above, and the thin metal wires 4a, 4
At step b, the process moves to the measurement process after a bonding process for connecting the semiconductor element 3 and the electrodes 2b and 2d, and a capping process for covering the camp, but prior to the measurement, the intersection of the plating electrodes 2n in the region 11b is indicated by a broken line. As a result, the regions 11a are formed in electrodeless regions 11c every third row, and the connection state between the semiconductor elements is cut off. The influence is reduced and accurate property measurements can be made. Note that instead of breaking the connection between the semiconductor elements by striking the intersection portions of the plating electrodes 2n, the connection between the semiconductor elements may be broken by cutting off the plating electrodes 2n using a laser beam.
計測工程は第７図に示したのと同様にしてセラミックシ
ート１０を裏返しにして、計測用治具と領域１１ａの裏
面における電極とをリード線にて接続して行う。計測工
程終了後ダイシングを行うことにより、前述の場合と同
様に組み立てた状態の半導体装置が得られることとなる
。The measurement step is carried out in the same manner as shown in FIG. 7 by turning the ceramic sheet 10 upside down and connecting the measurement jig and the electrode on the back surface of the region 11a with a lead wire. By performing dicing after the measurement process is completed, a semiconductor device assembled in the same manner as in the above case can be obtained.
以上の如く本案装置及びその製造方法にあっては、セラ
ミックシートを用いて、そのセラミック基板に対する電
極の形成、半導体素子の装着、ポンディング、キャッピ
ングの各２工程を終了した後、セラミックシートを切断
することにより、組み立てられ、計測を終了した状態の
半導体装置が直ちに得られることとなり、全工程をセラ
ミックシートの状態データ扱い得て作業能率が高く、工
程の大幅な省略が可能となり、量産化に通し、製品のコ
ストダウンが図れるなど本発明は優れた効果を奏するも
のである。As described above, in the present device and its manufacturing method, a ceramic sheet is used, and after completing each of the two steps of forming electrodes on the ceramic substrate, mounting semiconductor elements, bonding, and capping, the ceramic sheet is cut. By doing so, the assembled and measured semiconductor device can be obtained immediately, and the entire process can be handled using the state data of the ceramic sheet, increasing work efficiency and making it possible to significantly omit processes, making it easier for mass production. As a result, the present invention has excellent effects such as reducing the cost of the product.
第１図は本発明装置の断面構造図、第２図はセラミンク
基板を上面側からみた側面図、第３図は同じく下面側か
らみた斜視図、第４図はセラミックシートの平面図、第
５図（イ）、（ロ）、（ハ）はセラミックシート別の態
様を示す平面図、第６図（イ）、（ロ）はセラミックシ
ートに電極を形成した態様を示す表、裏面図、第７図は
計測工程の態様を示す部分斜視図、第８図（イ）、（ロ
）はセラミックシートに形成した電極パターンの別の態
様を示す平面図、第９図は従来装置の断面構造図、第１
０図は従来装置の製造過程を示す平面図、第１１図は同
じ〈従来装置に対する計測工程を示す模式図である。
１・・・セラミック基板 ２ａ、 ２ｂ、 ２ｃ、 ２
ｄ・・・電極３・・・半導体素子 ４ａ、４ｂ・・・金
属細線 ５・・・キャップ ６・・・マイクロストリッ
プ線路 ７・・・半田用金Ｍ １０・・・セラミック
シート１１・・・領域１２・・・打抜孔２１ ・・・計
測器具 ２１ａ 一孔 ２２ａ、 ２２ｂ、 ２２ｃ、
２２ｄ・・・リード線
特 許 出 願 人 三洋電機株式会社代理人 弁理
士 河 野 登 夫ｂｔ
尋 ４ 図
Ｉｔ）
算 ５ 図
弊 ６ 図
／Ｉ
ろ
ｚ
／、
々
卑 Ｇ 図
算 ＋７ 図
？
＄ ｑ 図
算 ＋０ ５！２
ｊＪ ＋＋ 図
手続補正ＩＦ（自発）
昭和６０年１０月２５日
昭和６０年特許願第８５０１４号
２、発明の名称
半導体装置及びその製造方法
３、補正をする者
事件との関係 特許出願人
所在地 守口市京阪本通２丁目１８番地名 称 （１８
８）三洋電機株式会社
代表者 井Ｎ 薫
４、代理人 〒５４３
住 所 大阪市天王寺区四天王寺１丁目１４番２２号
日進ビル２０７号
河野特許事務所（電話０６−７７９−３０８８ ）明Ｉ
［書の「発明の詳細な説明」の欄
Ｃ： ＩＪ：′：′Ｌ：ｍ＋±１ゲζ（１）
明細書の第１３頁１４行目乃至１５５行目「電極を接続
し、前記・−・打抜孔１２に挿入」とあるを、「電極を
接続し、スルーホール用金属材を打抜孔１２に挿入」と
訂正する。
（２）明細書の第１３頁１７行目に「左端側の打抜孔１
２」とあるを、「打抜孔１２Ｊと訂正する。
（４） 明ｍ沓の第１４頁１行目乃至５行目に「セラ
ミックシートＩＯにおける・・・容易となる利点を有す
る。」とあるを抹消する。
以上Fig. 1 is a cross-sectional structural diagram of the device of the present invention, Fig. 2 is a side view of the ceramic substrate seen from the top side, Fig. 3 is a perspective view similarly seen from the bottom side, Fig. 4 is a plan view of the ceramic sheet, and Fig. 5 is a top view of the ceramic sheet. Figures (a), (b), and (c) are plan views showing different aspects of the ceramic sheet, and Figures (a) and (b) are front, back, and side views showing the aspect of electrodes formed on the ceramic sheet. Figure 7 is a partial perspective view showing an aspect of the measurement process, Figures 8 (a) and (b) are plan views showing another aspect of the electrode pattern formed on the ceramic sheet, and Figure 9 is a cross-sectional structural diagram of the conventional device. , 1st
FIG. 0 is a plan view showing the manufacturing process of the conventional device, and FIG. 11 is a schematic diagram showing the measurement process for the same conventional device. 1...Ceramic substrate 2a, 2b, 2c, 2
d... Electrode 3... Semiconductor element 4a, 4b... Metal thin wire 5... Cap 6... Microstrip line 7... Soldering gold M 10... Ceramic sheet 11... Area 12...Punching hole 21...Measuring instrument 21a One hole 22a, 22b, 22c,
22d...Lead wire patent Applicant Sanyo Electric Co., Ltd. Agent Patent attorney Noboru Kono bt Hiro 4 Fig. It) Calculation 5 Fig. U 6 Fig./I Roz /, Hibi G Fig. +7 Fig.? $ q Diagram calculation +0 5!2 jJ ++ Illustration procedure amendment IF (spontaneous) October 25, 1985 Patent Application No. 85014 of 1985 2, Title of invention semiconductor device and its manufacturing method 3, Person making amendment case Relationship with Patent Applicant Location 2-18 Keihan Hondori, Moriguchi City Name (18
8) Sanyo Electric Co., Ltd. Representative Kaoru IN 4, Agent 543 Address 1-14-22 Shitennoji, Tennoji-ku, Osaka City
Nisshin Building 207 Kono Patent Office (Tel: 06-779-3088) Mei I
[Column C of “Detailed Description of the Invention” in the book: IJ:′:′L:m+±1geζ(1)
On page 13, lines 14 to 155 of the specification, "Connect the electrode and insert it into the punched hole 12" is replaced with "Connect the electrode and insert the metal material for the through hole into the punched hole 12." ” he corrected. (2) On page 13, line 17 of the specification, “Punching hole 1 on the left end side
2" has been corrected to read "punching hole 12J." (4) On page 14, lines 1 to 5 of Ming Yue, it says, "It has the advantage of being easy to use in ceramic sheet IO." Delete. that's all
Claims (1)
よう１又は複数本の電極を付着形成し、前記表面又は裏
面に半導体素子を装着し、該半導体素子と前記１又は複
数の電極とを金属線にて接続したことを特徴とする半導
体装置。 ２、セラミックシートを分割して半導体素子装着用のセ
ラミック基板を得る工程を含む半導体装置の製造方法に
おいて、セラミックシートの分割に先立ってセラミック
基板とすべき領域に沿い複数の打抜孔を穿設し、各打抜
孔夫々の周面を経て前記領域の表、裏両面にわたるよう
複数本の電極を付着形成し、前記領域の表面又は裏面に
半導体素子を装着し、該半導体素子と前記１又は複数の
電極とを金属線にて接続することを特徴とする半導体装
置の製造方法。 ３、前記打抜孔は円形、又は多角形である特許請求の範
囲第２項記載の半導体装置の製造方法。 ４、セラミックシートを分割して半導体素子を装着すべ
きセラミック基板を得る工程を含む半導体装置の製造方
法において、セラミックシートの分割に先立って予め定
めたセラミック基板とすべき領域に沿うよう複数の打抜
孔を穿設し、各打抜孔夫々の周面を経て前記領域の表、
裏両面にわたるよう複数本の電極を付着形成し、前記領
域の表面又は裏面に半導体素子を装着し、これと前記１
又は複数の電極とを金属線にて接続し、各領域における
半導体素子の特性を計測することを特徴とする半導体装
置の製造方法。 ５、前記打抜孔は円形、又は多角形である特許請求の範
囲第４項記載の半導体装置の製造方法。[Claims] 1. One or more electrodes are attached and formed on both the front and back sides of the ceramic substrate, a semiconductor element is mounted on the front or back side, and the semiconductor element and the one or more electrodes are attached to the front and back sides of the ceramic substrate. A semiconductor device characterized in that a plurality of electrodes are connected with a metal wire. 2. In a method for manufacturing a semiconductor device including a step of dividing a ceramic sheet to obtain a ceramic substrate for mounting a semiconductor element, a plurality of punching holes are punched along the area to be used as the ceramic substrate prior to dividing the ceramic sheet. , a plurality of electrodes are adhered and formed so as to cover both the front and back surfaces of the region through the circumferential surface of each punched hole, a semiconductor element is mounted on the front or back surface of the region, and the semiconductor element and the one or more 1. A method of manufacturing a semiconductor device, comprising connecting an electrode with a metal wire. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the punched hole is circular or polygonal. 4. In a semiconductor device manufacturing method that includes a step of dividing a ceramic sheet to obtain a ceramic substrate on which a semiconductor element is to be mounted, a plurality of blows are applied along predetermined areas to be made into a ceramic substrate prior to dividing the ceramic sheet. A punching hole is drilled, and the surface of the area is formed through the circumferential surface of each punching hole.
A plurality of electrodes are adhered and formed so as to cover both surfaces of the back surface, a semiconductor element is attached to the front surface or the back surface of the region, and this and the above 1.
Alternatively, a method for manufacturing a semiconductor device, characterized in that a plurality of electrodes are connected with a metal wire, and characteristics of a semiconductor element in each region are measured. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the punched hole is circular or polygonal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60085014A JPS61242030A (en) | 1985-04-19 | 1985-04-19 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60085014A JPS61242030A (en) | 1985-04-19 | 1985-04-19 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61242030A true JPS61242030A (en) | 1986-10-28 |
Family
ID=13846887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60085014A Pending JPS61242030A (en) | 1985-04-19 | 1985-04-19 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61242030A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5371029A (en) * | 1991-01-22 | 1994-12-06 | National Semiconductor Corporation | Process for making a leadless chip resistor capacitor carrier using thick and thin film printing |
| DE102006005746A1 (en) * | 2006-02-07 | 2007-08-16 | Elbau Elektronik Bauelemente Gmbh Berlin | Arrangement of a component to be electrically contacted, in particular arrangement of a sensor, preferably an MR sensor for position and angle measuring systems |
-
1985
- 1985-04-19 JP JP60085014A patent/JPS61242030A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5371029A (en) * | 1991-01-22 | 1994-12-06 | National Semiconductor Corporation | Process for making a leadless chip resistor capacitor carrier using thick and thin film printing |
| DE102006005746A1 (en) * | 2006-02-07 | 2007-08-16 | Elbau Elektronik Bauelemente Gmbh Berlin | Arrangement of a component to be electrically contacted, in particular arrangement of a sensor, preferably an MR sensor for position and angle measuring systems |
| DE102006005746B4 (en) * | 2006-02-07 | 2009-02-26 | Elbau Elektronik Bauelemente Gmbh Berlin | Electronic assembly, in particular electronic sensor system, preferably for position and angle measuring systems |
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