JPS612362A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration by forming a graft base by an emitter and self-alignment. CONSTITUTION:A p type layer 5 as an intrinsic base is shaped onto the surface of an n type silicon base body 3, and a mask material 7 consisting of an silicon nitride and a mask material layer 8 composed of a photo-resist on the mask material 7 are formed onto the surface of the layer 5. A window opening section larger than a window opening shaped to the mask material 8 is bored to the mask material 7, an impurity is introduced while using the mask material 8 as a mask, an n<+> type layer as an emitter is formed to one part of the surface of the p type layer, the mask material 8 is removed, and a mask material 10 consisting of an organic resin is buried to the window opening section of the mask materials 7. The mask material 7 is removed, and the impurity is introduced deeply to the surface of the p type layer while employing the organic resin as a mask, thus forming a high-concentration p<+> type layer 11 as a graft base.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of manufacturing a high performance graft-based transistor.

[Background technology]

In order to increase the speed of bipolar ICs (bipolar transistors) or to increase the collector polarity of inverse transistors in IIL (implanted integrated logic circuits), it is necessary to use a shallow, low-concentration intrinsic base directly below the emitter, and a deep, high-concentration graft base around the emitter. A structure is known. In this case, it is necessary to have a fine structure that reduces the lateral base resistance rbb'.

FIG. 17 is a cross-sectional view showing an ideal example of a graft-based transistor, in which numeral 3 is a first conductivity type semiconductor substrate, which is an n-type semiconductor substrate serving as a collector, and 9 is an emitter n+ type layer, which is a first conductivity type layer. , 5 is the intrinsic base p which becomes the second conductivity type layer
Base width d in mold layer.

is formed shallowly from the substrate surface, and 11 is a highly doped second conductivity type layer which serves as a graft base and is formed deep from the substrate surface. 16 represents a channel stopper.

In miniaturizing and forming such a graft-based transistor, the lateral width d of the intrinsic base p-type layer is
2 is an important problem in the characteristics of semiconductor devices. It has been found that if d2 is too large, rbb' becomes large and the effect of speeding up is small, and if d is too small or d=o, the emitter base breakdown voltage will drop, which is undesirable.

The results of the inventor's study have revealed that the miniaturization of graft-based transistors requires a self-alignment (self-alignment) technology for base-emitter junctions.

Various manufacturing methods have heretofore been proposed for manufacturing craft base transistors. For example, the applicant of the present application has developed a method of performing high concentration base diffusion using a polysilicon layer formed on an emitter as a stack. In this case, since it is not a self-line, mask alignment of the polysilicon layer with respect to the emitter is required. Furthermore, the Selfaline method includes oxidation and nitride removal methods. This involves performing high-concentration base diffusion using a nitride (SiN) film as a mask, then oxidizing the substrate surface using the silicon nitride film as an oxide film, removing the silicon nitride film, and using the silicon oxide film (,5iO2) on the surface as a mask. This method performs n+ type emitter diffusion. However, it has been found that with this method, the high concentration base layer is brought too close to the emitter junction, resulting in a reduction in breakdown voltage.

In addition, a two-layer film of polysilicon and CV D-8ioh was processed using Reactive Ion Etching (RI
A method of forming a graft pulse transistor using self-line (referred to as E) is also described in VLSI Device Handbook 1983 Edition P6S-71.

In this method, as shown in FIG. 18, a boron-doped polysilicon film 13 and a CVD-8102 film 14 are formed in two layers on the surface of an n-type silicon substrate.
0214 and polysilicon 13 are etched using RIE, and then boron-doped polysilicon 13 is side-etched using a dichloronitric acid-based etching solution. Then the first
As shown in FIG. 9, the surface of the exposed portion of polysilicon 13 is oxidized to form an oxide film 15, and boron is diffused from polysilicon layer 13 into the substrate to form highly doped p-type base 11. After this, the SIO2 on the board surface (not shown) is
Etch using IE to make a hole for the emitter,
Next, emitter n+ type diffusion 9 is performed. 16 indicates a channel stopper.

According to this method, it is possible to construct a graft-based transistor with a self-lined structure, but as with the oxidation and nitride removal methods, it has been found that the high concentration p+ type layer is close to the emitter junction, resulting in a low breakdown voltage.

[Purpose of the invention]

The present invention has solved the above-mentioned problems, and its purpose is to provide a method for manufacturing a graft-based transistor using self-alignment lines, which allows for high integration and has high emitter-base breakdown voltage.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a p-type layer is formed as an intrinsic base for a second conductivity type layer, and a first layer made of silicon/nitride is formed on the surface of this p-type layer. A layer of a second mask material consisting of a mask material and a photoresist is formed on the second mask material, a desired portion of the second mask material is opened, and this is used as a mask to form the first mask material and the second mask material. A window opening larger than that of the first conductivity type layer is opened, and an impurity is introduced using the second mask material as a mask to form an n+ type layer of the first conductivity type layer which will become an emitter on a part of the surface of the p type layer. After removing the second mask material and embedding a third mask material made of organic resin in the window opening of the first mask material, the first mask material is removed and the p-type layer is formed using the organic resin as a mask. This method involves deeply introducing impurities into the surface to form a highly doped p+ type layer, which is a highly doped second conductivity type layer that will serve as a graft base. A transistor can be obtained and the above object can be achieved.

[Embodiment 1] FIGS. 1 to 9 show an embodiment of the present invention, and are process sectional views of an emitter paste portion in a manufacturing process of a high frequency graft base transistor.

Each step will be explained in detail below.

(1) Using normal bipolar IC and isoplanar technology, as shown in FIG. 1, a first conductivity type semiconductor is formed by epitaxial growth by embedding an n+ type buried layer 2 on a p- type silicon substrate (substrate) 1. An n-type silicon layer 3 serving as a base is formed to a thickness of about 1 μm, a recess is made using a silicon nitride film or the like (not shown) as a mask, and selective oxidation is performed to form an isolation oxide film 4. Thereafter, boron (B) is ion-implanted into the surface of the n-type silicon layer 3 and diffused to form a shallow low-concentration p-type (p-type) layer 5 of the second conductivity type layer, which becomes an intrinsic paste. . During this diffusion, 50% of the surface of the p-type layer 5 is
A thin oxide film (S s 02 ) 6 having a thickness of about 0λ is formed. 16 indicates a channel stopper.

(21 As shown in Fig. 2, a silicon nitride film (nitride) 7, which will become the first mask material, is formed to a thickness of 0.5 to 0.7 μm on the entire surface using plasma discharge. A photoresist 8 serving as a second mask material is applied, and a portion of it is opened to form a mask through photo processing.

(3) Open-etch the nitride film 7 through the opened photoresist mask 8. The etching at this time is dry etching without anisotropy, for example, CF4 plasma etching, and the nitride film 7 is etched horizontally from the window opening of the photoresist mask by d=0.5 to 1.0μ.
obtains an overetched window opening.

(4) After this, as shown in FIG. 4, using the photoresist 8 as a mask, As (arsenic) ions are implanted into the p-type layer directly under the window opening, and the first An n+ type emitter diffusion layer 9 which becomes a conductivity type layer is obtained.

The emitter diffusion photoresist mask is removed with a suitable organic solvent.

(5) A polyimide film is applied to the entire surface and solidified by annealing to form a polyimide resin film 10 serving as a third mask material, as shown in FIG. The thickness of the polyimide resin film 10 is set to be sufficient to fill the window opening of the nitride film 7, for example, 0.5 to 07 μm or more.

(6) Plasma etching is performed using oxygen as a reaction gas to etch the surface of the polyimide film 100.
As shown in the figure, the polyimide film 10a inside the window opening is
Leave only.

(7) After this, plasma etching is performed using CF4 as a reactive gas to remove the nitride film 7, leaving only the polyimide portion (10a) as shown in FIG. What should be noted here is that by leaving the polyimide portion 10a, a first mask, that is, a mask having a pattern opposite to the window openings of the nitride film 7 is formed. This provides a semiconductor device with high breakdown voltage.

(8) Ion implanting B (boron) using the polyimide film 10a as a mask, or depositing boron glass 15,
By annealing 1- at 1000°C for 30 minutes, the graft base 11 of the highly doped p+ type layer, which will become the highly doped second conductivity type layer, is deep within the n-fJn layer as shown in FIG.
~0.7 μm).

If the IIL is formed on the same substrate, this ion implantation is performed in synchronization with the formation of the IIL injector.

(9) After this, contact photoetching is performed to make contact holes to expose each region. As for the emitter, as shown in FIG. 9, the 5in2 film 6 on the emitter is removed by the washed emitter method to open an emitter contact. That is, since the 5in2 film 6 on the emitter contains arsenic ions as shown in FIG.
The 5in2 film 6 on the emitter is sufficiently removed by light etching.

Thereafter, aluminum is deposited on the entire surface and patterned and etched to provide aluminum electrodes B, E, and C as shown in FIG. Note that the junction is shallow (0.3μ
m) By using aluminum containing silicon or forming a polysilicon electrode for the emitter part,
Prevents aluminum from sticking through the joint. In FIG. 10, 12 is a high concentration n for the collector contact.
+ type scattering layer CN+ layer).

〔effect〕

According to the present invention described in Example 1 above, the following effects can be obtained.

(1) Since the graft base can be formed of an emitter and a self-line, high integration becomes possible. That is, the lateral width (d2) of the intrinsic base p-type layer 5 is determined by the degree of overetching of plasma nitride, but the processing accuracy of this overetching is highly accurate and can be further freely controlled. can. As described above, microfabrication becomes possible, and therefore high integration can be achieved.

(2) Since the p+ type layer of the graft base cannot come into contact with the emitter n+ type layer, it is possible to increase the emitter-base breakdown voltage.

(3) Due to the above (1), the speed can be increased as a forward direction transistor. Furthermore, the above (2) allows the emitter-base breakdown voltage to be increased as a reverse transistor, making it suitable for application to IIL manufacturing.

[Embodiment 2] FIGS. 11 to 15 show another embodiment of the present invention, and are process sectional views of the craft base portion in the IC manufacturing process.

(1) Using normal bipolar IC and isobrainer technology, as shown in FIG. An isoplanar oxide film 4 is formed on the surface of the n-type layer 3, a p-type layer 5 serving as an intrinsic base is formed, a plasma nitride film 7 is formed on the entire surface, and then a photoresist is coated and exposed and developed to form an intrinsic base. The photoresist 8 is left as a mask by a certain width. 16 indicates a channel stopper.

(2) Using the photoresist mask 8, the nitride film 7 is plasma etched as shown in FIG. At this time, by slightly overetching the side portions of the nitride film 7, a nitride mask 7 that extends inside the pattern of the photoresist mask 8 is obtained.

(3) After this, use photoresist 8 as a mask and
(Boron) Ions are deeply implanted into the surface of the epitaxial layer and annealed to obtain a graft base p+ type layer 11 as shown in FIG. In this case, as in the previous embodiment, the IIL injector is formed simultaneously.

(4) The photoresist 8 is removed, and a polyimide resin face is applied to the entire surface and cured to form a polyimide film 10 as shown in FIG.

(5) Dry etching the surface of the polyimide film 10 to leave the polyimide film 10 surrounding the nitride mask 7 as shown in FIG.

(6) The nitride mask 7 is removed by etching, and As (arsenic) is ion-implanted to form an n++ layer 9 that will become an emitter, as shown in FIG. Thereafter, a contact etching process, an aluminum vapor deposition process, and a patterning etching process are performed to complete a graft-based transistor similar to the previous embodiment.

FIG. 20 shows an example of a semiconductor device formed according to the present invention. In the figure, the same reference numerals as in the above embodiment indicate the same or equivalent parts.

This figure shows a state in which bipolar transistors Q and IILQ2 are formed on the same substrate. What is characteristic in the figure is the pace of the bipolar transistor Q, and the pace of the bipolar transistor Q.
This means that the bases of the inverse transistors LQ, . Since the graft-based p+ type layer 11 of the inverse transistor of IILQ2 and the multi-collector n+ type layer 9 are not in contact with each other, the withstand voltage is high. Further, according to the present invention, the graft-based p+ type layer 11, the emitter n+ type layer 9 of the bipolar transistor Q1, and the multi-collector n+ type layer 9 of the IILQ* are formed by self-alignment, so that high integration can be achieved. The point is that it is miniaturized. Also, IILQ, injector (inj) and graft base
The main feature is that the p+ type layer of the substrate is simultaneously formed as a trap, thereby shortening the process. After this, although not shown, a protective film is formed on the surface of the substrate.

〔effect〕

According to the present invention described in Example 2, the same as in Example 1 (by using an organic resin and using a reverse pattern, the graft base can be formed with an emitter and a self-alignment line; therefore, in Example 1 The same effect as in the case of .

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples (although it is possible to make various changes without departing from the gist of the invention). Not even (ゝ.

For example, the mask material formed on the surface of the semiconductor layer can be changed as follows.

(1) 1st (lower layer) + 7) Mask material KCVD-8
in2. Use polysilicon, etc.

(2) Use photosensitive polyimide for the second layer mask material0 (3) Use photosensitive polyimide for the third layer mask material0 (4) Use polysilicon for the electrode that contacts the emitter. Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to a method of manufacturing a semiconductor device, which is the field of application which is the background of the invention, but the present invention is not limited thereto.

The present invention can be applied to bipolar transistors, bipolar ICs, IIL coexisting linear ICs, bipolar memories, or high-frequency transistors having a graft base structure.

[Brief explanation of the drawing]

FIGS. 1 to 9 show one embodiment of the present invention, and are process sectional views of a semiconductor device manufacturing process. FIG. 10 is a cross-sectional view of a graft-based transistor manufactured by the method of the present invention. FIGS. 11 to 16 show another embodiment of the present invention, and are process sectional views of a semiconductor device manufacturing process. FIG. 17 is a sectional view showing the principle structure of a graft-based transistor. FIGS. 18 to 19 are process cross-sectional views showing examples of conventional processes for graft-based transistors. FIG. 20 shows a cross-sectional view of a semiconductor device formed according to the present invention. 1...p-type silicon substrate (substrate), 2.
... n+ type buried layer, 3... epitaxial n- type silicon layer, 4... isoplanar oxide film, 5... p-type layer serving as an intrinsic paste, 6... oxide film, 7... - First mask material (silicon nitride film), 8... Second mask material (photoresist), 9... Emitter n+ type layer, 10
...Third mask material (polyimide resin), 11...
...p+ type layer serving as a graft base, 12...high concentration n+ diffusion layer, 13...polySi layer (polysilicon), 14...SiO2, 15...boron glass, 1
6...Channel strike, Pa. Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 13 Figure 14 Figure 161 Figure 17/' Figure 19

Claims (1)

[Claims] 1. A step of forming a second conductivity type layer on one main surface of a first conductivity type semiconductor substrate, a step of forming a first (lower layer) mask material and a second (upper layer) mask material on the surface of the second conductivity type layer. ), the second mask material is used as a mask, and the first mask material has a window opening that is larger than the window opening of the second mask material. a step of introducing an impurity using the second mask material as a mask and forming a first conductivity type layer on a part of the surface of the second conductivity type layer; removing the second mask material and forming the first mask material; a step of embedding a third mask material into the window opening, removing the first mask and using the third mask material as a mask to introduce impurities into the surface of the second conductivity type layer to form a highly concentrated second conductivity type layer; A method for manufacturing a semiconductor device, which comprises a step of forming a semiconductor device. 2. The first mask material is silicon nitride, and the second mask material is silicon nitride.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the mask material is a photosensitive corrosion-resistant resin, and the third mask material is a polyimide resin. 3. Forming a second conductivity type layer on the surface of the first conductivity type semiconductor substrate, forming a first (lower layer) mask material on the surface of the second conductivity type layer and a second (upper layer) mask material thereon. forming a layer consisting of, leaving a part of the second mask material, selectively removing the first mask material using the second mask material as a mask,
A first mask material having a peripheral edge inside the peripheral edge of the second mask material.
a step of using the second mask material as a mask to introduce impurities into the surface of the second conductivity type layer to form a highly concentrated second conductivity type layer; removing the second mask material and adding the first forming a third mask material so as to fill the periphery of the second conductivity type layer, removing the first mask material, introducing impurities using the third mask material as a mask, and forming the third mask material on the surface of the second conductivity type layer. 1. A method of manufacturing a semiconductor device, comprising the step of forming a conductivity type layer. 4. The first mask material is silicon nitride, and the second mask material is silicon nitride.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the mask material is a photosensitive corrosion-resistant resin, and the third mask material is a polyimide resin.