JPS61236223A - Digital-analog conversion and transmission circuit - Google Patents

Abstract

PURPOSE:To obtain a D/A transmission circuit with reduced error, low cost and ease of handling by providing a signal conversion means outputting a pulse width modulation signal to the transmission side and providing a filter means rejecting the harmonics to the reception side. CONSTITUTION:An output clock pulse of an oscillator 32 is counted by a counter 34 and its count is outputted to a comparator 36. An input digital signal SD representing '4' to a terminal A and an input count to a terminal B are compared in the comparator 36. The output goes to an H level when the count is 0-3, while the output goes to an L level with the count of 4-7. The comparator output is inputted to a reception buffer 22 of a receiver 20 via a transmission line 38, and harmonics are rejected by a low pass filter 24 to obtain an analog signal. Since the duty ratio of the output pulse of the comparator 36 corresponds to the signal SD, the output of the low pass filter 24 represents the analog quantity of the signal SD.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention is a digital-to-analog conversion transmission circuit (hereinafter referred to as a single crD/A transmission circuit) that converts a digital signal into an analog signal and transmits this signal to a remote location. (referred to as appositive) Hajime: It is related.

[Conventional technology]

As a conventional D/A transmission circuit, there is one shown in FIG. 5, for example. In this figure (2), the transmitter 10 side has a D/A
It includes a converter 12, an analog comparator 14, and a sawtooth wave oscillator 16, and the receiver 20 side includes a reception buffer 22 and a low-pass filter 24.

First, on the transmitter 10 side (-), the digital signal VD to be transmitted is set so that the D/A converter 12≦2 (-). , analog comparator 14 (- is connected, and the output of this analog comparator 14 is connected to the transmission line 18 (-).
: Therefore, the reception buffer 22C on the receiver 20 side is inputted. The reception buffer 22 includes a low-pass filter 241
= is connected, and this f: is therefore connected to C2 so that an analog output can be obtained.

Next (=, the operation of the above conventional example) First, the digital signal VD is converted into an analog signal, that is, a digital signal VDO value (: a voltage signal having a corresponding level (2 converted). , is input to the analog comparator 14. On the other hand, a sawtooth wave is input from the sawtooth wave oscillator 16 to the analog comparator 14 (=), and this is compared with the analog voltage to output a pulse signal. The pulse width of this pulse signal corresponds to the value of the digital signal VD.In other words, a pulse width modulated output having the same period as the sawtooth wave is transmitted from the transmitter 10 to the receiver 20 (: .

When this transmission signal is filtered by a low-pass filter 24 having a corner frequency sufficiently lower than the period of the signal, high frequency components are removed and a desired analog signal is obtained.

[Problem that the invention seeks to solve]

However, in the conventional D/A transmission circuit as described above, the digital signal is first converted into an analog signal, and then the analog signal (2) is subjected to various processing, so the following There are some inconveniences like.

First, an expensive /A converter is required, resulting in high cost. Amplitude fluctuations in the sawtooth wave oscillator 1 cause errors as they are, and offsets and operation delays of the comparator or conversion errors in the D/A converter also cause errors as they are.

The present invention has been made in view of these points, and an object of the present invention is to provide a low-cost, easy-to-handle /A transmission circuit with reduced errors.

[Means for solving problems]

The present invention includes, on the transmitter side, oscillation means for outputting pulses of a predetermined frequency, counting means for counting the pulses and outputting a count value, and outputting a pulse width modulated signal by comparing the count value and the value of a digital signal. The present invention is characterized in that it is provided with a signal conversion means for removing high frequency components, and a filter means for removing high frequency components is provided on the receiving side.

[For production]

According to the present invention, a pulse width modulation signal is generated by digital signal processing without using a D/A converter or the like.

〔Example〕

Hereinafter, the present invention (two such D/A transmission circuits is shown in attached drawing C:
Embodiment C: Based on the details (second explanation).

FIG. 1 (2) shows the first embodiment of the present invention. In this figure C, the transmitter 60 side includes a pulse oscillator 62, a counter 64, and a digital comparator 66, and the receiver 20 side includes a pulse oscillator 62, a counter 64, and a digital comparator 66. is the reception buffer 22 as in the conventional example above.
and a low-pass filter 24.

On the sending side, the pulse oscillator 62 is connected to a counter 64 (-), and the counter 34 is connected to a digital comparator 66 (:). Also, the output side of this digital comparator 66 is The receiving buffer 221 of the receiver 20 is connected via the transmission line 68.

Among these, the pulse oscillator 62 generates a clock signal of a predetermined frequency and outputs it to the counter 64. Next C:, the counter 64 constantly counts the glock signal, and when a certain count value (:) is reached, the count is repeated from the beginning, and the count value is inputted as Q to the digital comparator 66. The number of digits of 64 is equal to the number of digits C2 of the digital signal to be transmitted.A digital signal SD is inputted to the digital comparator 66 from the outside, and the value A of this digital signal SD and the count value B of the counter 64 are and.

are compared by the comparator 66 (:).For example, when A)B, C2 is the logical value rHJ
level (1) When a corresponding positive voltage is output from the digital comparator 36 and A≦B (- is the logical value rL
The voltage becomes zero corresponding to the J level.

Next C: Overall operation of the above embodiment (explained with reference to Figure 2).
1- shows the waveforms or operations of each part, where the counter 64 counts from "0" to "7" and the digital signal SD is "4". - First, the oscillator 62 oscillates a clock pulse of a predetermined period, as shown in the second figure, and outputs it to the counter 64 (2).The counter 64 counts the input clock pulses, and B) The count value indicated by l1 is output to the comparator 36+2.

On the other hand, a digital signal SD indicating, for example, "4" is input to the comparator 66. The comparator 66 compares the inputs A and B, that is, the digital signal SD, and the count value of the counter 64. In the same figure (as shown in c5, when the count value is “0” to “5”, A
)B, the output of the comparator 66 becomes rHJ level, and when the count value is "4" to "7",
Since A≦B, the output of the comparator 66 becomes rLJ level. The period of this output pulse is determined by the clock period of the oscillator 32 and the number of digits of the counter 64.

The output of the comparator 56 is transmitted through the transmission line 68 (from which an analog signal is obtained).In other words, the low-pass filter 24 can be thought of as a kind of smoothing circuit. Since the duty ratio of the output pulse of the comparator 66 corresponds to the digital signal SDO value C;
is the analog quantity.

Note that if the amplitude of the output pulse of the oscillator 62 is such that the counter 34 operates normally (-), characteristic 1: it will not cause an error.

The second embodiment of the present invention (
Let me explain about two things. Note that the same reference numerals are used for the same component parts C as in the above-described embodiment. Hereinafter, the sixth embodiment (the same applies even if there is one).

FIG. 3 (: On the receiver 40 side, a stabilized power supply 42,
Contains analog signal F-44. The transmission line 38 is
Analog switch 44C: Connected. This analog switch 44 has interlocking switches 44A and 44B, and one end of each is connected to the low-pass filter 24 via a resistor 44C. The other end of the switch 44A is connected to the stabilized power supply 42c', and the switch'f-
The other end of 44A is grounded. These switches 4
4A#44B operate in conjunction based on the output of the comparator 66 (==, and when either one is "ON", the other becomes [OF FJ. For example, the input of the comparator 66 (-, A) When B, that is, comparator 3
When the output of 6 is at the logic value rHJ level, the switch 'I
F-44A becomes [0, N J, and switch 44B becomes [
It becomes 0F FJ. On the other hand, when A≦B, that is, when the output of the comparator 66 is at the logical value rLJ level,
Reverse C: The switch 44A becomes [0FFl, and the switch 44B becomes "ON".

Next(:, The operation of the second embodiment will be explained using the case shown in FIG. 2(:) as an example. First, if the count value of the counter 34 is "0" to "6", Therefore, the output of the comparator 66 becomes the logic value rf (J level), and the voltage at the predetermined level is output from the stabilized power supply 42 with the switch 'f'' 44A turned "ON". Next (:, counter 6
If the count value of 4 is "4" or "7", A≦B
Therefore, the output of the comparator 66 is the logical value rLJ
level, the switch 44B is turned "ON", and the input of the low-pass filter 24 is at ground potential, that is, zero level tonal. Therefore, the low-pass filter 24 (= is the second
A pulse signal having the same waveform as that shown in FIG.

As described above, according to the second embodiment, the pulse output of the comparator 66, that is, the pulse width modulation output, is used as the control signal for the analogue suite 440. Attenuation 1:
This further reduces transfer errors due to this, making it possible to obtain stable analog signals.

Next, with reference to C2 and FIG. 4, the sixth embodiment (:) will be explained.
Both sides have basically the same configuration as the second embodiment described above, but the transmitter 50 side (: is provided with a light emitter 52, and the output side of the comparator 66 is a light emitter 52C:
It is connected. On the other hand, the receiver 60 side (second is the receiver 6
2 is provided, and the output side of this light receiver 62 is connected to the analog switch 44 (:).The light emitter 52 and the light receiver 62 are connected by an optical fiber 541. For example, it can be an optical communication D/A transmission circuit.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be applied even if there are two Cs with appropriate design changes so as to produce the same effect.For example, the first embodiment
The embodiment shown in FIG.

〔Effect of the invention〕

As explained above, the D/A transmission circuit according to the present invention (12) has the following effects.

■ The amplitude of the oscillator on the transmitter side (= This reduces the errors that occur, so even a very common one can be used.

■ Expensive / Since no A converter is used, it is inexpensive.

(2) Since the signal is processed digitally without using analog circuits, the only error factors are transmission delays or time fluctuations in the logic circuit, and good digital-to-analog conversion and transmission can be performed. Additionally, no special adjustments required for analog circuits are required.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of such a D/A transmission circuit, FIG. 2 is a time chart showing an outline of the operation, and FIGS. 6 to 4 show other embodiments. The circuit block diagram shown in FIG. 5 is a circuit diagram showing an example of the prior art. 20.40.60...Receiver'Ka, 24...Low pass filter, 32...Oscillator, 54...Counter, 6
6... Comparator, 68... Transmission line, 42...
Stabilized power supply, 44...analog switch, 8D...
Digital signal.

Claims (1)

[Claims] The transmitter to which the digital signal is input includes an oscillation means for outputting pulses of a predetermined frequency, and a counting means for repeatedly counting the pulses and outputting the count value.
The receiver for outputting an analog signal includes a signal conversion means for digitally comparing the output of the counting means and the value of the digital signal and outputting a pulse signal having a width corresponding to the value of the digital signal; A digital-to-analog conversion and transmission circuit, comprising filter means for removing high frequency components from the pulse signal.