JPS59138102A - Sinusoidal wave generating circuit - Google Patents

Abstract

PURPOSE:To eliminate the asymmetricity of a waveform and the phase shift by utilizing the symmetricity of an added and a subtracted count of a reversible counter. CONSTITUTION:When a clock signal is inputted to a terminal CP of the reversible counter 21, signals shown in (b)-(e) are outputted respectively at terminals QA-QC and CO of the counter 21. In this case, a signal to a terminal U/D changes over the counter 21 so as to make addition at ''1'' input and to make subtraction at ''0'' input. Signals outputted from the terminals QA-QC are converted into decimal numbers by a decoder 22, ''1'' is outputted to any of terminal Yi of the decoder 22 corresponding to converted values 0-4, and they are weighted by resistors Ri. A waveform shown in (h) is obtained by setting suitably the resistors Ri in order to approximate the waveform outputted at a terminal e0 of an amplifier 24 to a sinusoidal wave. Since the same resistors Ri are used at the addition and subtraction by the counter 21, a symmetrical sinusoidal wave is obtained in this case.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is applicable to, for example, psx phase shift keying, or IPSK
The present invention relates to a sine wave generation circuit suitable for use in frequency shift modulation, etc.

[Technical background of the invention]

Traditionally, PB has been used as a method for transmitting digital information.
K<phase shift modulation), ysK (frequency shift modulation), etc. are known. Among these, when using an imperial transmission line, the transmission band is limited, so PSK, which can transmit in a narrow bandwidth, is suitable.

This PSK method is a method for discretely controlling the phase Z of a carrier wave according to input digital information.

An example of a four-phase PSK system will be described with reference to a block diagram of a four-phase phase modulator shown in FIG. 1(a).

In the psx system, the input signal transmitted as digital information is a binary code string, where t'L is 2 bits,
A serial-to-parallel converter IIIC converts the signals into parallel signals.

The 2-bit data f output from this serial-parallel converter l
The lower digit signals are simultaneously supplied to the balanced modulator 2, and the higher digit signals are supplied to the balanced modulator 8. This modulator 8 has one
A carrier wave of reference phase 0 generated by an oscillator 4 is supplied, and a carrier wave advanced by 4 phases is supplied to the modulator 2 by a transporter 5. Therefore, depending on whether the signal of the lower digit of the 2-bit data is 1'' or 04, the phase of the carrier wave output from the modulator 2 will be 1'' or 1'', and depending on whether the signal strength of the lower digit is 1'' or 04''. , the phase of the carrier wave output from the modulator 8 will be 0 or π. Therefore.

When the output Y7111 of the two-stage modulator 2.8 is obtained, a four-phase phase modulated wave modulated as shown in FIG. Supplied.

Power( It is necessary to synchronize with the clock signal in order to get closer to the current state.

First, if the input signal and carrier wave are not synchronized, a two-phase shift will occur, making it impossible to obtain a modulated wave corresponding to the input signal. However, if the carrier wave is generated by an oscillation circuit or the like independently from the clock signal for sampling data, it is difficult to synchronize them, so the carrier wave and the input signal must be synchronized.

Therefore, there has been a desire to generate a sine wave as a carrier wave from a clock signal to eliminate the need to synchronize the input signal and the carrier wave again. Conventionally, in order to meet this demand, the circuit shown in FIG. 2 was constructed to generate a sine wave as a carrier wave. This circuit is.

The addition counter 11 that counts clock signals and the output signals of each stage of this addition counter 11? Decoder 12 to convert
and an adder 13 that divides the output signals of each stage of the decoder 12 into respective values of the sine wave to be approximated and adds them.

In the above circuit, when a clock signal is input to the terminal CP of the 770 counting counter 11, the terminals Q1AtQB, Qo of the addition counter 11 are input; A signal frequency-divided by 2 is output. This situation is shown in Figure 1.

Terminals QA, QB, Q of the above 7111 N-counter 11
The signal output from o is processed by the decoder 12 to
It is converted into a base number and converted into f'L, which is sent to one of the terminals yiH=o~7) of the decoder 12 corresponding to the fc value θ~7).
1' is output. Here, terminal Y of the decoder 12,
(i: 0~?) When IE'l'(') v, ,
o throat*v,=.

The voltage is output from the decoder 12.

In the jJD calculator 18, a resistor R□ (1=O to 7) is connected directly to the input terminal 1 between the inverting input terminal of the amplifier 14 and the terminal Y1 (1=O to 7) of the decoder 12, and the amplifier 140 Inverting input terminal and terminal θ. The configuration is such that a resistor RX is connected between them. As mentioned above, the decoder 12 is the decoder 1
Terminal Yi (1=0-JI)'0) selected by 2
1 for only one! Output and output Ot to other terminals. Therefore, the terminal e of the amplifier 14. The output voltage is .

R a It is expressed as

Therefore, in order to make this output close to a sine wave, if a resistor R□ (1=θ~7)t is set, for example, the waveform shown in Fig. 8 is output from the terminals. By passing the output waveform through a band pass filter, an approximated sine wave can be obtained.

[Problems with background technology]

In the conventional sine wave generation circuit with < n1fL as described above, it is possible to supply a carrier wave whose phase is synchronized with the input signal, but since the required sine wave has a symmetrical waveform, the generated waveform is In order to make it symmetrical, resistor R1” R
7'R2"R6" r R5. However, since the resistance includes errors, it is impossible to satisfy the above conditions, and as a result, 9 occurs and the t sine waveform becomes asymmetrical. In other words, this sine wave has a phase shift.

Therefore, in the PSK described above, when the above-mentioned sine wave generation circuit is used as a carrier wave, there is a problem that the change in position as digital information is affected by the phase shift of the carrier wave, and correct information is not transmitted. was occurring. Furthermore, in order to accurately approximate and obtain a t sine wave, the number of resistors increases, which is problematic in terms of cost.

[Purpose of the invention]

The present invention is synchronized with the Utsuk signal, and is the waveform asymmetry? It is an object of the present invention to provide a sine wave generation circuit suitable for use in PSK, FSK, etc., which generates a sine wave in which one phase shift is eliminated by eliminating the phase shift.

[Summary of the invention]

In order to achieve the above object, the present invention has the following features.

a counter for reversibly counting clock signals; and means for reversing the counting direction of the upper distribution counter every time the count value of this counter reaches a predetermined winnow 1 count value and a second count value; It consists of a decoder that converts the output signal of each stage of the counter, and an adder that divides and adds the output signal of each stage of the decoder to the value of the sine wave to be approximated. To provide a sine wave generating circuit Z that generates a symmetrical sine wave by exploiting the symmetry of subtraction counting.

(Strongly Recommended Embodiment of the Invention) An embodiment of the present invention is shown in FIG. 4 and will be explained below.
, QB, and Qo and are connected to the decoder 22. Switching the reversible counter 21 from subtraction to addition, or from MJX to subtraction! The terminal Q of the clip-flop 25 is connected to the terminal %. The terminal S of this flip-flop 25 is connected to the terminal Q of the reversible counter 21 . IK[M is applied to the terminal R of the flip-flop 25.

All terminals QA, QB, and Qo of the reversible counter 21 are O.
, the terminal CO of this reversible counter 21 becomes lap.
is connected.

It was a cabinet. The adder 28 connects the terminal Y□(1
A resistor R1 (1:0 to 4) is connected to each of the resistors R□ (1=0 to 4), and the other end of the resistor R□ (1=0 to 4) is connected to the amplifier 24.
The inverting input terminal of the amplifier 24 and the terminal θ are commonly connected to the 0 inverting input terminal. A resistor is connected between the two.

As described above, if <1ltFN, then the operation t of the present embodiment, the fifth
This will be explained with reference to the figures.

When a clock signal is input to the terminal aP of the reversible counter 21, the terminal QA of the reversible counter 21 is input.

Signals shown in FIG. 5(b) to (θ) are output to QB, Qo, and CO. The terminal % of the reversible counter 21 is used for addition when the input is 1, and for subtraction when the input is 0.
Switch.

From the above, when the terminals Q, A, QB, and Qc are all V, in other words, when the count value C is 00, the terminal CO becomes 41', and the flip-flop 25 is set to "
14 w output from terminal Q, A is input to terminal 14 of the reversible counter 21, the reversible counter 21 adds and counts 1t, terminal Q of this reversible counter 21. is “12
In other words, when the count value O is 642,
The flip-flop 25 is reset and the terminal Q to 6C
is output, and ν is input to the terminal % of the reversible counter 1z11, and the reversible counter 21 performs subtraction counting.

Terminal 1 of the reversible counter 21; LA, QB, Qo
The constant signal outputted from the converter is converted into an lθ base number by the decoder 22, corresponding to the converted -tlJj values 0 to 4.

De: Terminal Yi (1 = 0 to 4) of ff-1-22 is outputted, and the output signal of each stage of the decoder 22 is controlled by the resistor R, (1 = 0 to 4). weighted.

Here, in order to approximate the waveform output to the terminal e0 of the amplifier 24 to a sine wave, by setting the resistor R□ (0 to 4) as an example, the waveform shown in FIG. In this actual example, the adder 28 uses the same resistors R1, R2, 'R3'4 when the reversible counter 21 performs addition and subtraction counts, so the sine waveform is symmetrical. can be obtained. Therefore, even if the circuit of this embodiment is used as a carrier wave in the PSK system,
Since there is no phase shift in the carrier wave, there is no possibility of transmitting erroneous information.11! Highly axial PSK@ can be performed.

Next, another embodiment of the invention will be described with reference to FIGS. 6 and 7. This embodiment is a circuit in which the octal reversible counter 21'& hexadecimal reversible counter 81 of the i1T embodiment is replaced with a decoder 82'It which has an input terminal and an output terminal V incremented. I am using it.

In this embodiment having the above configuration, a clock signal having twice the frequency of the clock signal of the previous embodiment is used.

When input to the terminal CP of the reversible counter 81, the signal shown in FIG.
) to (e) are connected to terminals Q, A, Q, B, Q
, o, is output from the QD. Does the reversible counter 81 repeatedly divide the addition count and the subtraction count into one repetition period yxsi while the count value 0 is between "O' and 8'?

Terminals QA-Q, B#Qo of the reversible counter 81
.

The signal output from QD is converted to R by the decoder 82.
A terminal Y1 (i=8) of this decoder 82 is left, and a terminal e of the amplifier 84 is connected thereto. &C In order to approximate the output waveform to a sine wave, by setting the resistor R1 (1:=0 to 8) as an example and ``C5=-'', the waveform shown in FIG. 7(1) is obtained.

According to this embodiment, it is possible to generate a waveform closer to a sine wave with fewer +1ia14 wave components than in the previous embodiment.

In addition, in the above embodiment, the 7 lip flops 85
An input signal is input to the terminal S of the reversible counter 81 from the terminal QD. However, if the input is calculated from the AND of each terminal QA, QB, Qo, and QD of this reversible counter 81,
Count value , *, reversible counter 8 between ' and 115'
1fr - By repeating the addition count and the subtraction count, one period of the waveform may be divided into 80 parts, and 9 approximate waveforms with higher accuracy may be output.

That is, according to the present invention, the reversible counter 1xJ3! L
Since the count and the subtraction count can be inverted at any count value, it is possible to generate a sine wave approximated with any cycle j and with any precision.

[The young fruits of invention]

According to the present invention, it is possible to obtain a symmetrical waveform and generate a sine V without a phase shift by utilizing the symmetry of the X calculation and the subtraction count of the reversible counter as described above. Furthermore, due to the above symmetry, the output terminal of the decoder and the weighted n output signal connected to this output terminal are weighted (the number of resistors to be connected is greatly reduced, so when integrated, it is difficult to It is extremely advantageous in terms of installation of one circuit as it can reduce the number of cages required.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a four-phase phase modulator, Fig. 2 is a circuit diagram showing a conventional sine wave generation circuit, Fig. 8 is a diagram showing waveforms of each part shown in Fig. 2, and Fig. 4 is a diagram showing the waveforms of each part shown in Fig. 2. A circuit diagram showing a seventh embodiment of the sine wave generating circuit according to the present invention, FIG. 5 is a diagram showing waveforms of each part shown in FIG. 4, and FIG. 6 is a diagram showing another embodiment according to the present invention. It is. 21.81...Counter 22.82...Decoder 28.88...Kataguchi) 1 unit 24.84...Amplifier 25.85...7 Rig 7o Tsubu<7817) Representative Patent Attorney Chika Nori Kensuke (1 person) Fig. 1 ((1) (b) (b) oo + jK '01'' - A4 Fig. 2 Fig. 3 Fig. 4rI!J Fig. 5 Fig. 6 Fig. 7

Claims (1)

[Scope of Claims] A counter that selectively adds or subtracts a clock number to a predetermined first or second count value. means for reversing the counting operation of the counter each time the count value of the counter reaches the first count value or the second count value; The output terminal has a number of output terminals corresponding to the number of counted values of the counter, and the output terminal corresponds to the phase of the approximate point of the sine wave to be approximated by converting the output signal of the counter in accordance with the clock signal. A sine wave generating circuit characterized in that it comprises a 770x device which divides the output signal of this decoder into a sine wave value to be roughly approximated and adds the voltage when the decoder is on.