JPS6242412B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency display device used in a PLL synthesizer type receiver.

Conventionally, in a PLL synthesizer type receiver, the only way to display the received frequency in an analog manner, for example using a meter, was to use the output voltage, ie, the tuning voltage, of the low-pass filter that makes up the PLL circuit. However, this tuning voltage cannot be made exactly proportional to the receiving frequency due to the voltage-capacitance characteristics of the variable capacitance diode used. Especially in the AM band, the voltage-capacitance characteristics are highly nonlinear, so the receiving frequency cannot be made linearly proportional to the receiving frequency. It was difficult to provide analog display with good quality. Also FM and AM
The tuning voltage range varies greatly depending on the variable capacitance diode used, and the tuning voltage range varies greatly when the power is turned on and off.
While the PLL circuit is not working, the tuning voltage cannot be specified.
For this reason, there was a problem in which the meter could swing out of control, either reaching the maximum voltage or reaching the minimum voltage.

The present invention provides a frequency display device that solves these problems.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

Figure 1 is a peripheral block diagram of the PLL circuit.
1 is a clock pulse generator; 2 is an 8-bit binary counter that performs up-counting using the clock pulses generated by the clock pulse generator 1;
3 is a receiving frequency display decoder that converts the contents of binary counter 2 into 7-segment data of the corresponding receiving frequency; 4 is a decoder 3 with 7 segments;
A display device digitally displays the signal converted to segment data; 5 is a program frequency divider that divides the input signal at a division ratio specified by the contents of binary counter 2; 6 is a reference frequency generator; 7 is a A phase comparator that compares the phase of the output of the reference frequency generator 6 and the output of the program frequency divider 5; 8 is a low-pass filter that converts the output of the phase comparator 7 into a low frequency; 9 is the output voltage of the low-pass filter 8; Voltage controlled local oscillator with controlled oscillation frequency, 10
11 is a prescaler which fixedly divides the output of the local oscillator 9, converts it into the required frequency and supplies it to the program frequency divider 5, and 11 receives the content of the binary counter 2 and converts the digital value thereof to the corresponding frequency. A digital-to-analog converter 12 converts into an analog value, and 12 is an output terminal of an analog voltage.

Note that the program frequency divider 5, reference frequency generator 6, phase comparator 7, low pass filter 8, voltage controlled local oscillator 9, and prescaler 10 are well-known.
A PLL circuit is configured.

A concrete configuration of the binary counter 2 and the digital/analog converter 11 is shown in FIG. In FIG. 2, the binary counter 2 includes two 4-bit binary up counters, which are connected in series to form an 8-bit binary counter. Here, first, one pulse is input from the clock pulse generator 1 to the pin of the binary counter 2 in the case of frequency scanning for each step, or continuous pulses in the case of fast forwarding. When a pulse is input to the pin, the contents of binary counter 2 are incremented by +1. The pin is a terminal that controls whether or not to accept a clock pulse input to the pin. As the clock pulses are sent sequentially, the counter in the binary counter 2 counts up and finally reaches the state [1111]. At this time, the diodes D4, D5, D6, and D7 are all turned off, and the potential of the pin becomes H level. When this state is reached, the counter is cleared to the state [0000] by the next clock pulse input to the pin, and the pin goes to L level through the diodes D4, D5, D6, and D7. The counter counts up when this pin changes from H level to L level. In other words, the diodes D4, D5, D6, and D7 detect the carry of the counter. When the clock pulse is input in the same manner, the counter will count up, and finally the D output of the counter will be
The diodes D1, D2, and D3 are turned off at the same time that the D and C outputs of the counter go to H level, and the pins that were at L level become H level. The pins are a counter and a terminal for resetting the counter, respectively, and this is executed at H level. Therefore, at this point, the counter and counter will be reset at the same time, and the contents will be [0000].
and return to [0000]. In this way, D1, D2, D
Each diode of 3 defines a counter and an upper limit of the counter. In other words, if we consider the Japanese FM band to be 76.0 to 89.9MHz and the channel space is 100KHz, the number of channels included in the band will be 140, and if we convert the 141 channels, which exceed the upper limit of the band, to binary,
It becomes [1000, 1100]. Therefore diode D
1, D2, and D3 are connected to the output terminal where "1" stands on the 141st channel of 8-bit counter 2.
This defines the upper limit of the binary counter 2.

In this way, the 8-bit binary counter 2 is
While the value of that 1 bit takes a value corresponding to one channel of the receiving frequency, it can take any value within the receiving frequency range, and this value is decoded by the decoder 3 and the receiving frequency is digitally displayed on the display 4. The local oscillation frequency corresponding to the reception frequency can be obtained by displaying the value or by controlling the program frequency divider 5 using this value.

On the other hand, each bit output of this 8-bit binary counter 2 is also connected to a digital-to-analog converter 11. This digital-to-analog converter 11 converts an 8-bit digital quantity into an analog current value corresponding to it and outputs it to a pin. VR1 is this digital-to-analog converter 1
1 gain adjuster. The analog current output to the pin is converted into an analog voltage by a current-voltage converter 13. The analog voltage output finally obtained at the output terminal 12 becomes a voltage proportional to the value stored in the 8-bit binary counter 2, that is, a voltage proportional to the receiving frequency, and the voltage changes for each channel of the receiving frequency. Therefore, the obtained analog voltage has linearity with respect to the reception frequency, and moreover, it is possible to obtain analog voltages in the same voltage range for FM and AM.

Furthermore, if a digital-to-analog converter that varies the duty of pulses is used as the digital-to-analog converter 11, an analog voltage can be obtained by simply providing an external CR integrator. In this case, by using a well-known PLL control LSI with a variable duty output terminal for electronic volume, the above system can be configured with a single chip, at an extremely low cost, and accurately proportional to the receiving frequency without increasing the number of parts. It is possible to obtain analog voltage.

As described above, in a receiver having a PLL circuit, the present invention converts a digital amount stored in a storage device for storing frequency information into an analog voltage corresponding to the amount by a digital-to-analog converter,
This analog voltage is used to display the reception frequency in an analog manner, so compared to the analog display using the low-pass filter output voltage of a conventional PLL circuit, a straight line that is accurately proportional to the reception frequency is displayed. It is possible to perform analog display with good quality.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a circuit diagram of the main part. 1... Clock pulse generator, 2... Binary counter (storage device), 3... Decoder, 4...
Digital to analog converter, 5 to 10...PLL
Circuit, 11...Digital-to-analog converter, 1
2...Analog voltage output terminal, 13...Current -
voltage converter.

Claims (1)

[Claims] 1 A storage device that stores frequency information, a program frequency divider set to a division ratio corresponding to the frequency information of the storage device, and a phase comparison between the output of the program frequency divider and the output of the reference frequency generator. A receiver having a phase comparator that converts the output of the phase comparator, a low-pass filter that converts the output of the phase comparator into a low-frequency wave, and a local oscillator whose frequency is controlled by the output of the low-pass filter. , a frequency display device comprising a digital-to-analog converter for converting the digital quantity into an analog voltage corresponding to the digital quantity, and displaying the frequency stored in the analog voltage in an analog manner.