JPS6019169B2 - Superheterodyne receiver tuning device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a tuning layer for a superheterodyne receiver, comprising a counting device for counting the oscillations of a local oscillator of the receiver, in which the frequency steps counted are is smaller than the frequency step between the transmission frequencies of the predetermined frequency sequence, and further comprising an automatic frequency control device, in which a control signal for frequency control is derived from the counting state of the counting device. The present invention relates to a tuning device for a superheterodyne receiver.

Known automatic frequency control devices (AFC circuits) have a significant drawback that when two broadcasting stations are adjacent to each other at a narrow interval in the frequency spectrum, the system inevitably tunes to the broadcast wave with the stronger received field strength. The subject of the present invention is the known AF
For a superheterodyne receiver with a C circuit,
To provide a tuning device that can perform tuning extremely easily. Also, a counting device from which the control signal is taken out;
In order to simplify the device, the number of lines connecting circuit elements forming control signals should be reduced as much as possible. This problem is solved by the invention described in claims 1 and 2 as follows.

That is, a counting device is constructed from a counting stage that counts up to 5, and 1
The control voltage for control in one direction is taken directly from the logic signal (for example a "1" signal) at the second output terminal of the counting stage, and the control voltage for control in the other direction is taken directly from the second output terminal of the counting stage. It is derived from a logical combination of the signal and the signal at the third output terminal (for example, a "0" signal at each of its terminals).
Further, according to the present invention, the counting device is composed of a counting stage for counting up to 2 and a counting stage for counting up to 5, and the vibration of an oscillator is supplied to the input side of the counting stage for counting up to 5, and the counting stage for counting up to 5 is provided. The output signal at the second output of the stage is fed via an inverting element to the counting input of the counting stage for counting up to two. Next, embodiments of the present invention will be described in detail using the drawings.

In FIG. 1, a received high frequency wave reaches a mixing circuit 3 via an antenna 1 and a high frequency amplifier 2.

This mixing circuit includes an intermediate frequency amplification and demodulation circuit 4,
A low frequency circuit 5 that feeds power to the speaker 6 is directly connected to the rear. The vibration of an oscillator 7 is applied to the mixing circuit 3 to generate an intermediate frequency, and the frequency is controlled by a control voltage (tuning voltage). This oscillation is further transmitted to the broadband amplifier 8.
added to. This broadband amplifier converts the oscillating vibrations into square wave vibrations of the same frequency. This oscillation is counted by a counter. The circuit of the broadband amplifier 8 is also used in the AM'Komo FM and is described in detail, for example, in German Patent Application No. 23-673.4 of the applicant. The digital output signal of the broadband amplifier 8 is applied to a frequency divider 9 whose frequency division ratio can be set to various values. A gate circuit 10 is connected directly to this divider. The gate circuit is controlled by a pulse applied to its control input 22. The pulses from the frequency divider 9 are therefore applied to the input E of the counter 11 only for a predetermined time, ie during the gate opening time.
is counted by this counter. The periodically repeated gate opening time can be chosen to be, for example, IQhs. This IQhs gate opening pulse can be generated using a crystal oscillator (not shown) and a frequency divider connected thereto. In the following description, it is assumed that this superheterodyne receiver operates in the very short wave region, and receives, for example, an FM frequency of 80.05 MHZ. The frequency division ratio of frequency divider 9 is assumed to be 100:1. Therefore, the frequency divider can be used to convert input pulses of, for example, 10 Hz to I
Forms an MHZ output pulse. Figure 6a) shows the frequency divider 9
b) shows the gate opening pulse applied to the control input 22 of the gate circuit 10; c) shows the pulse delivered from the output of the gate circuit 10. This pulse c) is applied to the input E of the counter 11. The counter is 1 female day 2
One counting pulse is counted each time a corresponding number of pulses are input. That is, the counting state of the counter 11 is changed by "1" every time the oscillator frequency changes by 10 KHz. Therefore, if the gate opening time is 1 hs, the value of the frequency interval or frequency step counted by the counter 11 is 1 HZ, that is, one counting pulse is counted by the counter 11 every 10 KHz. Make it. When the broadcast wave is received, the oscillator 7 has a specified frequency, and in this case, the counter 1
Make the count value of 1 correspond to 4 or 9. This will be discussed below. Corresponding to the channel spacing between broadcast waves being 5 HZ, there are 5 counting steps (
A frequency step of 1 MHz) is provided. Broadcast waves in the ultra-high frequency range are usually arranged at intervals of 100 KHZ, but in some cases, this interval may be 50 KHZ.
Therefore, in the case of the present invention, the channel spacing is set to 50 KHz. Examples of the reception frequency, the oscillation frequency of the oscillator 7, the output frequency of the frequency divider 9, the pulse meter passing during the gate time, and the counting results of the counter 11 are shown below.

In this case, the value of the intermediate frequency is 10.6 HZ.
Counter 11 also operates as a 10:1 frequency divider.

From its output IA, pulses are supplied to a counter and control unit 12 which cooperates with this counter 11 to count the received frequency. The counted received frequencies are optically displayed on the display device 13. The reception frequency is generated by counting the oscillations, in which case the intermediate frequency is subtracted. Counter 11
(see Figures 3 and 4) has two output terminals C and D, to which the logic signal "0" is applied depending on the counting state.
Various combinations of and "1" appear.

These combinations are shown in FIG. In the case of a specified frequency belonging to the receiving frequency of broadcast waves arranged at intervals of 50 KHZ, a logic value "0" appears at the output terminal C, and a logic value "1" appears at the output terminal D.

These "0" and "1" are part of the value of 4 or 9 expressed in binary code. In the case of "0" and "1", a control voltage for changing the oscillation frequency is not generated. Both output terminals C,
D is connected via a NOR gate 14 to a low-pass filter (integrating element) 16 connected after the DC voltage amplifier 18. When the logic signals representing counting states 4 and 9 appear at the output terminals C, D, the output 14a of the NOR gate 14 receives the logic value "0", which corresponds approximately to the level of OV.
appears. The low-pass filter 16 is therefore unable to generate a voltage. The low-pass filter 15, which is directly controlled from the output terminal C, also does not generate a voltage for the "0" potential of the terminal C. On the contrary, if the oscillation frequency deviates from the specified frequency, the count value will be different from 4 or 9.

Therefore, a control voltage is generated to adjust the oscillation frequency to a specified frequency value. When the counting state is 2, 3 or 7, 8, a logic value "1" appears at the output terminal C, and a logic value "0" appears at the output terminal D. In this case, the output side 14a is still at "0" potential, so that no voltage is generated at the output side of the low-pass filter 16. However, the low pass filter
5 generates a positive voltage because it is supplied with a logic value "1" having a positive voltage level. This voltage is amplified by a DC voltage amplifier 17 connected in the latter layer and appears on its output line 19 as a control voltage UI, that is, a control variation from a predetermined reference voltage. Since the logic value "1" appears periodically at the output terminal C, pulses are continuously supplied to the low-pass filter 15. Therefore, the filter 15 generates a DC voltage due to its integral action. Voltage UI is applied to oscillator 7 via line 21, so that the oscillation frequency increases until the specified frequency is reached again. A change in the frequency of the oscillator 7 can be carried out via a voltage-dependent capacitive diode. When the oscillator 7 reaches the specified frequency, the counting state of the counter 11 becomes 4 or 9 again, so that the control voltage is no longer generated. When the counting state is 2, 3 or 7, 8, the oscillation frequency is increased.

This is shown by {10△na} in FIG. On the other hand, if the counting state is 0, 1 or 5, 6, a change in the control voltage, ie, the reference voltage, appears. This voltage reduces the oscillation frequency that deviates from the specified frequency. As shown in Figure 2, in these counting states, output terminals C and D are both “
0" potential. Therefore, a pulse of "1" appears at the output 14a of the NOR gate 14. This pulse is applied to the low-pass filter 16. Due to the integral action of this filter, the DC voltage amplifier 18 The control direction of the DC voltage amplifier 18 is configured to be opposite to the control direction of the DC voltage amplifier 17. As a result, the output current J2 of the output line 20 is controlled by the DC voltage amplifier 17.
The polarity is opposite to that of the output current J. The control voltage U2 controls the oscillator 7 to reduce its actual frequency to the specified frequency. The capacitor 31 connected to the currents J, , 21 is charged or discharged. The voltage of the capacitor is set accordingly, and this voltage becomes the control voltage. When the counting state is 0, 1 or 5, 6, the output terminal C has a “0” potential, so the low-pass filter 1
5 does not generate voltage. As a result, only voltage U2 acts. Both DC amplifiers 17 and 18 are, for example, CA308 top type (
RCA).

The counting state of the counter 11 is maintained constant from the end of one gate time to the start of the next gate time. A control voltage for the oscillator is generated during this period. However, between the start and end of the gate time, 0
Output terminals C and D correspond to counting states from to 9.
Logic signals are generated one after another. Therefore, before the logic signal at the output terminals C, D reaches its final value at the end of the gate time, the control voltage U corresponding to the change in this logic signal
．． and U2 occur. However, as mentioned above, voltages U, , U2 do not appear simultaneously. In other words, the control voltage U, which increases the frequency of the oscillator, and the control voltage U2, which decreases it, occur alternately during the counting time.

Therefore, the logic signals appearing at terminals C and D during the counting time,
Therefore, even if the control voltages U, . . . U2 change, the time constant of the control voltage generator and the counting pause time, which lasts longer than the counting time, are only negligibly affected. Therefore, practically no adverse effects on the functioning of the tuned circuit occur. However, it is also possible to provide a logic circuit (not shown) by means of which only the counting state appearing at the end of the gate time is evaluated, so that the control voltage is generated only during the counting pause time.

This tuned circuit can also be used in the short wave, medium wave or long wave reception range.

In the case of short waves, the frequency division ratio of the frequency divider 9 is such that the channel spacing is approximately H.
The frequency steps counted accordingly are IK
Changed to HZ. It is advantageous to change this frequency division ratio at the same time when setting each reception area. If a counter with a different counting type (not the IG Hayabusa counter) is used, the oscillation frequency interval can be set to a value other than HZ and 50KH2.

For example, if a counter that counts up to 9 is used, a frequency spacing of channel spacing of HZ, which corresponds in part to the medium wave region, can be obtained. It is also possible to combine various channel spacings.
Next, the counter 11 used in this tuning circuit will be explained using FIGS. 3 and 4.

FIG. 3 shows a known 1G ship counter. This counter is, for example, model SN7490 (Texas Instruments). 1 Bo Hayabusa Counter 1 1 is 4 as is known
It can be configured by connecting two flip-flops FFI-FF4.

Among these flip-flops, the first flip-flop. FFI constitutes a counter that counts up to 2, and the other three flip-flops. FF2 to FF4 form a counter that counts up to 5. As is known, the counter can also be used as a frequency divider, so that the pulses applied to the counting input E are frequency-divided by 10:1 and appear at the output IA of the counter 11. Counter 11 has four output terminals A, B, C, D, the logical values appearing at these terminals representing the number of pulses counted in binary code. This known decimal counter is constructed as shown in FIG. 4, and control information is obtained using only a portion of the count value appearing in the form of a sign at output terminals A-D. This is achieved in the following way: the counting pulses fed to the input E of the counter 11 are fed directly to the input BD of the counters (FF2-FF4) counting up to 5. . Furthermore, the output terminal C is passed through an inverting element 30 to a counter (flip-flop FF) that counts up to 2.
Connect to the input side Ain of I). In the case of the known counter, the weight 4 is assigned to the output terminal C in binary form (i.e. in the case of counting state 4 the logic value "1" appears at the output terminal C in the known counter, while the other The output terminal of is at “0” potential). The logic state of the output terminals A-D shown in FIG. 2 thus appears as a function of the counting pulses applied to the input E.
Logic signals shown in boxes appearing at output terminals C and D
It is sufficient to use only ``0'' and ``1'' for the control voltage generation.As a result, the output terminals A and B are not needed for this purpose.Since the evaluation is based directly on the logic potentials, the decoder This simplifies the tuning circuit considerably.Since the output terminal C is connected to the input side Ajn of the flip-flop FFI via the inverting element 30,
The counter in FIG. 4 also converts the pulses supplied to this counter into 10
: can be divided into 1.

This frequency-divided pulse can be taken out from the output side IA, which is connected to the output terminal A. In FIG. 2, it can be seen that the frequency is divided by 10:1 according to the potential of the output terminal A, which is surrounded by a broken line. The potential at output terminal A is alternately "1" and "1" during each of five consecutive counting pulses. FIG. 5 shows an embodiment of the NOR gate 14 described above.

The signals supplied via both input lines 23 and 24 are connected to a resistor 25.
, 26 to the base of transistor 28. The base can optionally be connected to a reference potential (earth) via a resistor 27 shown in broken lines. Output line 14
The output signal of the NOR gate appearing at a is the transistor 2
8 collector. Furthermore, the collector is connected to the operating voltage +UB via an operating resistor 29. This operating voltage corresponds to, for example, a positive voltage level representing a logic state "1".

[Brief explanation of the drawing]

1 is a schematic circuit diagram of a superheterodyne receiver with a tuning circuit according to the invention; FIG. 2 is the counting state of the counter coded as a function of the counting pulses supplied to the counter;
Fig. 3 is a block diagram of a known IG Hayabusa counter, Fig. 4 is a block diagram of a counter used in the present invention, and Fig. 5 is a block diagram of a NOR counter.
A schematic circuit diagram of the gate, FIG. 6 shows waveform diagrams on the input side and output side of the gate circuit. 2...High frequency amplifier, 3...Mixing circuit, 4
...Intermediate frequency amplification and demodulation circuit, 5...
...Low frequency amplifier circuit, 7...Oscillation circuit, 8...
...Broadband amplifier, 9... Frequency divider, 10.
...Gate, 11...Counter, 12...
... Counter and control section, 13 ... Display device,
15, 16...Low pass filter, 17, 18
...DC voltage amplifier. F/G. 2 F'G. 5'rG. 'FIG. 3 F'G・IFig. 6

Claims (1)

[Claims] 1. A tuning device for a superheterodyne receiver, comprising:
The receiver includes a counting device that counts vibrations of the local oscillator of the receiver, and the frequency steps counted by the counting device are smaller than the frequency steps between broadcast frequencies arranged at predetermined intervals, and further includes automatic frequency control. A tuning device for a superheterodyne receiver comprising a device, in which a control signal for frequency control is derived from a counting state of a counting device, wherein the counting device is configured to include a counting stage (FF2) for counting up to five. ~FF4), and 1
The control voltage for control in the direction is applied to the counting stage (FF
The control voltage for control in the other direction is directly taken out from the logic signal of the second output terminal C of FF2 to FF4),
A tuning device for a superheterodyne receiver, characterized in that the signal is extracted from a logical combination of the signal at the second output terminal C of the counting stage (FF2 to FF4) and the signal at the third output terminal D. 2. A tuning device for a superheterodyne receiver, which
The receiver is equipped with a counting device that counts the vibrations of the local oscillator of the receiver, and the frequency steps counted by the counting device are smaller than the frequency steps between broadcast frequencies arranged at predetermined intervals, and automatic frequency control is provided. a frequency display device in which a control signal for frequency control is derived from the counting state of a counting device, and a frequency display device in which the counting device is directly connected to the frequency display device as a frequency divider. In the tuning device of the superheterodyne receiver connected in front of
) and counts up to 5 (FF2 to FF2).
The oscillator vibration is supplied to the input side of FF4), and the control voltage for control in one direction is supplied to the input side of the counting stage (FF2 to FF
3) is directly taken out from the logic signal of the second output terminal C, and furthermore, the control voltage for control in the other direction is taken out by the counting stage (
The output signal of the second output terminal C of the counting stage (FF2 to FF4) that counts up to 5 is extracted from the logical combination of the signal of the second output terminal C of FF2 to FF4) and the signal of the third output terminal D. Counting stage (FF1) that counts up to 2 via an inverting element
A tuning device for a superheterodyne receiver, characterized in that the tuning device supplies a signal to a counting input side of a superheterodyne receiver.