JPS61235765A - Inspecting method for printed circuit board - Google Patents
Inspecting method for printed circuit boardInfo
- Publication number
- JPS61235765A JPS61235765A JP60076669A JP7666985A JPS61235765A JP S61235765 A JPS61235765 A JP S61235765A JP 60076669 A JP60076669 A JP 60076669A JP 7666985 A JP7666985 A JP 7666985A JP S61235765 A JPS61235765 A JP S61235765A
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- block
- printed wiring
- overcurrent
- blocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はプリント配線板の検査方法に関し、特に、回路
の欠陥部を溶断して不良品を選別するプリント配線板の
検査方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a printed wiring board inspection method, and more particularly to a printed wiring board inspection method for selecting defective products by cutting out defective parts of circuits.
（従来の技術）
絶縁基板に印刷回路を設けたプリント配線板は、現在、
種々の電気機器に組み込まれているが、電気機器の小型
化に伴い、小型で高密度のものが用いられるようになっ
てきた。(Prior technology) Printed wiring boards, which have printed circuits on insulating substrates, are currently
They are incorporated into a variety of electrical equipment, and as electrical equipment becomes smaller, smaller, higher-density products are being used.
プリント配線板は、小型で高密度にするためには、ライ
ン幅の狭い構造となり、ラインに切り欠は等の損傷部が
あると、持ち運びの際あるいは使用時等に容易に断線し
易い欠点があった。In order to make printed wiring boards compact and high-density, they have a structure with narrow line widths, and if the lines have damaged parts such as cutouts, they can easily break when being carried or used. there were.
そのため、通常は製造工程の段階において、拡大鏡を用
いて目視検査等を行い、断線不良の不良品をチェックし
選別している。Therefore, visual inspection using a magnifying glass is usually performed during the manufacturing process to check and sort out defective products with broken wires.
（発明が解決しようとする問題点）
しかしながら、この方法では、検査に要する時間が長く
なり量産が困難であり、また、目視であるため検査ミス
を生じ易い欠点があった。(Problems to be Solved by the Invention) However, this method has disadvantages in that the time required for inspection is long and mass production is difficult, and that inspection errors are likely to occur because inspection is performed visually.
これ等の欠点を解決するために、絶縁基板に印刷された
個々の回路に過電流を流して欠陥部分を溶断する方法が
考えられる。が、単独の回路数の多いプリント配線板の
場合、過電流をその回路数分だけ通電しなければならず
、検査時間はあまり短縮されず、自動化の長所を生かせ
ない欠点がある。In order to solve these drawbacks, a method can be considered in which an overcurrent is applied to each circuit printed on an insulating substrate to blow out the defective portion. However, in the case of a printed wiring board with a large number of individual circuits, the overcurrent must be applied for the number of circuits, so the inspection time is not reduced much and the advantages of automation cannot be utilized.
本発明の目的は、以上の欠点を改良し、断線不良となり
易い欠陥回路を有するプリント配線板を短時間にかつ確
実にチェックでき、自動化の可能なプリント配線板の検
査方法を提供するものである。An object of the present invention is to improve the above-mentioned drawbacks, to provide a method for inspecting printed wiring boards that can be automated and that can quickly and reliably check printed wiring boards that have defective circuits that are prone to disconnections. .
（問題点を解決するための手段）
本発明は、上記の目的を達成するために、プリント配線
板の回路に過電流を流し欠陥部を溶断するプリント配線
板の検査方法において、任意個数の回路を直列接続して
ブロック化し、該ブロックに過電流を流して前記回路の
欠陥部を溶断することを特徴とするプリント配線板の検
査方法を提供するものである。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for inspecting a printed wiring board in which an overcurrent is applied to the circuits of the printed wiring board and a defective part is blown out. The present invention provides a method for inspecting a printed wiring board, characterized in that circuits are connected in series to form blocks, and defective portions of the circuits are blown out by passing an overcurrent through the blocks.
（作用）
本発明によれば、多数の独立した回路を幾つかにまとめ
てブロック化し、ブロック内の回路を互いに直列接続し
、ブロック毎に過電流を流して回路の欠陥部を溶断して
いるために、過電流の通電回数を減少でき、検査に要す
る時間を短縮できる。(Function) According to the present invention, a large number of independent circuits are grouped into several blocks, the circuits in the blocks are connected in series, and an overcurrent is applied to each block to melt down defective parts of the circuit. Therefore, the number of overcurrent energizations can be reduced, and the time required for inspection can be shortened.
また、過電流により欠陥部を溶断するため、検出ミスを
防止でき自動化が可能となる。Additionally, since the defective part is blown out by overcurrent, detection errors can be prevented and automation possible.
なお、通常、ブロックは複数個となるが、回路が少ない
場合には全体を直列接続して１ブロツクとしてもよい。Note that normally there are a plurality of blocks, but if the number of circuits is small, they may all be connected in series to form one block.
（実施例） 以下、本発明の実施例を図面に基づいて説明する。(Example) Embodiments of the present invention will be described below based on the drawings.
第２図において、１はプリント配線板であり、互いに電
気的に独立して多数の回路２が印刷されている。In FIG. 2, 1 is a printed wiring board, on which a large number of circuits 2 are printed electrically independent of each other.
また、第３図において、３はビンボードであり、回路２
のランド４の位置に対応して接触ピン５が貫設されてい
る。そして両端の接触ピン５を除いて、互いに隣り合う
接触ピン５が接続コード６により一つおきに電気的に接
続されている。In addition, in FIG. 3, 3 is a bin board, and the circuit 2
A contact pin 5 is provided through the contact pin 5 corresponding to the position of the land 4 . Except for the contact pins 5 at both ends, every other contact pin 5 adjacent to each other is electrically connected by a connection cord 6.
第１図は、本発明方法により不良品を検出する場合の回
路図を示す。プリント配線板１の回路２は、ピンボード
３の接触ピン５を回路２のランド４に接触することによ
り、複数個が直列接続され、ブロック７−１〜７−５に
区分けされている。端部に設けられた接触ピン５は、一
方は電源８に接続され、他方は切替スイッチ９の一端に
接続されている。また、切替スイッチ９の他端は電ｉ［
８に接続されている。FIG. 1 shows a circuit diagram when defective products are detected by the method of the present invention. A plurality of circuits 2 of the printed wiring board 1 are connected in series by contacting the contact pins 5 of the pin board 3 with the lands 4 of the circuits 2, and are divided into blocks 7-1 to 7-5. One end of the contact pin 5 provided at the end is connected to a power source 8, and the other end is connected to one end of a changeover switch 9. In addition, the other end of the changeover switch 9 is connected to the electric current i[
8 is connected.
上記実施例に基づいて不良品を検出するには、先ず、切
替スイッチ９をブロック７−１に接続して過電流を所定
時間、ブロック７−１に流す。この時、ブロック７−１
内の回路２が一つでも溶断すれば、不良品として処理す
る。ブロック７−１内の回路２が溶断されない場合には
、切替スイッチ９をブロック７−２に接続して同様な処
理を行う。以下、ブロック７−５まで上記処理を繰り返
す。To detect a defective product based on the above embodiment, first, the changeover switch 9 is connected to the block 7-1 and an overcurrent is applied to the block 7-1 for a predetermined period of time. At this time, block 7-1
If even one of the circuits 2 inside is fused, it is treated as a defective product. If the circuit 2 in the block 7-1 is not fused, the changeover switch 9 is connected to the block 7-2 and similar processing is performed. Thereafter, the above processing is repeated up to block 7-5.
すなわち、上記実施例によれば、互いに独立した回路２
を複数個まとめて１ブロツクにし、接触ピン５を用いて
このブロック内の回路２を直列接続し、−回の通電によ
り１ブロツク内の回路２の欠陥部を検出できる。そのた
めに、欠陥部の検出に要する時間は大幅に短縮され、検
出ミスもなくなる。That is, according to the above embodiment, the mutually independent circuits 2
A plurality of circuits 2 are combined into one block, and the circuits 2 in this block are connected in series using the contact pins 5, and a defective part of the circuit 2 in one block can be detected by energizing - times. Therefore, the time required to detect defective parts is significantly shortened and detection errors are eliminated.
例えば、独立した回路を３００個有するプリント配線板
を検査する場合、回路を１５個づつ２０ブロツクに分け
る。１５個の回路を直列接続すると、抵抗はほぼ０．５
〜１〔Ω）となる。それ故、電圧１５（Ｖ）の定電圧定
電流の電源を用いて、１ブロツク当たり１５〜３０ （
Ａ）の過電流を最大０．１秒間流す。切替スイッチの切
替えに要する時間は、半導体を用いた場合には、通常、
最大０．０５秒間である。従って、２０ブロツクの検査
に要する時間は（０，１＋０．０５）ｘ２０−３秒であ
る。これに対して、３００個の回路を個個に過電流を流
して検査する場合には、回路の通電時間だけでも３０秒
かかる。For example, when inspecting a printed wiring board having 300 independent circuits, the circuits are divided into 20 blocks of 15 each. When 15 circuits are connected in series, the resistance is approximately 0.5
~1 [Ω]. Therefore, using a constant voltage constant current power supply with a voltage of 15 (V), 15 to 30 (
Apply the overcurrent of A) for a maximum of 0.1 seconds. When using semiconductors, the time required to change the changeover switch is usually
The maximum time is 0.05 seconds. Therefore, the time required to inspect 20 blocks is (0,1+0.05)x20-3 seconds. On the other hand, when inspecting 300 circuits by individually applying overcurrent to them, it takes 30 seconds just to energize the circuits.
（発明の効果）
以上の通り、本発明によれば、回路を複数のブロックに
区分けし、ブロック毎に過電流を流して欠陥部を溶断す
る方法により不良品の検査を行なっているために、検査
時間を大幅に短縮でき、かつミスなく検査でき、自動化
の可能なプリント配線板の検査方法が得られる。(Effects of the Invention) As described above, according to the present invention, defective products are inspected by dividing the circuit into a plurality of blocks and blowing out defective parts by passing an overcurrent in each block. A printed wiring board inspection method that can significantly shorten inspection time, perform error-free inspection, and can be automated is obtained.
第１図はプリント配線板の平面図、第２図はピンボード
の側面断面図、第３図は本発明の実施例の回路図を示す
。
１・・・プリント配線板、 ２・・・回路、７−１〜７
−ｎ・・・ブロック、 ８・・・電源。
特許出願人 日立コンデンサ株式会社
第１図
□第２図 第３図FIG. 1 is a plan view of a printed wiring board, FIG. 2 is a side sectional view of a pin board, and FIG. 3 is a circuit diagram of an embodiment of the present invention. 1... Printed wiring board, 2... Circuit, 7-1 to 7
-n...Block, 8...Power supply. Patent applicant Hitachi Capacitor Co., Ltd. Figure 1 □ Figure 2 Figure 3
Claims (1)
断するプリント配線板の検査方法において、任意個数の
回路を直列接続してブロック化し、該ブロックに過電流
を流して前記回路の欠陥部を溶断することを特徴とする
プリント配線板の検査方法。(1) In a method for inspecting a printed wiring board in which an overcurrent is applied to a circuit on the printed wiring board to fuse out a defective part, an arbitrary number of circuits are connected in series to form a block, and an overcurrent is applied to the block to detect defects in the circuit. A method for inspecting a printed wiring board, the method comprising melting a portion of the printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60076669A JPS61235765A (en) | 1985-04-12 | 1985-04-12 | Inspecting method for printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60076669A JPS61235765A (en) | 1985-04-12 | 1985-04-12 | Inspecting method for printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61235765A true JPS61235765A (en) | 1986-10-21 |
| JPH0469752B2 JPH0469752B2 (en) | 1992-11-09 |
Family
ID=13611820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60076669A Granted JPS61235765A (en) | 1985-04-12 | 1985-04-12 | Inspecting method for printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61235765A (en) |
-
1985
- 1985-04-12 JP JP60076669A patent/JPS61235765A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0469752B2 (en) | 1992-11-09 |
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