JPS6123516B2 - - Google Patents

Info

Publication number
JPS6123516B2
JPS6123516B2 JP15558280A JP15558280A JPS6123516B2 JP S6123516 B2 JPS6123516 B2 JP S6123516B2 JP 15558280 A JP15558280 A JP 15558280A JP 15558280 A JP15558280 A JP 15558280A JP S6123516 B2 JPS6123516 B2 JP S6123516B2
Authority
JP
Japan
Prior art keywords
circuit
pulse
drive
pulse motor
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15558280A
Other languages
Japanese (ja)
Other versions
JPS5696269A (en
Inventor
Akio Nakajima
Tadayasu Machida
Kenji Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP15558280A priority Critical patent/JPS5696269A/en
Publication of JPS5696269A publication Critical patent/JPS5696269A/en
Publication of JPS6123516B2 publication Critical patent/JPS6123516B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04CELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C3/00Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means
    • G04C3/14Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means incorporating a stepping motor
    • G04C3/143Means to reduce power consumption by reducing pulse width or amplitude and related problems, e.g. detection of unwanted or missing step

Description

【発明の詳細な説明】 本発明は電子時計に関し、特にその電気機械変
換機であるパルスモーターの駆動回路の改良に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and more particularly to an improvement in a drive circuit for a pulse motor, which is an electromechanical converter thereof.

電子時計用として使用されている電気機械変換
機には、水晶発振器からの分周信号により強制駆
動されるテンプ及び1ステツプづつ定方向に回転
するパルスモーター等が実用化されている。
BACKGROUND ART Electromechanical converters used in electronic watches include a balance that is forcibly driven by a frequency-divided signal from a crystal oscillator, a pulse motor that rotates one step at a time in a fixed direction, and the like.

一般に腕時計に用いられる電気機械変換機は衡
撃負荷に対する安定度が問題となるが一相のパル
スによるテンプの駆動方式については耐衝撃性を
向上させるために、駆動コイルの誘起電圧により
駆動パルスのパルス巾を制御する方式が提案され
ており一部実用化されている。
Generally, electromechanical converters used in wristwatches have problems with stability against equilibrium loads.However, in order to improve shock resistance, the balance drive system uses single-phase pulses, and in order to improve shock resistance, the drive pulses are controlled by the induced voltage of the drive coil. A method for controlling the pulse width has been proposed and some have been put into practical use.

しかるに一相駆動方式の場合、テンプの場合は
往復運動のうちの片側のみに駆動パルスが印加さ
れるだけであるため、衝撃時にパルス巾が広くな
つても誤動作を起しやすく、多相パルスモーター
の場合は構造上多極化されて1ステツプの回転角
度が小さくなるため誘起電圧が小さくなり充分な
制御作用を行うことができず安定度はあまり良く
なかつた。これらの観点から最大限パルス巾を広
げたパルスを供給して安定度を得ているため消費
電力も大きくなる欠点を有していた。
However, in the case of a single-phase drive system, in the case of a balance wheel, the drive pulse is only applied to one side of the reciprocating motion, so even if the pulse width becomes wide at the time of impact, malfunctions are likely to occur, and multi-phase pulse motors In this case, the structure is multi-polar and the rotation angle of one step becomes small, so the induced voltage becomes small and it is not possible to perform a sufficient control action, resulting in poor stability. From these viewpoints, since stability is obtained by supplying pulses with the maximum pulse width, the power consumption is also increased.

本発明は上述の欠点のない耐衝撃性の良い高安
定な変換機の駆動回路を提供するものである。
The present invention provides a highly stable converter drive circuit with good shock resistance and without the above-mentioned drawbacks.

本発明は二相の駆動パルスによつて駆動される
電気機械変換機の駆動パルスのパルス巾が駆動コ
イルの誘起電圧によつてステツプ状に制御される
ことを特徴とする高安定な時計用電気機械変換機
のク動回路を提供することを目的とする。
The present invention provides a highly stable electric watch characterized in that the pulse width of the drive pulse of an electromechanical converter driven by two-phase drive pulses is controlled in a stepwise manner by the induced voltage of the drive coil. The purpose of this invention is to provide a power circuit for a mechanical converter.

本発明はまた駆動コイルの一端を入力とするイ
ンバーター、及び他の一端を入力とするインバー
ターを有することを特徴とする時計用電気機械変
換機駆動回路を提供することを目的とする。
Another object of the present invention is to provide an electromechanical converter drive circuit for a watch, which is characterized by having an inverter having one end of the drive coil as an input, and an inverter having the other end as an input.

以下実施例について説明する。 Examples will be described below.

第1図a及びbは電気機械変換機の一実施例
で、101はテンワ、102は磁石、103,1
04は駆動コイル、105はヒゲゼンマイ、a,
bは駆動コイル端子であり、a,bに印加される
二相のパルス電圧による電流のため駆動コイルに
発生する磁場によつてテンワに固着された磁石が
力を受けヒゲゼンマイとテンワよりなるテンプは
往復運動を行なう。第2図は電気機械変換機の他
の一実施例で、106は少なくとも2極の磁極を
有する磁石よりなる回転子、107,108は磁
性材よりなる固定子、109は駆動コイル、a,
bは駆動コイル端子であり、a,bに印加される
二相のパルス電圧による電流のため駆動コイルに
発生する磁束を固定子に導いて回転子を定方向に
ステツプ状に回転させるパルスモーターである。
Figures 1a and 1b show an example of an electromechanical converter, in which 101 is a balance wheel, 102 is a magnet, 103, 1
04 is a drive coil, 105 is a balance spring, a,
b is a drive coil terminal, and the magnet fixed to the balance wheel receives a force due to the magnetic field generated in the drive coil due to the current caused by the two-phase pulse voltage applied to a and b, and the balance consisting of the hairspring and balance wheel is performs a reciprocating motion. FIG. 2 shows another embodiment of the electromechanical converter, in which 106 is a rotor made of a magnet having at least two magnetic poles, 107 and 108 are stators made of magnetic material, 109 is a drive coil, a,
b is the drive coil terminal, and it is a pulse motor that rotates the rotor in a fixed direction in steps by guiding the magnetic flux generated in the drive coil to the stator due to the current due to the two-phase pulse voltage applied to a and b. be.

第3図は本発明の電子時計の一実施例で、20
1は水晶発振回路、202は分周回路、203は
パルス選択回路206、パルス変換回路207、
制御回路208を含むパルス巾切換回路、204
は駆動回路、205は検出回路209、復帰手段
210を含む検出記憶回路である。
FIG. 3 shows an embodiment of the electronic watch of the present invention, with 20
1 is a crystal oscillation circuit, 202 is a frequency dividing circuit, 203 is a pulse selection circuit 206, a pulse conversion circuit 207,
Pulse width switching circuit 204 including control circuit 208
205 is a detection storage circuit including a detection circuit 209 and a recovery means 210.

第4図は駆動コイルの状態説明図、第5図、第
6図は電気機械変換機としてテンプを用いた場合
の波形図であり、第5図は定常時、第6図は衝撃
時の状態を示す。第7図、第8図は電気機械変換
機としてパルスモーターを用いた場合の各部の波
形図であり、第7図は定常時、第8図は衝撃時の
状態を示す。
Figure 4 is an explanatory diagram of the state of the drive coil, Figures 5 and 6 are waveform diagrams when a balance wheel is used as an electromechanical converter, Figure 5 is the state at steady state, and Figure 6 is the state at the time of impact. shows. 7 and 8 are waveform diagrams of various parts when a pulse motor is used as an electromechanical converter, with FIG. 7 showing a steady state and FIG. 8 showing a state at an impact.

第3図に於て分周回路202のフリツプフロツ
プ(以下FFと称する)117、FF118の出力
はパルス選択回路206の切換回路124,12
5の各入力となつており、定常時はFF117の
出力がパルス変換回路207のFF120,12
1のリセツト端子に印加されて各出力F1,F2
は短かいパルスφ,φが交互に発生する。
F1はリセツト、セツトフリツプフロツプ126
(以下RS−FFと称する)のR4端子、復帰手段2
10を構成するRS−FF127のS6端子、F2は前
記RS−FF126のS4端子、復帰手段210であ
るRS−FF128のS5端子に接続されている。パ
ルス変換回路207のFF120の他の出力1
制御回路208のFF123の入力及び駆動回路
204のPチヤンネルMOSトランジスタ133
(以下P−ChMOSトランジスタと称する)、FF1
21の他の出力2はFF123の他の入力及びP
−ChMOSトランジスタ135の各ゲートに接続
され、FF123の出力F3NチヤンネルMOSトラ
ンジスタ136、(以下N−ChMOSトランジス
タと称する)3はN−ChMOSトランジスタ13
4の各ゲートに接続されている。駆動コイル13
7はMOSトランジスタの共通ドレインa,b間
に接続され、a端子は検出回路209の誘起電圧
検出インバーター130、b端子は誘起電圧検出
インバーター129の各入力ゲートに接続され、
インバーター129出力はゲート回路131を介
して前記復帰手段210のFF127のR6端子、
インバーター130出力はゲート回路132を介
してFF128のR5端子に接続されている。前記
FF127出力F6はパルス選択回路206の切換
回路125、FF128出力F5は切換回路124
の各入力に接続されている。
In FIG. 3, the outputs of flip-flops (hereinafter referred to as FF) 117 and FF 118 of the frequency dividing circuit 202 are connected to the switching circuits 124 and 12 of the pulse selection circuit 206.
During normal operation, the output of FF117 is input to FF120, 12 of pulse conversion circuit 207.
1, and short pulses φ 1 and φ 2 are alternately generated at each output F 1 and F 2 .
F 1 is reset, set flip-flop 126
(hereinafter referred to as RS-FF) R4 terminal, return means 2
The S 6 terminal and F 2 of the RS-FF 127 constituting the RS-FF 10 are connected to the S 4 terminal of the RS-FF 126 and the S 5 terminal of the RS-FF 128 which is the recovery means 210 . The other output 1 of the FF 120 of the pulse conversion circuit 207 is the input of the FF 123 of the control circuit 208 and the P channel MOS transistor 133 of the drive circuit 204.
(hereinafter referred to as P-ChMOS transistor), FF1
The other output 2 of 21 is the other input of FF123 and P
- Connected to each gate of the ChMOS transistor 135, output F 3 of the FF 123 N-channel MOS transistor 136, (hereinafter referred to as N-ChMOS transistor) 3 is the N-ChMOS transistor 13
It is connected to each gate of 4. Drive coil 13
7 is connected between the common drains a and b of the MOS transistors, the a terminal is connected to the induced voltage detection inverter 130 of the detection circuit 209, the b terminal is connected to each input gate of the induced voltage detection inverter 129,
The output of the inverter 129 is connected to the R6 terminal of the FF 127 of the return means 210 via the gate circuit 131.
The inverter 130 output is connected to the R5 terminal of the FF 128 via a gate circuit 132. Said
The FF127 output F6 is the switching circuit 125 of the pulse selection circuit 206, and the FF128 output F5 is the switching circuit 124.
connected to each input.

まずテンプの場合を考えてみると第5図に於て
まずt=tでφパルスが発生しP−Ch,MOS
トランジスタ133はオンとなる。このときF3
=1であるからN−ChMOSトランジスタ136
はオンであり、駆動回路は第4図(1)の状態とな
り、a端子に駆動電圧が印加されa→bに電流が
流れテンプは駆動力を受ける。一方、φパルス
は復帰手段210のFF127のセツト端子S6
印加されてFF出力はf=1に復帰する。t=t2
でパルスが切れるとF3=0,3=1となりP−
ChMOSトランジスタ133N−ChMOSトラン
ジスタ136はオフ、134はオンとなり、第4
図(2)のようになる。a端子はトランジスタ134
を介して接地され第5図aの如くになるため、検
出回路209の誘起電圧検出用インバーター13
0は動作しない。一方b端子はφパルス印加時
は接地されているが、パルスが切れた直後に接地
が解除され誘起電圧がインバーター129に印加
され、t=t3〜t4で誘起電圧が、インバーターの
しきい値電圧以上となりゲート回路131の出力
dが発生する。ゲート回路131,132は前記
検出回路209の誘起電圧検出インバーター12
9,130が検出する駆動パルスを除いて誘起電
圧のみを復帰手段210のFF127,128の
リセツト入力とするためのものである。
First, considering the case of a balance wheel, in Fig. 5, a φ1 pulse is generated at t=t, and P-Ch, MOS
Transistor 133 is turned on. At this time F 3
= 1, so N-ChMOS transistor 136
is on, the drive circuit is in the state shown in FIG. 4(1), a drive voltage is applied to the a terminal, a current flows from a to b, and the balance receives a driving force. On the other hand, the φ1 pulse is applied to the set terminal S6 of the FF 127 of the return means 210, and the FF output returns to f=1. t= t2
When the pulse is cut off, F 3 = 0, 3 = 1, and P-
ChMOS transistor 133N-ChMOS transistor 136 is turned off, 134 is turned on, and the fourth
It will look like Figure (2). The a terminal is the transistor 134
Since the inverter 13 for detecting the induced voltage of the detection circuit 209 is grounded as shown in FIG.
0 does not work. On the other hand, the b terminal is grounded when the φ1 pulse is applied, but immediately after the pulse is cut off, the grounding is released and an induced voltage is applied to the inverter 129. At t= t3 to t4 , the induced voltage is The voltage exceeds the threshold voltage, and the output d of the gate circuit 131 is generated. The gate circuits 131 and 132 are connected to the induced voltage detection inverter 12 of the detection circuit 209.
This is for using only the induced voltage, excluding the drive pulses detected by FFs 9 and 130, as the reset input for the FFs 127 and 128 of the recovery means 210.

この出力dは、復帰手段210のFF127の
リセツト端子R6に印加され、FF127出力=
0となる。従つてパルス選択回路206の選択ゲ
ート125出力はFF118の出力となるから、
次のφパルスもφパルスと同じ短いパルス巾
のパルスとなる。
This output d is applied to the reset terminal R6 of the FF127 of the recovery means 210, and the FF127 output=
It becomes 0. Therefore, since the selection gate 125 output of the pulse selection circuit 206 becomes the output of the FF 118,
The next φ 2 pulse also has the same short pulse width as the φ 1 pulse.

次にt=t5でφパルスが発生し、P−
ChMOSトランジスタ135はオンとなる。N−
ChMOSトランジスタ134はオンのままである
から、駆動回路204は第4図(3)の状態となり、
b端子に駆動電圧が印加され、b→aに電流が流
れ、テンプは前とは逆方向に駆動力を受ける。一
方φパルスは復帰手段210のFF128のセ
ツト端子S5に印加されてFF出力はe=1に復帰
する。t=t6でパルスが切れるとF3=1,3=0
となり、P−ChMOSトランジスタ135、N−
ChMOSトランジスタ134はオフ、136はオ
ンとなり、第4図(4)のようになる。b端子はトラ
ンジスタ136を介して接地され、第5図bの如
くになるため、誘起電圧検出インバーター129
は動作しない。一方a端子はφパルス印加時は
接地されている。パルスが切れた直後に接地が解
除され誘起電圧がインバーター130に印加さ
れ、t=t7〜t8で誘起電圧がインバーターのしき
い値電圧以上となり、ゲート回路出力Cが発生す
る。FF128はCでリセツトされてe=0とな
り切換回路124出力はFF117出力となり、
次のφは短いパルス巾のパルスとなりまたFF
127はφでセツト、dでリセツトされて=
0となり切換回路125出力はFF117出力と
なり、さらに次のφは短いパルス巾のパルスと
なつている。
Next, at t= t5 , a φ2 pulse is generated, and P-
ChMOS transistor 135 is turned on. N-
Since the ChMOS transistor 134 remains on, the drive circuit 204 is in the state shown in FIG. 4(3),
A driving voltage is applied to the b terminal, a current flows from b to a, and the balance receives a driving force in the opposite direction. On the other hand, the φ2 pulse is applied to the set terminal S5 of the FF 128 of the return means 210, and the FF output returns to e=1. When the pulse ends at t=t 6 , F 3 = 1, 3 = 0
Therefore, P-ChMOS transistor 135, N-
The ChMOS transistor 134 is turned off and the ChMOS transistor 136 is turned on, as shown in FIG. 4(4). Since the b terminal is grounded through the transistor 136, as shown in FIG. 5b, the induced voltage detection inverter 129
doesn't work. On the other hand, the a terminal is grounded when the φ2 pulse is applied. Immediately after the pulse ends, the ground is released and an induced voltage is applied to the inverter 130, and at t= t7 to t8 , the induced voltage becomes equal to or higher than the threshold voltage of the inverter, and a gate circuit output C is generated. FF128 is reset by C and e=0, and the switching circuit 124 output becomes the FF117 output.
The next φ 1 is a short pulse width and FF
127 is set at φ1 and reset at d=
0, the output of the switching circuit 125 becomes the output of the FF 117, and the next φ2 becomes a pulse with a short pulse width.

次に衝撃負荷を受けた場合第6図の如くにな
る。すなわち、FF127出力fはφで1にセ
ツトされるが、誘起電圧が減少してしきい値電圧
以下となりセツトパルスが発生しないため=1
のままであり、切換回路125が切換りFF12
1のR2端子にはFF118出力が印加され、φ
は2倍のパルス巾t13〜t14となる。さらにFF12
8はφにより1にセツトされるがリセツトパル
スが発生しないためe=1のままであり、切換回
路124が切換りFF120のR1端子にはFF11
8出力が印加され、次のφは2倍のパルス巾
t15〜t16となる。パルス巾が2倍となり駆動力が
増加して誘起電圧が前の状態にもどるとt=t17
〜t18でdにリセツトパルスが発生し、=0と
なり次のφパルスは前の状態にもどり、さらに
φパルスも前の状態にもどる。
Next, when an impact load is applied, the result will be as shown in FIG. That is, the FF127 output f is set to 1 at φ 1 , but since the induced voltage decreases and becomes below the threshold voltage, no set pulse is generated, so it becomes =1.
remains as it is, and the switching circuit 125 switches FF12.
FF118 output is applied to the R2 terminal of 1, and φ2
becomes twice the pulse width t13 to t14 . Furthermore FF12
8 is set to 1 by φ2 , but since a reset pulse is not generated, e remains at 1, and the switching circuit 124 switches and the R1 terminal of FF120 is set to FF11.
8 outputs are applied, the next φ 1 is twice the pulse width
It becomes t15 to t16 . When the pulse width doubles, the driving force increases, and the induced voltage returns to its previous state, t=t 17
At ~ t18 , a reset pulse is generated at d, which becomes =0, and the next φ2 pulse returns to the previous state, and furthermore, the φ1 pulse also returns to the previous state.

次にパルスモーターの場合を考えてみる。誘起
電圧波形のいく分異なるのみで他はほとんどテン
プの場合と同じであるが、第7図に於てt=t31
でφパルスが発生し、駆動コイルのa端子に駆
動電圧が印加されa→bに電流が流れ固定子10
7,108は励磁され、回転子106は右方向に
180゜回転し一定時間自由減衰振動して停止す
る。一方φパルスは、復帰手段210のFF1
27のセツト端子S6に印加されてFF出力は=
1に復帰する。φが切れた直後にa端子は接地
され、b端子は接地解除され、回転子の自由減衰
にともなう誘起電圧が検出回路209の検出イン
バーター129に印加され、t=t33〜t34で誘起
電圧が、検出インバーターのしきい値電圧以上と
なりゲート回路出力dが発生する。FF127出
力は0にリセツトされ次のφは短かいパルス
巾となる。回転子はt=t35でほゞ静止安定す
る。次にt=t36でφパルスが発生し、駆動コ
イルのb端子に駆動電圧が印加されb→aに電流
が流れ前と逆励磁されて同方向に180゜回転す
る。一方、φパルスは復帰手段210のFF1
28のセツト端子S5に印加されてFF出力はe=
1に復帰する。t=t37でパルスが切れるとb端
子は接地され、a端子は接地解除され、誘起電圧
が検出インバーター130に印加され、t=t38
〜t39で誘起電圧が検出インバーターのしきい値
電圧以上となり、ゲート回路出力cが発生する。
FF128はcでリセツトされてe=0となり切
換回路124出力はFF117出力となり次のφ
は短いパルス巾のパルスとなり、FF127は
φでセツト、dでリセツトされて=0となり
切換回路125出力はFF117出力となり、次
のφは短いパルス巾のパルスとなつている。
Next, consider the case of a pulse motor. The induced voltage waveform is slightly different, but everything else is almost the same as in the case of the balance wheel, but in Fig. 7, t=t 31
A φ1 pulse is generated, a driving voltage is applied to the a terminal of the driving coil, and a current flows from a to b, and the stator 10
7 and 108 are excited, and the rotor 106 moves to the right.
It rotates 180°, oscillates with free damping for a certain period of time, and then stops. On the other hand, the φ1 pulse is FF1 of the return means 210.
Applied to the set terminal S6 of 27, the FF output is =
Return to 1. Immediately after φ1 is cut off, the a terminal is grounded, the b terminal is ungrounded, and the induced voltage accompanying the rotor's free decay is applied to the detection inverter 129 of the detection circuit 209, and the induced voltage is induced at t= t33 to t34 . When the voltage exceeds the threshold voltage of the detection inverter, a gate circuit output d is generated. The FF127 output is reset to 0 and the next φ2 is a short pulse width. The rotor becomes almost stationary and stable at t=t 35 . Next, at t=t 36 , a φ 2 pulse is generated, a driving voltage is applied to the b terminal of the driving coil, and a current flows from b to a, and the coil is reversely excited and rotated 180° in the same direction. On the other hand, the φ2 pulse is FF1 of the return means 210.
28 set terminal S5 , the FF output is e=
Return to 1. When the pulse ends at t=t 37 , the b terminal is grounded, the a terminal is ungrounded, the induced voltage is applied to the detection inverter 130, and t=t 38
At ~ t39 , the induced voltage becomes equal to or higher than the threshold voltage of the detection inverter, and gate circuit output c is generated.
FF128 is reset at c and e=0, and the switching circuit 124 output becomes the FF117 output and the next φ
1 becomes a pulse with a short pulse width, FF127 is set at φ1 , reset at d, becomes 0, and the output of the switching circuit 125 becomes the output of FF117, and the next φ2 becomes a pulse with a short pulse width.

次に衝撃負荷を受けた場合第8図の如く、FF
127出力はφで1にセツトされるが、誘起
電圧が減少して検出回路209の検出用インバー
ターのしきい他電圧以下となりリセツトパルスd
が発生しなくなるため=1にセツトされたまま
となり、切換回路125は切換り、FF121の
R2端子にはFF118出力が印加され、φは2
倍のパルス巾t43〜t44となる。さらにFF128は
φによりセツトされe=1となり誘起電圧が減
少して検出用インバーター130のしきい他電圧
以下となつてリセツトパルスcが発生しなくなる
ためe=1にセツトされたままとなり、切換回路
124が切換りFF120のR1端子はFF118出
力が印加されてφは2倍のパルス巾となり駆動
力が増加するため誤動作を防止できる。負荷が0
になれば誘起電圧は前の状態にもどりdにリセツ
トパルスが発生し=0となりφパルスは前の
状態にもどり、φパルスも前の状態にもどる。
テンプの場合は駆動パルスの直前と直後に誘起電
圧が発生するためパルス巾制御にどちらかを用い
ても良いが、パルスモーターの場合は駆動パルス
の直後に誘起電圧が発生するのみであるためこの
実施例が適している。本願の如く負荷の状態を検
出するのにパルスモータ駆動回路のトランジスタ
を夫々独立に制御するように構成し、回転子の自
由減衰振動時に、前記トランジスタにより駆動コ
イルの一端を電源ラインから切離すことにより、
誘起電圧を大振巾のまま検出するようにしている
ため検出回路が簡単となり、従来、困難とされて
いたパルスモータの負荷状態の検出を適確に行う
ことが可能となつた。
Next, when subjected to impact load, as shown in Figure 8, FF
The 127 output is set to 1 at φ 1 , but the induced voltage decreases and becomes below the threshold voltage of the detection inverter of the detection circuit 209, causing the reset pulse d.
Since no longer occurs, it remains set to 1, the switching circuit 125 switches, and the FF 121
The FF118 output is applied to the R2 terminal, and φ2 is 2
The pulse width is doubled from t 43 to t 44 . Furthermore, the FF 128 is set by φ 2 and becomes e=1, the induced voltage decreases and becomes below the threshold voltage of the detection inverter 130, and the reset pulse c is no longer generated, so e=1 remains set and the switching is performed. The circuit 124 is switched and the output of the FF 118 is applied to the R 1 terminal of the FF 120, and φ 1 becomes twice the pulse width and the driving force increases, thereby preventing malfunction. load is 0
When the voltage becomes 0, the induced voltage returns to the previous state and a reset pulse is generated at d, which becomes 0, the φ2 pulse returns to the previous state, and the φ1 pulse also returns to the previous state.
In the case of a balance wheel, the induced voltage is generated just before and after the drive pulse, so either one can be used for pulse width control, but in the case of a pulse motor, the induced voltage is only generated immediately after the drive pulse, so this Examples are suitable. As in the present application, the transistors of the pulse motor drive circuit are configured to be independently controlled to detect the state of the load, and one end of the drive coil is disconnected from the power supply line by the transistor when the rotor freely damps vibrations. According to
Since the induced voltage is detected with a large amplitude, the detection circuit is simplified, and it is now possible to accurately detect the load condition of a pulse motor, which has been difficult in the past.

本願の如く構成すれば、定常時は変換機の駆動
に必要な最少限のパルス5ミリsec以下の駆動パ
ルスで駆動し、衝撃負荷が加わつた時に5ミリ
sec以上のパルス巾にすることにより、衝撃に打
勝つ駆動力を変換機に与えて誤動作を防止し、衝
撃負荷がなくなれば、又もとの5ミリsec以下の
パルス巾にすることにより、平均消費電流1μA
以下にすることが可能である。
If configured as in the present application, the converter will be driven with a drive pulse of 5 milliseconds or less, which is the minimum pulse required to drive the converter, during normal operation, and when an impact load is applied, the converter will be driven with a drive pulse of 5 milliseconds or less.
By increasing the pulse width to 5 milliseconds or more, we can provide the converter with driving force to overcome the impact and prevent malfunctions, and once the shock load is removed, by reducing the pulse width to the original 5 milliseconds or less, the average Current consumption 1μA
It is possible to do the following.

また駆動コイルの誘起電圧をCMOSインバータ
ーで検出するため、特に変換機に検出コルを設け
るとか、変換機に接続した輪列に接点又は半導体
を設けるとかの検出機構を必要せず、駆動電流検
出ではないため増巾回路は不要であり、消費電流
は無視しうる。このため発振回路、分周回路を含
めた全消費電流を2μA以下とすることが可能で
ある。
In addition, since the induced voltage of the drive coil is detected by a CMOS inverter, there is no need for any detection mechanism such as installing a detection coil in the converter or providing contacts or semiconductors in the wheel train connected to the converter. Since there is no amplification circuit, the current consumption can be ignored. Therefore, it is possible to reduce the total current consumption including the oscillation circuit and the frequency dividing circuit to 2 μA or less.

本実施例では衝撃時に駆動パルス巾が定常時の
2倍になるように設定したが、ステツプ状に任意
のパルス巾に設定することも可能である。
In this embodiment, the drive pulse width is set to be twice as long as during normal operation when an impact occurs, but it is also possible to set the drive pulse width to an arbitrary pulse width in steps.

また本実施例では衝撃時の駆動パルスについて
記述したが、例えばカレンダー表示駆動等のよう
に負荷変動があつた場合にも適用できることは自
明である。
Further, although the present embodiment has been described with respect to the drive pulse at the time of an impact, it is obvious that the present invention can also be applied to a case where there is a load fluctuation, such as when driving a calendar display, for example.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a及びbは電気機械変換機であるテンプ
の一実施例を示す平面図及び側面図、第2図は電
気機械変換機であるパルスモーターの一実施例を
示す平面図、第3図は本発明の電子時計の一実施
例を示す回路図、第4図は駆動コイルの状態説明
図、第5図、第6図は電気機械変換機としてテン
プを用いた場合の各部の波形図、第7図、第8図
はパルスモーターを用いた場合の各部波形図であ
る。 101……テンワ、102……磁石、103,
104,109……駆動コイル、105……ヒゲ
ゼンマイ、106……回転子、107,108…
…固定子、201……発振回路、110……イン
バーター、111……水晶振動子、112……帰
還抵抗、113,114……外付容量、202…
…分周回路、115……インバーター、116,
117,118,119……フリツプフロツプ、
203……パルス巾切換回路、206……パルス
選択回路、207……パルス変換回路、208…
…制御回路、124,125……切換回路、20
4……駆動回路、133,135……P−
ChMOSトランンジスタ、134,136……N
−ChMOSトランジスタ、137……駆動コイ
ル、205……検出記憶回路、209……検出回
路、210……復帰回路、129,130……検
出用インバーター、131,132……ゲート回
路。
1A and 1B are a plan view and a side view showing an embodiment of a balance wheel which is an electromechanical converter, FIG. 2 is a plan view showing an embodiment of a pulse motor which is an electromechanical converter, and FIG. is a circuit diagram showing one embodiment of the electronic timepiece of the present invention, FIG. 4 is a state explanatory diagram of a drive coil, FIGS. 5 and 6 are waveform diagrams of various parts when a balance wheel is used as an electromechanical converter, FIGS. 7 and 8 are waveform diagrams of various parts when a pulse motor is used. 101... Balance wheel, 102... Magnet, 103,
104, 109... Drive coil, 105... Balance spring, 106... Rotor, 107, 108...
... Stator, 201 ... Oscillation circuit, 110 ... Inverter, 111 ... Crystal resonator, 112 ... Feedback resistor, 113, 114 ... External capacitor, 202 ...
...Frequency dividing circuit, 115...Inverter, 116,
117, 118, 119...flip flop,
203...Pulse width switching circuit, 206...Pulse selection circuit, 207...Pulse conversion circuit, 208...
...Control circuit, 124, 125...Switching circuit, 20
4...Drive circuit, 133, 135...P-
ChMOS transistor, 134, 136...N
- ChMOS transistor, 137... Drive coil, 205... Detection storage circuit, 209... Detection circuit, 210... Recovery circuit, 129, 130... Detection inverter, 131, 132... Gate circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 発振回路、分周回路、パルスモータ駆動回
路、駆動コイル及び回転子を含むパルスモータ、
前記パルスモータへの駆動パルス印加終了後の前
記回転子の自由減衰振動にともなつて駆動コイル
に発生する誘起電圧を検出する検出回路、駆動力
の異なる複数の駆動パルスを発生するパルス変換
回路、前記検出回路によつて制御され、パルス変
換回路の出力パルスをパルスモータ駆動回路に選
択供給するためのパルス選択回路を備えた電子時
計において、前記パルスモータ駆動回路は夫々独
立に制御される複数のMOSトランジスタにより
構成されると共に前記パルスモータ駆動回路を構
成する夫々のMOSトランジスタを制御して前記
駆動コイルの少なくとも一端を電源ラインより実
質的に切り離す制御回路を具備したことを特徴と
する電子時計。
1. A pulse motor including an oscillation circuit, a frequency dividing circuit, a pulse motor drive circuit, a drive coil, and a rotor,
a detection circuit that detects an induced voltage generated in a drive coil due to free damping vibration of the rotor after the application of drive pulses to the pulse motor ends; a pulse conversion circuit that generates a plurality of drive pulses with different drive forces; In an electronic timepiece that is controlled by the detection circuit and includes a pulse selection circuit for selectively supplying output pulses of the pulse conversion circuit to the pulse motor drive circuit, the pulse motor drive circuit has a plurality of independently controlled pulse motor drive circuits. 1. An electronic timepiece comprising a control circuit configured of MOS transistors and controlling each MOS transistor constituting the pulse motor drive circuit to substantially disconnect at least one end of the drive coil from a power supply line.
JP15558280A 1980-11-05 1980-11-05 Electromechanical converter driving circuit for timepiece Granted JPS5696269A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15558280A JPS5696269A (en) 1980-11-05 1980-11-05 Electromechanical converter driving circuit for timepiece

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15558280A JPS5696269A (en) 1980-11-05 1980-11-05 Electromechanical converter driving circuit for timepiece

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP9640576A Division JPS5321966A (en) 1976-08-12 1976-08-12 Electric-mechanical converter driving circuit for timepiece

Publications (2)

Publication Number Publication Date
JPS5696269A JPS5696269A (en) 1981-08-04
JPS6123516B2 true JPS6123516B2 (en) 1986-06-06

Family

ID=15609186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15558280A Granted JPS5696269A (en) 1980-11-05 1980-11-05 Electromechanical converter driving circuit for timepiece

Country Status (1)

Country Link
JP (1) JPS5696269A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0530528U (en) * 1991-09-26 1993-04-23 株式会社ケー・シー・シー・商会 Natsu
JP2011067061A (en) * 2009-09-18 2011-03-31 Sanyo Electric Co Ltd Driver circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5646846B2 (en) 2009-01-28 2014-12-24 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー Driver circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0530528U (en) * 1991-09-26 1993-04-23 株式会社ケー・シー・シー・商会 Natsu
JP2011067061A (en) * 2009-09-18 2011-03-31 Sanyo Electric Co Ltd Driver circuit

Also Published As

Publication number Publication date
JPS5696269A (en) 1981-08-04

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