JPS61234527A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent errors during the mask aligning process by arranging the mask aligning patterns of partly different in shape for each semiconductor product on a part of the masks and effecting the mask aligning of said part of masks by these patterns. CONSTITUTION:When PS and SG are used as common masks regardless of a kind of products and CW(A) and AL(A) used as the masks which are different in pattern contents corresponding to the kind of products are matched, and when CW(B) and AL(B) are matched, PS and SG are the same patterns, but the corresponding masks CW and AL are partly different in shape of pattern between for a product A and a product B. If the mask of AL(B) is going to be used by error in the mask aligning process during manufacturing a product A, at that time, the overlapping of the mask aligning patterns shows disaccord as both masks CW(A) and AL(B) cross with each other partly, thereby perceiving the erroneous use of the mask.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is a method for manufacturing semiconductor devices using a mask alignment pattern that can prevent incorrect use of masks of different types in the mask alignment process in the semiconductor device manufacturing process. This relates to a manufacturing method.

(Prior Art) FIG. 4 shows the flow of a general diffusion process for a gate array having a conventional complementary MO3 structure. In the figure, in response to the n-type semiconductor substrate preparation step 1, an n-channel well formation step 2 is performed, and then a field oxide film formation step 3 is performed.
Then, according to the procedure shown in FIG. 4, a polysilicon gate formation step 4, a p-channel source/drain diffusion layer formation step 5, an n-channel source/drain diffusion layer formation step 6. Step 7 of forming a contact window between the diffusion layer/gate and metal electrode, step 8 of forming a metal electrode, and finally step 9 of forming a window above the input/output pad of the protective film are performed to complete the diffusion step.

The mask used in each of the above steps 2 to 9 has the symbol 2.
Each step corresponds to 0 to 90.

In the gate array, in this process, masks with different patterns are used in the contact window formation step 7 between the diffusion layer gate and the metal electrode, and the metal electrode formation step 8, so that semiconductor products compatible with the same mask are manufactured. . That is, from the mask (mask 20) with the name PW
A common mask is used for each process up to the D mask (mask 60) and the SG mask (mask 90),
For example, when manufacturing product A, CW (
A) Using a mask (mask 70), in step 8
L (A) mask (mask 80) is used.

On the other hand, when manufacturing product B, GW is
(B) mask (mask 70') is used, and in step 8, an AL (B) mask (mask 80') is used. Conventionally, a common pattern for this type of mask alignment has been used for all masks regardless of the type of product as long as the manufacturing process is the same. In other words, the GW (A) mask and the CW (B) mask in Fig. 4, or the A
The shapes of the mask alignment patterns placed on the L (A) mask and the AL (B) mask were completely the same.

(Problems to be Solved by the Invention) In the conventional method, in the mask alignment process, if an operator misreads the product name written on the periphery of the mask or the mask number indicating the mask change history, or the mask Even if a different mask is used by mistake due to contamination, etc., the error may be overlooked until the inspection process after the diffusion process is completed, and the error cannot be detected during the mask matching process. . This will be specifically explained using the manufacturing example shown in FIG. Now, in the manufacturing process of product A, according to the flow of the diffusion process, from process 2 to process 7, masks are sequentially applied pW → oI) - + P 5 -) P D → ND4
In the next step, metal electrode forming step 8, the semiconductor wafer that has been processed up to CW (A) is originally AL (A).
) I mistakenly used the mask of 80 AL (B
) If you end up using a 80' mask, AL (
Since the mask alignment patterns provided for each of A) 80 and AL (B) 80' are the same, AL (B) 80' is also a problem for CW (A) 70 masks in mask alignment work. The worker was unable to match A.
I did not realize that I had mistakenly used L (B) 80' for the AL (A) 80 mask.

The losses caused by the above-mentioned errors will become greater as semiconductor mass production technology improves and it becomes possible to process a large number of wafers at once. In addition, since errors are discovered only after the inspection process begins, the time loss required to redo the diffusion process is enormous.

The purpose of the present invention is to overcome the drawbacks of the prior art and to prevent errors during the mask alignment process.

(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention is to manufacture a semiconductor device that distinguishes each semiconductor product by changing the mask pattern for only some of a plurality of masks. In the method, a mask alignment pattern having a partially different pattern shape for each semiconductor product is arranged on the part of the mask, and the mask alignment of the part of the mask is performed using this mask alignment pattern.

(Function) According to the present invention, in the process of using masks with different contents depending on the type of product, since the shape of the mask matching pattern differs for each product, it becomes impossible to match the masks with different types of masks. Misuse of masks will no longer occur.

(Example) Figures 1 and 2 are schematic diagrams of mask alignment patterns according to an embodiment of the present invention.
Using S40 and 5G90, CW (A
)70 and AL (A) 80, and CW (B) 70' and AL (B) 80'
This is an extracted drawing of the case where each mask is combined with . Figure 1 shows a mask matching pattern dedicated to product A, and Figure 2 shows a mask matching pattern dedicated to product B.
Both figures have the same pattern for PS and SG, but C
Regarding masks compatible with both W and AL, product A and product B have partially different pattern shapes.

That is, in FIGS. 1 and 2, both CW and AL (A
) and (B), the positions of the protrusions are different. Now, while manufacturing product A in the mask alignment process, I accidentally
(B) Assuming that an 80' mask is to be used, the overlap of the mask alignment patterns at this point will be as shown in Figure 3, and CW (A) 70 and AL
(B) Since the patterns of both masks 80' partially intersect and do not match, it is possible to notice misuse of the masks.

In the above example, product A and product B are CW,
Although an example in which products are distinguished by two masks called AL has been described, this can also be applied to the case where products are distinguished by three or more masks.

(Effect of the invention) According to the present invention, for manufacturing a semiconductor device.

When multiple masks are used in series, with different sets for each set, the mask alignment pattern is the same for each series but different for each coarse interval, thereby improving mask alignment during the manufacturing process of semiconductor integrated circuit devices. This has the effect of preventing troubles caused by misuse.

[Brief explanation of drawings]

1 and 2 are plan views of a mask alignment pattern according to an embodiment of the present invention, FIG. 3 is a plan view showing an example of misuse of the same mask alignment pattern, and FIG. 4 is a plan view of a conventional complementary MO
8 is a flowchart of the manufacturing process of an integrated circuit device and a correspondence diagram of masks used in each process. 1... N-type semiconductor substrate preparation step, 2...
n-channel well formation process, 3... field oxide film formation process, 4... polysilicon gate formation process, 5... p-channel source/drain diffusion layer formation process, 6... n-channel source/drain Diffusion layer forming step, 7... Contact window forming step between diffusion layer/gate and metal electrode, 8... Metal electrode forming step, 9... Input/output pad upper window forming step of surface protection film, 20 to 90...Masks for each process. Patent applicant Matsushita Electronics Co., Ltd. Figure 1 Figure 2 S Figure 3

Claims (1)

[Claims] In a method for manufacturing a semiconductor device that distinguishes each semiconductor product by changing a mask pattern for only a part of a plurality of masks, a uniform pattern shape for each semiconductor product is formed on the part of the mask. 1. A method of manufacturing a semiconductor device, comprising arranging mask alignment patterns having different parts, and performing mask alignment of the part of the mask using the mask alignment patterns.