JPS61234437A - Data prefetch device - Google Patents

Abstract

PURPOSE:To perform an execution of microinstruction effectively by providing a memory access instruction of microinstruction with the information regarding whether or not a data buffer is consumed and also providing the data buffer as well as a bus timing control circuit. CONSTITUTION:In case where the memory access instruction from a micro muprogram control part 102 consumes data of a data buffer 101, a decoder 103 causes a prefetch data consumption signal QCOM 111. When a signal EMP 109 representing that the buffer 101 is empty will indicate '0' but not empty, the bus timing control circuit 105 gives a priority to make a mu instruction memory access start earlier than a data prefetch cycle and a data read-write is carried out across a desired register of executing part 104 and an external memory. When the signal EMP 109 represents '1' and the buffer 101 is empty but the signal QCOM 111 represents '1', the circuit 105 has a priority to make the data prefetch cycle start and when its signal QCOM 111 represents '0', its circuit 105 has a priority to make the mu instruction memory access start.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microprogram-controlled data prefetching device having a data buffer.

BACKGROUND OF THE INVENTION Conventional data preemption devices include, for example, Japanese Patent Application Laid-open No. 1986-
It is shown in Japanese Patent No. 48146.

Fig. 2 is a block diagram of this conventional data prefetching device, in which 1 is a data buffer that stores the prefetched instruction or data, and 2 is a microprogram that executes the prefetched microinstruction. Microprogram control section 3 is a decoder that decodes the contents of microinstructions and outputs various control signals for executing microinstructions such as memory access; 4 is prefetched data and data obtained by memory access of microinstructions; 5 is a bus timing control circuit that controls prefetching of data to external memory and memory access of microinstructions; 6 is a prefetching data bus indicating the flow of prefetched instructions or data; 7 is a memory access time of microinstructions; 8 is an external bus, and 9 is an EMP indicating that data buffer 1 is empty.
The signal ("1" when empty, 1o is the RWOP signal (1" when requested) indicating a memory access request of a microinstruction.

In the conventional data prefetching device configured as described above, when the EMP signal is 0'', the bus timing control circuit recognizes that the microinstruction is a memory access instruction (RWO).
When the P signal is 1"), memory access is activated and the execution unit 4
Data is read and written between a desired register and an external memory via a data bus 7. Also, the EMP signal is 1
”, the data pre-fetch cycle is activated and the pre-fetch data is stored in the data buffer 1.

Problems to be Solved by the Invention However, in the above configuration, the data buffer 1
When the bus timing control circuit is empty (when the EMP signal is 11), the bus timing control circuit always starts a data prefetch cycle.
When the microinstruction is a memory access instruction, there is a problem in that the execution of the instruction is delayed regardless of whether the data in the data buffer 1 is consumed or not.

In view of the above, an object of the present invention is to provide a data prefetching device that can efficiently execute microinstructions.

Means for Solving the Problems The present invention is a data prefetching device that includes information as to whether or not a data buffer is consumed by a memory access command of a microinstruction, a data buffer, and a bus timing control circuit.

According to the above-described structure, even if the microinstruction is a memory access instruction when the data buffer is empty, if the memory access instruction does not consume the data buffer, the memory access instruction is transferred to the bus timing control circuit. Embodiment FIG. 1 is a block diagram of a data preemption device according to an embodiment of the present invention. In the figure, for the same functions as those in FIG. 2, only the corresponding numbers are shown and the explanation is omitted. 101 in Figure 1 is 1 in Figure 2, 104 is 4, 1
06 becomes 6, 107 becomes 7, 108 becomes 8, 109 becomes 9
, 110 corresponds to 1o, respectively. In Figure 2, 1
02 is a microprogram control unit that includes information as to whether or not the data in the data buffer 1o1 is consumed in the microinstruction of the memory access instruction; 103 is a microprogram control unit that has the functions of the decoder 3 shown in FIG. When a memory access command consumes data in the data buffer 101, a decoder 105 generates a prefetch data consumption signal, and a decoder 105 dynamically generates a data prefetch signal according to the state of the prefetch data consumption signal even when the EMP signal 109 is "al". Bus timing control circuit with function to change cycle and memory access priority, 1
11 is the prefetch data consumption signal QCOM.

The operation of the data prefetching device of this embodiment configured as described above will be described below.

When the EMP signal 109 is o'', the bus timing control circuit 105 gives priority to the data prefetch cycle and starts the memory access of the microinstruction, as in the conventional operation, and connects the desired register of the execution unit 104 with the external Data is read and written between memories via the data bus 107. Also, when the EMP signal 109 is 1'', the bus timing control circuit 105 starts the data prefetch cycle with priority when the OCOM signal 111 is 1#. , QCOM signal 111
When is 0'', priority is given to microinstruction memory access.

As described above, according to this embodiment, information on whether or not a data buffer is consumed is added to the memory access instruction of a microinstruction, and a decoder that interprets this information and a decoder that interprets this information, By providing a bus timing control circuit that dynamically changes memory access priorities, unnecessary waiting for execution of memory access instructions can be prevented.

As described in detail, according to the present invention, memory access instructions that do not consume data buffers are not made to wait for data fetch cycles, and the arithmetic processing speed can be improved. is big.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data prefetching device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional data prefetching device. 101...-Thetaha7a, 102...
... Microprogram control section, 103 ... Decoder, 104 ... Execution section, 105 ...
・Bus timing control unit, 106...preemption data bus, 107...data bus, 108...
...External bus, 1o9...Data buffer empty signal (EMP), 11Q...Memory access request signal (RWOP), 111...Data buffer consumption signal (QCOM) ). Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 8 Cleave part bus

Claims (1)

[Claims] A data buffer for storing prefetched data, a first signal indicating that the data buffer is empty, a microinstruction having information as to whether the memory access instruction consumes the data buffer, and the microinstruction. a decoder for interpreting and generating a second signal indicative of a memory access request and a third signal indicative of consuming the data buffer; and data prefetching and the microinstruction according to the first, second, and third signals. and a bus timing control circuit that dynamically changes the priority of memory access in the data buffer, and is characterized in that even if the data buffer is empty, memory access instructions that do not consume data in the data buffer are executed with priority. data prefetch device.