JPS61234054A - Integrated semiconductor device - Google Patents

Abstract

PURPOSE:To prevent wirings from being stepwisely disconnected by leading aluminum wirings from the contact of a function element so as not to cross an etched groove (e.g., in parallel), and externally leading it at the position without etched groove from a single crystal silicon island. CONSTITUTION:The conventional manufacturing process can be used up to the steps before forming aluminum wirings 11. The wirings 11 led from a function element are led laterally along the insular wall of a single crystal silicon island 2, and externally led from the island 2 at the position not extended out of the islands of diffused patterns 7-9. Since the wirings 11 do not cross the etched groove, the wirings 11 are not stepwisely disconnected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor device in which a plurality of functional elements are highly integrated on a dielectric isolation substrate in which a plurality of single-crystal silicon island regions are isolated from each other and supported and fixed with polycrystalline silicon. In particular, the present invention relates to an integrated semiconductor device in which disconnection of lead wiring from a single functional element is prevented in a semiconductor device having a structure in which a wide pattern extends beyond a single-crystal silicon island region.

The dielectric isolation method is a method of insulating and isolating functional elements using a dielectric film such as a SiOx film.
Compared to junction isolation, it has the drawbacks of a complicated manufacturing process, difficulty in achieving high integration, and high manufacturing costs, but it provides ideal isolation characteristics in terms of parasitic capacitance and dielectric strength. For this reason, it is the most excellent separation method especially when applied to high-voltage, AC circuit ICs, etc.

An integrated semiconductor device using a conventional dielectric isolation substrate will be explained with reference to FIG. 1 and FIG. 2, which is an enlarged sectional view thereof, and problems with the conventional technology will be described.

A dielectric isolation substrate 1 includes a plurality of single crystal silicon islands 2 separated from each other by 5iOa films 3, and the entire island is supported and fixed by polycrystalline silicon 5. Desired functional elements are formed in these single crystal silicon islands 2 by diffusing predetermined impurities in a predetermined pattern.

If the dielectric isolation method is adopted, the degree of integration cannot be increased very much due to its structure, but it is desirable to configure functional elements within the small single crystal silicon island 2 in order to obtain an inexpensive semiconductor device.

The isolation grooves 4 of the dielectric isolation substrate 1 are formed by anisotropically etching an n-type silicon wafer in 100 directions, but it is difficult to obtain high dimensional accuracy.

In particular, in order to obtain a thick monocrystalline silicon island 2 in the vertical direction, the separation trenches 4 must be formed deeply, resulting in poor dimensional accuracy.

Further, the dielectric isolation substrate 1 is formed by polishing or etching the main surface side of single crystal silicon to separate it into individual single crystal silicon islands 2, but dimensional accuracy may be affected due to wafer curvature and instability of polishing accuracy. The uniformity and reproducibility within the wafer are extremely poor. Furthermore, the alignment of the dielectric isolation substrate 1 and the diffusion patterns (N+ diffusion pattern 8, P diffusion pattern 9, etc.) is formed at the same time as the 5-separation groove 4. In addition, since alignment marks (not shown) appearing on the main surface of the polishing machine are used, alignment deviations of 5 to 10 μm often occur.

On the other hand, in order to obtain a high degree of integration, it is necessary to form functional elements close to the island wall of the single crystal silicon island 2. Therefore, the design is such that the diffusion pattern approaches the island wall. Therefore, if the dielectric isolation substrate 1 lacks dimensional accuracy, the diffusion pattern may protrude from the single crystal silicon island 2. When the diffusion pattern protrudes from the single-crystal silicon island region 2, when a diffusion window is etched in the 5iOi film 6 for passivation on the element surface, the 5iOz film 3 for isolation is simultaneously etched.
is etched, creating an etch groove 12.

The isolation 5iOa film 3 is formed vertically with an inclination of about 53 degrees inward from the main surface of the wafer, and once etched, it hardly grows in the vertical direction even during subsequent oxidation. Therefore, this portion remains etched and, conversely, a 5-ins film grows in the diffusion window. Therefore, the etched groove 12 becomes deeper. Also, etch groove 1
The depth of 2 increases as overetching and pattern protrusion during etching are repeated.

In recent years, elements with high reverse breakdown voltage have been required, and the passivation film tends to be thicker, and accordingly, the passivation film tends to be deeper than the etched groove 12. As a result, the Afi wiring 11 for taking out from the contact window 10 of the functional element (
It is shown with hatching in the plan view. ) has started to break on this etched groove, a so-called breakage accident.

Generally, glass flow of a PSG film, spin-on glass, etc. are applied to flattening the stepped portion. 1st
．． 7 in FIG. 2 is a pattern for alleviating the step difference. This planarization technique is extremely effective for shallow steps such as ICs, but deep and narrow etch grooves 12 cannot be easily improved by applying the above-described planarization technique.

If you try to arrange functional elements so that they do not protrude outside the single-crystal silicon island in order to avoid the occurrence of stepped portions, you will have to design with a fairly large dimensional margin in mind, which will significantly degrade the degree of integration. Become.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated semiconductor device that improves the above-mentioned drawbacks and prevents disconnection of wiring.

The present invention confirms that the disconnection of the lead-out wiring from the functional element is caused by a break in the etch groove caused by the protrusion of the diffusion pattern, and provides means for eliminating this break.

The means of the present invention for eliminating step breakage is to prevent the AΩ wiring from the contact portion of the functional element from crossing the etched groove (for example,
(parallel to this), and is drawn out from the single-crystal silicon island at a position where there are no etched grooves.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

Next, one embodiment of the present invention will be described with reference to FIG. The steps before forming the AI2 wiring 11 are the same as the conventional manufacturing process.The AQ wiring 11 taken out from the 0 functional element is drawn out laterally along the island wall of the single crystal silicon island 2, and is formed into a diffusion pattern. , 8.9, and is pulled out from the single crystal silicon island 2 at a position that does not protrude to a height of 8.9.

In this embodiment, since the AQ wiring 11 does not cross the etch groove, disconnection due to a break in the wiring 11 does not occur. but,
In this embodiment, the lead-out wiring cannot be drawn out at the shortest distance, so there is some margin for wiring.

As described above, according to the present invention, in a highly integrated semiconductor device in which functional elements are arranged at high density on a dielectric isolation substrate and a diffusion pattern protrudes from a single crystal silicon island region, there is a step in the lead-out wiring from the functional elements. An integrated semiconductor device without disconnection due to cuts can be obtained.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of a conventional integrated semiconductor device. The same figure (b) is the equivalent circuit diagram, and Figure 2 is the ■-■ of Figure 1.
FIG. 3 is a partially enlarged longitudinal sectional view taken along the cutting line, and is a plan view of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Dielectric isolation substrate, 2... Single crystal silicon island region, 3... 5ins film for isolation, 7... Pattern for level difference mitigation. 1st prisoner

Claims (1)

[Claims] 1. On the main surface of a plurality of single-crystal silicon island regions provided on a polycrystalline silicon support through island walls of a dielectric film, a diffusion pattern of functional elements constituting a circuit forms a part of the single-crystal silicon island. In the case where the wiring is formed protruding from the single-crystal silicon island region, it is characterized in that the lead-out wiring of the functional element is led out from the single-crystal silicon island region at a location apart from the portion beyond the island wall of the diffusion pattern. Integrated semiconductor device.