JPS61233497A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To facilitate setting of the capacitance of a reference storage element by constituting the capacitance of the reference storage element while plural capacitors are connected in series. CONSTITUTION:Electrodes 4'', 4''' form capacitors 9, 10 with electrodes 16, 17 respectively so as to form the same capacitance as the capacitance of the storage element and the capacitors 9, 10 are connected in series. That is, the capacitance of the two capacitors 9, 10 connected to a transistor 8 of the reference storage element have the same capacitance as that of the storage element. The ratio of the capacitor CS of the storage element to the capacitor CR of the reference storage element is varied less from the setting value with respect to the variance in the shape, thickness (manufacturing tolerance) because the shape of the capacitors of the reference storage element and the storage element is nearly identical and an integrated circuit with a broad manufacture margin is manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and in particular to a dynamic R
The present invention relates to a reference storage element of an AMfi storage device.

(Prior art) MO8 dynamic RAM (hereinafter referred to as 1-Tra) composed of one transistor and one capacitor
FIG. 3 shows an equivalent circuit of a part of the memory element.

In FIG. 3, digit lines l are connected to both sides of each sense amplifier 3, one reference memory element 12 and a plurality of memory elements 13 are connected to each digit line l, and one reference memory element 12 and a plurality of memory elements 13 are connected to each digit line l. A word line 2 is connected to the gates of the transistors forming the transistor 13.

Therefore, two reference storage elements 12 and a plurality of storage elements 13 are connected to one sense amplifier 3.

4 and 5 are a plan view of the memory element 13 and a reference memory element, respectively, in which the electrode 14 or 15 connected to the digit line 1 and the electrode 4 form a capacitor.

Capacitance Cs of the capacitor of the memory element 13 The capacitance CR of the capacitor of the memory element 12 for the 7th arrangement is 1-Trf
In the dynamic RAM of i, Os:cR is set to a value of around 221. In the conventional semiconductor device, the area of the capacitor portion of the reference memory element 12 is determined by the area of the memory element 13.
The ratio of capacitance Cs to CR was achieved by setting the area to be approximately one-half of the area of the capacitor.

(Problems to be Solved by the Invention) In recent years, as the capacity of memories has increased, the area of the storage element and the capacitor of the storage element have become extremely small. In particular, the area of the capacitor of the reference storage element is extremely small.

Therefore, in the conventional semiconductor memory device described above, the ratio of the free capacitances Cs and CR deviates from the set value due to variations in the formation of each pattern using photoetching, such as variations in field width, dimensions of capacitor electrodes, etc. It has started to have an impact on yield and operating margin.

Furthermore, in recent years, a 1-Trfi memory element in which a capacitor is formed in a groove on a substrate 6 as shown in Fig. m6 has been developed. However, the conventional setting of the ratio of Cs and cR by area is very difficult because the accuracy of the groove depth is poor. In Fig. 4, 4' is a capacitor 4.6 made of polysilicon.
, silicon substrate, 7 is 8i0s.

(Means for Solving the Problems) The semiconductor memory device of the present invention includes a memory element in which one end of one capacitor is connected to a digit line via a switching circuit controlled by a word line signal, and a plurality of capacitors. The reference storage element includes a reference storage element, one end of which is connected in series to a digit line via an opening/closing circuit controlled by a word line signal.

(Example) The present invention will be explained below using examples.

FIG. 1 shows an equivalent circuit of a reference storage element according to one embodiment of the present invention. FIG. 2 is a plan view of the reference memory element shown in FIG. 1. 4IP, 4I in Figure 2
I is a capacitor electrode of a reference storage element made of polysilicon, and 2 is a word line made of polysilicon. 16 is a capacitor electrode connected to digit @1 and made of a diffusion layer η), 17 is a capacitor electrode made of a diffusion layer and is connected to the electrode 4'' by a contact portion 11.Each electrode 41°4# is connected to each electrode 16s17. Forms capacitor 9 #10, and capacitor 9゜1
0 is formed to have the same capacity as the capacitor of the memory element 13 shown in FIG. 4, and the capacitors 9 and 10 are connected in series.

In other words, the two capacitors 9 and 10 connected to the transistor 8 of the reference memory element have the same capacitance as the capacitor of the memory element, and C1=Cz=
Cs (Ct-Cz also indicates the capacitance of a capacitor of 9°100). Therefore, the capacitor 9 of the reference storage element,
The equivalent capacity of 10 is CR.

Therefore, the capacitance Cs of the capacitor of the memory element and the capacitance ftCR of the reference memory element can be set accurately without being influenced by the structure and shape of the capacitor such as the previous structure capacitor.

In other words, since the shapes of the reference storage element capacitor and the storage element capacitor are almost the same, the ratio of capacitance ftCs and cR is unlikely to change from the set value due to manufacturing changes such as shape and film thickness. , it is possible to manufacture integrated circuits with wide manufacturing margins.

(Effects of the Invention) As explained above, the present invention provides a degree of freedom in the area and shape of the reference memory element by configuring the capacitance of the reference memory element by connecting a plurality of capacitors in series. It becomes easy to set the capacitance value of the memory element. In addition, if a capacitor of almost the same shape as the memory element capacitor is connected in series as the reference memory element, deviations from the set value in the ratio of the capacitance of the memory element and the reference memory element due to manufacturing variations can be minimized. It is possible to realize a semiconductor circuit with a wide operating margin.

[Brief explanation of the drawing]

1 and 2 are an equivalent circuit diagram and a plan view of a reference memory element according to an embodiment of the present invention, FIG. 3 is a circuit diagram of a part of a conventional semiconductor memory device, and FIG. 4 is a circuit diagram of a part of a conventional semiconductor memory device.
: A plan view of the memory element 13 shown in FIG. 3, and FIG.
61st plan view of the reference storage element 12 shown in the figure.
1 is a tffi plane view of a memory element having a trench structure capacitor. 1... Digit -12... Word line, 3... Sense amplifier, 4... Capacitor electrode, '6...81 board ,7...
・Sin, 8...Transistor. 9.10...Capacitor, 11...Diffusion layer and polysilicon contact part. Figure 2

Claims (1)

[Claims] A storage element that connects one end of one capacitor to a digit line via a switching circuit controlled by a word line signal, and one end of a series connection of multiple capacitors connected to a digit line via a switching circuit controlled by a word line signal. A semiconductor memory device comprising a reference memory element connected to a digit line.