JPS61232680A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable to accurately control the gate length of the first polycrystalline silicon to the prescribed length by forming the first silicon in a gate electrode shape, then oxidizing it with the second polycrystalline silicon remaining on the side, and forming a high melting point metal silicide on the first silicon. CONSTITUTION:The second polycrystalline silicon layer 9 is entirely grown, and anisotropically etched to allow the layer 9 to remain only on the side of the first polycrystalline silicon layer 4. It is oxidized in a steam atmosphere, the layer 9 is at least all oxidized, and altered to a silicon oxide 9a. After a silicon nitride film 5 and a silicon oxide film 6 on the layer 4 are then removed, a high melting point titanium film 10 is coated on the entire surface. This is heat treated to silicify the film 10 at the portion contacted with the upper surface of the layer 4, thereby selectively forming a titanium silicide film 11.

Description

Detailed Description of the Invention 5 [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having an MO8 type field effect transistor, and in particular, a gate electrode composed of two layers of high melting point metal silicide and polycrystalline silicon. The present invention relates to a method of manufacturing a semiconductor integrated circuit device.

[Conventional technology]

With the demand for higher integration and higher speed operation of semiconductor integrated circuit devices, MO8m field effect transistors (hereinafter referred to as MO8m field effect transistors)
The resistance of polycrystalline silicon, which forms the gate electrode of a type 8 transistor (referred to as an 8-type transistor), could no longer be ignored, and a two-layer gate electrode structure in which high-melting point metal silicide was integrally formed on polycrystalline silicon was proposed. ing.

FIGS. 2A to 2D are diagrams illustrating a conventional method for forming this type of gate electrode.

That is, as shown in FIG. 4, after forming the field insulating film 22 and the insulating film 23 on the silicon substrate 210,
A polycrystalline silicon layer 24 is grown, a silicon oxide film 25 is formed on its surface, and a silicon nitride film 26 is further grown. Then, as shown in the same figure (B), the photoresist film 2
The polycrystalline silicon layer 24, the silicon oxide film 25, and the silicon nitride film 26 are patterned into the shape of a gate electrode using a photoetching technique using 7, and a source/train region 2 is formed on the silicon substrate 21 by a self-alignment method or the like.
form 8.

Next, as shown in FIG.
form a. Then, by removing the silicon nitride film 26 on the polycrystalline silicon 24 and lightly etching the silicon oxide film, the thin silicon oxide film 25 on the polycrystalline silicon 24-top is removed first. The upper surface of polycrystalline silicon 25 is exposed.

By applying a high melting point metal to the entire surface, heat-treating it to form a metal silicide 30 on the polycrystalline silicon 24, and then removing the unreacted metal, as shown in the figure (to). A two-layer gate electrode or MO8 type transistor consisting of polycrystalline silicon 24 and metal silicide 30 can be manufactured.

[Problems to be Solved by the Invention] In the conventional manufacturing method described above, the silicon oxide film 24a, which serves as a gate electrode to protect the side surface of the polycrystalline silicon 24 from the next process, is As mentioned above, since the polycrystalline silicon 24 itself is formed by oxidation,
The long gate length of polycrystalline silicon becomes short due to oxidation, and the controllability of the gate length and the controllability of the characteristics of the MO8 type transistor become worse. In particular, when the gate length becomes about 1.0 μm, this influence becomes extremely large.

Also, by this oxidation treatment, the interface between the polycrystalline silicon 24 and the silicon substrate 21, and the polycrystalline silicon 24
There is also the problem that the oxide film 24a sinks in at the interface between the gate electrode and the silicon nitride film 26, causing the gate electrode to curve and making it impossible to obtain the desired characteristics.

[Failure to solve the problem]

In the method of manufacturing a semiconductor integrated circuit device of the present invention, after forming a first polycrystalline silicon in the shape of a gate electrode, a second polycrystalline silicon is deposited on the entire surface and anisotropically etched to form the first polycrystalline silicon. a step of leaving second polycrystalline silicon only on the side surfaces of the polycrystalline silicon, a step of oxidizing at least this remaining second polycrystalline silicon to convert it into silicon oxide, and a step of covering the entire surface with a high melting point metal film. The method includes a step of depositing and heat-treating the same to form a metal silicide on the first polycrystalline silicon, and a step of removing the unreacted metal film.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1O) are cross-sectional views showing an embodiment of the present invention according to the manufacturing process, and this example shows an example of manufacturing an N-channel MO8 type transistor.

First, as shown in FIG. 1A, a field insulating film 2 and a gate insulating film 3 are formed on a P-type silicon substrate 1 using silicon oxide films, respectively. On top of that, a first polycrystalline silicon layer 4 constituting the lower layer of the two-layer gate electrode is grown to a thickness of several thousand amps by CVD, and its surface is oxidized to form a
A silicon oxide film 5 of approximately 0 OA is formed, and a silicon nitride film 6 of 20 OA is further formed thereon by CVD. Note that phosphorus is introduced as an impurity into the first polycrystalline silicon layer 4 to lower the resistance.

Next, as shown in FIG. 6B, for example, a photoresist film 7 is patterned using a phosphorography technique, and using this as a mask, the first polycrystalline silicon layer 4, silicon oxide film 5, and silicon nitride film 6 are dried. These are processed into a shape corresponding to the gate electrode by etching. Thereafter, impurities such as phosphorus are implanted into the silicon substrate 1 by a self-alignment method to form N-type source/drain regions 8.

Subsequently, as shown in FIG.
Thereafter, anisotropic etching is performed using a CCl4 gas. This anisotropic etching is continued until the field insulating film 2 and the gate insulating film 3 are etched, and as a result, as shown in FIG.
is left only on the side surfaces of the polycrystalline silicon layer 4. At this time, the field insulating film 2 and the gate insulating film 3 are hardly etched because the etching speed of the silicon oxide film is slow.

Then, oxidation treatment is carried out for 20 minutes in a steam atmosphere at 900°C to completely oxidize at least the second polycrystalline silicon layer 9 and change it to silicon oxide 9a as shown in FIG. let

Next, after removing the silicon nitride film 5 and silicon oxide 11a6 on the first polycrystalline silicon layer 4, a titanium film 10 of a high melting point metal is deposited by sputtering as shown in the same figure.
Coat the entire surface with a thickness of 000X.

By heat-treating this at 600'O for 1 hour, the portion of the titanium film 10 that contacts the upper surface of the first polycrystalline silicon layer 4 is silicided, and a titanium silicide film 11 is selectively formed.

After that, if the unreacted titanium film 11 is removed using a hydrogen peroxide-based etching solution, a two-layer structure with the titanium silicide film 11 as the upper layer and the first polycrystalline silicon layer 4 as the lower layer is formed as shown in O) in the same figure. N-channel MO with gate electrode 12 of structure
The 8-type transistor is completed.

In the MO8 type transistor formed in this way,
The silicon oxide provided to protect the side surfaces of the first polycrystalline silicon layer 4 as the gate electrode 12 is formed by a second polycrystalline silicon layer 9 that is grown and etched separately from the first polycrystalline silicon layer 4. Since the first polycrystalline silicon layer 4 is formed by oxidation, the Jt of the first polycrystalline silicon layer 4 is not shortened by oxidation, and the gate electrode 12 having the desired gate length can be obtained with high precision.

Furthermore, since the second polycrystalline silicon layer 9 is left only on the side surface of the first polycrystalline silicon layer 4 and is oxidized,
The silicon oxide film does not penetrate between the first polycrystalline silicon layer 4 and the silicon substrate 1 or the silicon nitride film 6, and the first polycrystalline silicon layer 4 does not curve at all. do not have.

In addition to the above-mentioned titanium, high-melting point metals include molybdenum,
Tantalum and tungsten can also be used.

〔Effect of the invention〕

As explained above, in the present invention, after forming the first polycrystalline silicon in the shape of a gate electrode, the second polycrystalline silicon is left only on the side surfaces of the first polycrystalline silicon, and the second polycrystalline silicon is oxidized. Then, a high melting point metal silicide is formed on the first polycrystalline silicon to form the gate electrode, so the gate length of the first polycrystalline silicon can be controlled with high precision to the required length. At the same time, it is possible to prevent the first polycrystalline silicon from bending, etc., and it is possible to manufacture an MO8 type transistor with excellent characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1(A) to 1eJ) are sectional views for explaining the method of the present invention in the order of manufacturing steps, and FIGS. 2(A) to 2(D) are sectional views of the conventional method. 1...P-type silicon substrate, 4...--first
polycrystalline silicon layer, 5...silicon oxide 11
1.6... Silicon nitride film, 8... Source/drain region, 9... Second polycrystalline silicon layer, 10... High melting point metal Membrane (titanium membrane),
11... High melting point metal silicide (titanium silicide), 12... Gate electrode. Sai

Claims (1)

[Claims] 1. Forming the first polycrystalline silicon in the shape of a gate electrode, and depositing the second polycrystalline silicon and anisotropically etching it to form the second polycrystalline silicon only on the side surfaces of the first polycrystalline silicon. a step of leaving polycrystalline silicon, a step of oxidizing at least the remaining second polycrystalline silicon to convert it into silicon oxide, and depositing a high melting point metal film on the entire surface and heat-treating it to form the first 1. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a metal silicide on polycrystalline silicon; and removing unreacted metal film.