JPS61222150A - Method of forming bier on inner layer and flatting said inner insulated layer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a process for manufacturing integrated circuits, and in particular, the present invention relates to a process for manufacturing integrated circuits, and in particular for forming an insulating layer between conductor layers spaced apart or between a conductor and an active region during the manufacture of integrated circuits. Then, when applying the upper conductor layer.

This relates to a method for generating more appropriate surfaces.

<Conventional technology> One of the issues plaguing the semiconductor industry today.

One problem is the step coverage of the metal layer. The term "step" here refers to an area raised by the circuit elements under the insulating layer that separates each circuit element from the metal layer on the substrate, and this step is not covered by the metal layer. The metal layer deposited on such a step will generally be thinner at the deposited location than elsewhere, resulting in electromigration of the metal, melting spots, or Problems such as gaps being formed between parts of the metal layer occur.

In order to eliminate such level differences, various methods for flattening the surface of the intermediate insulating layer have been devised. This flattening technique is known as so-called planarization.

Another problem plaguing the semiconductor industry is how best to apply metallization through vias formed in insulator layers between conductor layers, or to metallize the element areas of circuits. There is a question of whether to go to

In this case, various methods are known to avoid the problem of metal adhering to the sharp upper corner of the via by making the via tapered.

Since a thin metal slope is formed at this upper corner, problems similar to those of the thin metal layer described above arise. Various methods are conventionally known for forming tapered vias and planarizing the intermediate insulating layer. Both use two separate processes.

This unnecessarily complicated the integrated circuit manufacturing process. It is therefore an object of the present invention to provide a method in which the formation of a tapered via and the planarization of an intermediate insulating layer are performed in a single step.

Means for Solving the Problems In order to achieve the above object, the process according to the present invention involves forming a tapered via and planarizing an intermediate insulating layer in a single step. The process is as follows. First, a photoresist is deposited on the surface of the insulating layer and then patterned to form openings at locations where vias are to be formed.

The photoresist material is then reflowed by heating the photoresist layer to form tapered openings in the photoresist layer at positions corresponding to the via formation openings. Thereafter, the photoresist layer and the intermediate insulator layer are etched using an anisotropic etching method with a selectivity ratio of 1:1 between the photoresist layer and the intermediate insulator layer. In the process according to the present invention, the photoresist is in a liquid state at the time it is applied, so that a flat surface is formed after the photoresist is applied. Since the insulator layer and the photoresist layer are each etched with equal etch ratios, the intermediate insulator layer also has a planarized surface after the photoresist layer is completely etched away. Furthermore, by using an anisotropic etch method for the etching process, the tapered pattern of the photoresist layer is maintained when the via is etched into the insulator layer, thus forming a tapered via in the insulator layer. <Example> The present invention will be described in detail below with reference to two drawings.

1A to 1E are schematic sectional views showing manufacturing steps as an embodiment of the method according to the present invention. First of all
Figure A shows a cross-sectional structure of an integrated circuit formed by forming a conductor layer 2.3 on the surface of a substrate l, on which a silicon dioxide layer 4 is deposited to a thickness of 1.3 by plasma oxidation vapor deposition. It is formed to have a thickness of approximately 12,000 angstroms. This plasma oxidation vapor deposition method is used to obtain a formal oxide layer that conforms to the topography of the underlying layer, as shown in Figure 2. Next, a photoresist (OFPR-800) is applied to the surface of the silicon dioxide layer 4.
A photoresist layer 5 is formed by depositing
The thickness of the photoresist layer 5 from the surface to the lowest point on the silicon dioxide layer 4 is approximately 12,000 angstroms. This photoresist layer 5 is then patterned.

A via opening 6 is formed. The structure thus obtained is 1B
As shown in the figure, this photoresist layer 5 is then deposited at approximately 165 cm.
The photoresist layer 5 is reflowed by baking at a temperature of about 2 minutes. The structure thus obtained is shown in FIG. 1C. With respect to the structure shown in FIG. Perform anisotropic etching treatment using plasma of carbon fluoride and oxygen, etc. For steps 9 or more, refer to rPIanarization of Pho.
Sphorous Doped Silicon Dio
xideJ (Planarization of silicon dioxide doped with phosphorus, 128.J.

ElectrocheIl, Sac, 423 (1
981)) contains a related description.

FIG. 10 shows a cross section of the integrated circuit after the photoresist layer 5 has been etched to a depth of 8,000 angstroms. What is important in this case is that the tapered via shape formed by reflowing the photoresist layer 5 is directly transferred to the silicon dioxide layer 4 by the anisotropic etching process. This etching process is continued until the photoresist layer 5 is completely etched away, resulting in the structure shown in FIG. 1E.

Thus, the surface of the silicon dioxide layer 4 can be flattened and the tapered via 6 can be formed using only one mask step, one photoresist adhesive flow step, and one etching step. It becomes possible.

<Effects of the Invention> As described above, the process according to the present invention makes it possible to form tapered vias and planarize the intermediate insulating layer in a single process. First, a photoresist (5) is deposited on the surface of the insulator layer (4) and then patterned to form openings (6) at locations where vias are to be formed.
After forming a tapered opening in the photoresist layer (5) at a position corresponding to the via formation opening by promoting the flow of the photoresist material by heating the photoresist layer (5), the photoresist layer (5) is heated. ) and the insulating layer (4) using anisotropic etching with a selection ratio of 1:1. It is something. In this process.

Since the photoresist is in a liquid state at the time it is applied, it forms a flat surface after it has been applied, and the insulator layer (4) and the photoresist layer (5) are in phase with each other. Since the etching process is performed with equal etch ratios, the insulator layer (4) will also have a planarized surface after the photoresist layer (5) has been completely etched away. Furthermore, by carrying out the etching process using an anisotropic etch method, the tapered pattern of the photoresist layer (5) is retained when the vias are etched into the insulator layer (4), and thus the insulator layer A tapered via is formed in (4).

Thus, one embodiment of the present invention requires only one mask process and one photoresist glue flow process.

A single etch step is used to form a planarized insulator layer and a tapered via in the insulator layer. In other words, it is well known that conventional methods require a much more complex process and the use of various individual steps to form vias and planarize the insulator layer than the process of the present invention. As described above, reducing the number of process steps leads to improving the manufacturing yield of integrated circuits and reducing the total cost of manufacturing integrated circuits.2 The present invention has such effects. be.

The following sections are further disclosed in connection with the above description.

(1) When forming a tapered via in an insulator layer in an integrated circuit and planarizing the intermediate insulator layer.

Prepare an integrated circuit with an insulator layer.

A resist layer is formed on the surface of this insulator layer.

Patterning the resist layer at selected locations corresponding to vias to be formed in the insulator layer.

Heating the integrated circuit causes the resist layer to flow.

The resist layer and the insulator layer are etched using an anisotropic etching method so that the etch ratio between the two layers is 1:1, and this etching process is continued until the resist layer is completely removed. A method for forming vias and planarizing an intermediate insulating layer, characterized in that:

(2) A method for forming vias and planarizing an intermediate insulator layer as set forth in claim 1, wherein the integrated circuit is formed in a silicon substrate.

(3) The method for forming a via and planarizing an intermediate insulating layer according to item 1, wherein the insulating layer is a silicon dioxide layer.

(4) The method for forming a via and planarizing an intermediate insulating layer according to item 3, wherein the silicon dioxide layer is formed by a plasma oxidation method.

(5) In forming a silicon dioxide layer having a tapered via and a planarized surface.

A silicon dioxide layer is formed on the surface of the insulator layer to conform to the irregularities of the underlying layer.

A photoresist layer is formed on the surface of this silicon dioxide layer.

The photoresist layer is patterned to form vias at selected locations.

heating the integrated circuit to reflow the photoresist layer;

etching the photoresist layer and the silicon dioxide layer using an anisotropic etching method such that the etch ratio between the two layers is 1:1 and until the photoresist layer is completely removed; A method for forming a silicon dioxide layer, characterized in that:

The embodiments of the present invention have been described above.

It goes without saying that the method according to the present invention may be implemented with appropriate additions or changes to such embodiments.

[Brief explanation of the drawing]

1A to 1E are schematic sectional views showing manufacturing steps as an embodiment of the method according to the present invention. 1. . . . Substrate. 2.3. ,,conductor layer. 4. Silicon dioxide layer. 5. Photoresist layer. 6. Via opening. Applicant Texas Instruments Incorporated Drawing W <No change in content) April 23, 1985 Commissioner of the Patent Office Michibu Uga Display patent application No. 1981-019137 Name of the invention In the middle layer Relationship with the case of a person amending the method of forming vias and flattening the intermediate insulating layer Patent applicant

Claims (1)

[Claims] In forming a tapered via in an insulating layer in an integrated circuit and planarizing the intermediate insulating layer, an integrated circuit having an insulating layer is prepared, and the surface of the insulating layer is forming a layer of resist thereon, patterning the resist layer at selected locations corresponding to vias to be formed in the insulator layer, heating the integrated circuit to reflow the resist layer, and performing an anisotropic etch process. The resist layer and the insulating layer are etched using the resist layer and the insulating layer so that the etch ratio between the two layers is 1:1, and the etching process is continued until the resist layer is completely removed. method for forming vias and planarizing intermediate insulator layers.