JPS6121563A - Data processor - Google Patents

Abstract

PURPOSE:To analyze efficiently a fault by writing an identifier of a sub processor having issued a command to recognize a sub processor neglecting release when a test/set command is successful to a lock word executing the said command. CONSTITUTION:When a data of a test/set (T&S) address issued from a command analysis decoder 190 in a main storage 200 is read, a comparator 170 compares it with an initial value of a lock word of a register 180, and when they are coincident, a command 202 is issued, and a sender sub processor identifier issued with a command 202 and set to a register 130 is written in an area of the main storage 200 set to the register 140. When the access to the main storage 200 is finished by the T&S command, the main storage unit transmits a data set to the register 180 to a system bus 1000 and the end of T&S command is reported to the oscillation subprocessor. The the oscillating sub processor reads the reading data on the bus (1110).

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data processing device in which a main memory unit and a plurality of subprocessors are connected to a common system path.

[Prior art]

Conventionally, in data processing devices composed of multiple subprocessors, when each subprocessor references or updates an area that is commonly accessed, such as the system area of main memory, accesses from each subprocessor conflict. ,
Normal reference and update operations may not be possible. For this reason, a specific word in the system area is set as a lock word, and the subprocessor checks the state of the lock word when referencing or updating the system area. By locking the lock word when not being accessed, access rights to the system area are taken, and the state of the system area is prevented from being disturbed by references and updates from other subprocessors. Furthermore, after the subprocessor that has locked the lock word has finished accessing the system area, it must be unlocked to allow other subprocessors to access the system area. AN
This is a technology that has been conventionally used as a D SET (hereinafter referred to as T&S) function.

However, in recent data processing devices in which multiple subprocessors are connected to a common system bus, frequently access the shared area (system area) of the main memory unit, and execute system operations, If a subprocessor that has succeeded in T&S and has access rights to the system area is unable to release access rights to the system area due to a failure or a programming error in the program running in the subprocessor, the system The operation will stop.

Here, this conventional T&S function will be explained. When one sub-processor executes a T&S command to the main memory unit for the word at the address specified in the command, the main memory unit reads the data at the address, and the value of this read data becomes the initial value. If it is in the locked state, the read data is reported to the subprocessor that issued the T&S command, and a fixed value is written as data indicating the locked state in the word that executed the T&S command.

The sub-processor to which the read data has been reported determines that the T&S command has been successful if the reported data is the initial value, and proceeds to the next operation. If the data read by the main memory unit in response to the T&S command is data indicating a locked state, the main memory unit reports the read data to the subprocessor that issued the T&S command. When the subprocessor to which the read data is reported recognizes that the read data indicates a lock state, it determines that the T&S command has failed and is forced to wait until the T&S command succeeds before proceeding to the next operation. There were times when I ended up in a situation where I ended up in trouble.

In this way, in the conventional technology, the data indicating the lock state was written as a fixed value, so as mentioned above, the subprocessor that had succeeded in the T&S command and had access rights could not be determined. As mentioned above, if a subprocessor that has gained access rights to the system area due to a successful T&S directive is unable to release access rights to the system area due to a failure, programming error, etc., it will take a great deal of time and effort to analyze the failure. A situation like this had occurred.

[Purpose of the invention]

Therefore, an object of the present invention is to prevent the subprocessor from locking and accessing the system area when the subprocessor fails to release the lock word and the system stalls.
An object of the present invention is to provide a data processing device that can efficiently perform failure analysis and program analysis.

[Structure of the invention]

In the data processing device of the present invention, each sub-processor has means for independently issuing a command for accessing the main memory to the main memory unit, and one of the commands is included in the command in the main memory. It has a test/setting command to test/set the state of a word at a specified address, and when the main memory unit receives the test/setting command, it executes the test/setting command.
Inspects the state of the word at the address specified in the setting command, and if the word is in the initial state, reports the contents of the word to the subprocessor that issued the test/setting command as the execution result of the test/setting command. At the same time, it has means for writing into the word an identifier of the subprocessor that issued the test/setting command.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention. The data processing apparatus of this embodiment is composed of a main memory unit 100 connected to a common system bus 1000 and N sub-processors 1, 2.degree.

2 is a block diagram of the storage unit 100 of FIG. 1, FIG. 3 is a block diagram of the subprocessor 1-N of FIG. 2, and FIG. 4 is a diagram showing the data format on the system bus 100G.
FIG. 5 and FIG. 3 are diagrams showing mapping of the main memory 200.

A system area 201 (FIG. 5) allocated to addresses 0000 to 0100 of the main memory 200 is used by each subprocessor 1 to N to transmit information between each subprocessor l to N or to control the system of this data processing device. This is the area accessed for.

If the subprocessors l-N update the reference contention at the same time, correct information cannot be transmitted. Therefore, address 0000 of the system area 201 is defined as the lock word 202, and each sub-processor l-N tests the lock word 202.・System area 20 by setting
You will have 1 access right.

As shown in FIG. 3, each sub-processor INN includes a microprogram execution control section 10 that includes a microprogram storage memory, a microprogram execution sequencer, an arithmetic unit, an accumulator, and a group of working registers.
, system bus command code and main memory address are set by the microprogram execution control unit 10, respectively, in registers 14, 13. Register 15 in which the originating subprocessor identifier is set. Register meta 11. Read data read from the main memory 200 (FIG. 2) is set. Register 12 to which write data is set from the microprogram execution control unit IO in the case of a main memory write command. When the main memory access request signal 18 is output to the system bus control unit 11O (FIG. 2) of the main memory unit 100 by the command F17 from the microprogram control unit 10, and the access permission signal 19 is sent back from the system bus control 5110. 4, the data is sent onto the system bus 1000 in the data format shown in FIG. It consists of a system bus control section 16 that takes in the read data being read out on the bus 1000 into the register 11.

As shown in FIG. 2, the main memory unit 100 has main memory 2.
00. Registers 120.130.140.150.The system bus command code sent out on the system bus 1000, the originating subprocessor identifier, the main memory address, and the write data are set, respectively. register 120
Analyze the system bus command code set to T
A command analysis decoder 180 that issues a command 201 when it is analyzed as a &S command. When a command 201 is issued from the command analysis decoder 190, the data at the main memory address set in the register 140 is read from the main memory 200. Registers to be set and set
160. A register iso in which the initial value of the lock word 202 is set, compares the data read from the main memory 200 and the initial value of the lock word 202 in the register 180, and if the two are equal, issues the command 202 and sets it in the register 130. A comparator 170 writes the originating subprocessor identifier to the area of the main memory 200 at the main memory address set in the register 140 through the register 150, and the system bus control unit 16 of each subprocessor 1-N (FIG. 3). When the main memory access request signal 18 is received from the main memory access request signal 18, the access permission signal 19 is sent back to the system bus control unit 16, and the system bus command code sent on the system bus 1000, the originating subprocessor identifier, the main memory address, and the write data are stored in the register.
Set to 120.130.140.150 respectively,
When the access to the main memory 200 by the T&S command is completed, the system bus control unit 110 sends the read data 160 set in the register 160 to the system bus 1000 and outputs the command completion report signal 20 to each subprocessor l to N. Consisting of

Next, the operation of this embodiment will be described in the case where a microprogram running on the service processor 1 accesses the system area 201 of the main memory 200 shown in FIG.

When the microprogram in the subprocessor 1 outputs a T&S command for the lock word 202, the microprogram execution control unit 10 in the subprocessor 1 stores the command code for the system bus 1000 in the register 14.
and sets the T&S address (oooo in this embodiment) of the main memory 200 in the register 13. and,
When the microprogram execution control section 10 outputs the "command 17" to the system bus control section 16, the system bus control section 16 outputs a main memory access request signal 18 to the main memory unit 00. Main memory unit 100
When the system bus control unit 110 within the subprocessor 1 recognizes the main memory access request signal 18 from the subprocessor 1, it returns an access permission signal 18 to the subprocessor 1. This results in
The system bus control unit 1B sends data to the system bus 1000 in the data format shown in FIG. Of the data sent out on the system bus 1000, the system bus command code is sent to the register 120 for the outgoing subprocessor.
The sensor identifier is taken into register 130, the main memory address is taken into register 140, and the write data is taken into register 150. The system bus command code set in register 120 is read by command analysis decoder 18.
When the command analysis decoder 190 issues a command 201, the command analysis decoder 190 issues a command 201. The data at the address (oooo address) of the main memory 200 set in the register 9 140 of this command 201 is read from the main memory 200r, and the data is set in the register 9 140.
60 and input to the comparator 70. The comparator 170 compares the read data of the register 160 and the initial value of the lock word of the register 180 (°“oo” in this embodiment), and if the two are equal, a command 202 is issued and the output signal set in the register 130 is The subprocessor identifier is written through the register 150 to the area of the main memory 200 at the address set in the register 140 (in this embodiment, address oooo). If the results of the comparison by the comparator +70 are not equal, the command 202 will not be issued, and no data will be written to the area of the main memory 200 at the main memory address set in the register 140, and the main memory according to the T&S command will not be written. The operation of unit h too ends. T
When the access to the main memory 200 by the &S command is completed, the main memory unit 100 transfers the read data set in the register 180 to the system bus controller 110.
At the same time, the T&S command completion is sent to the system bus 1000 through the command completion report signal 20 to the subprocessor 1, which is a subprocessor that sends the T&S command. When the system bus control unit 16 of the sub processor l receives the command completion report signal 20, the system bus control unit 16
By taking in the read data sent out on 0O into the register 11, the T&S command issued by the subprocessor 1 is completed in this series of operations.

In this embodiment, each sub-processor 1.2゜---,
Since a value other than 00"° is set as the identifier of N, the microprogram in the subprocessor l checks the read data of the register 11, and this data is set as the initial number 1 of the lock word (oo" in this embodiment). So,
It is determined that the T&S command is successful, and the system area 201 existing in the main memory 200 can be referenced and updated. While the sub-processor l successfully executes the T&S command and executes the reference/update of the system area 201, the other sub-processors 2 to N send the T&S command to the main memory unit in the same manner as described above in order to access the system area 201. 100, the main memory unit 2 100 reads the lock word 202 and checks it, but since this read data is not the initial value "00", the main memory unit 200 stores the outgoing subprocessor identifier of the subprocessor l. Subprocessors 2 to N return the contents of address 0000 of 200 to subprocessors 2 to N that issued the T&S command.
determines that the T&S command has failed because the data in the lock word 202 is not the initial value "00°", and access to the system area 201 is disabled until the initial value "00" is read out by the T&S command. Sub processor 1
When the update during reference to the system area 201 is completed, the initial value of the lock word “°0” is stored at address 0000 in the main memory 200 by the microprogram in the subprocessor l.
Issue a command to write 0"'.

The method of system bus control within the subprocessor l in response to the main memory access command is the same as the T&S command described above, so the explanation will be omitted, but in the case of a main memory write command, the write data is set in the register 12, Write data is set in the write data section in the data format on the system bus 1000 shown in the figure. If subpu.
If a failure occurs in the processor 1 or a mistake in the microprogram in the subprocessor 1, the lock word 20
If subprocessors 2 to 2 cannot be initialized, even if subprocessors 2 to N request access to system area 201 as described above, T&S commands will continue to fail, resulting in a system stall state.

〔Effect of the invention〕

The present invention provides a lock word that executes a T&S command.
In the case of a successful T&S command, the identifier of the subprocessor that issued the T&S command is written, so by reading the lock word, it is possible to easily recognize the subprocessor that has neglected to release the lock word, allowing for failure analysis, Program analysis can be performed more efficiently than before.

[Brief explanation of the drawing]

1 is a block diagram of a data processing device according to an embodiment of the present invention, FIG. 2 is a block diagram of the main memory unit 100 of FIG. 1, and FIG. 3 is a block diagram of each subprocessor INN of FIG. 1. , FIG. 4 is a diagram showing the data format on the system bus 1000, and FIG. 5 is a diagram showing the mapping of the main memory 200 in FIG. 2. 1-N: Subprocessor lO2 Microprogram execution control unit 11-15: Register 16: System bus control unit 100: Main memory unit 110 System bus control unit 120 to 1θ0.180: Register, 170: Comparator 1
80: Command analysis decoder 200: Main memory, 1000 system bus 18: Main memory access request signal 18: Access permission signal 20: Command completion report signal 201, 202: Command II Figure 5th zone? Figure 32

Claims (1)

[Claims] In a data processing device in which a main memory unit and a plurality of subprocessors are connected to a common system bus, each of the subprocessors independently issues instructions to the main memory unit to access the main memory. a test and setting means for testing and setting the state of a word at an address specified in the command in main memory as one of the commands;
When the main memory unit receives the test/setting command, the main memory unit checks the state of the word at the address specified in the test/setting command, and if the word is in the initial state, the test/setting is performed. As a result of execution of the command, the content of the word is reported to the sub-processor that issued the test/setting command, and means is provided for writing an identifier of the sub-processor that issued the test/setting command to the word. Characteristic data processing device.