JPS61214656A - Fading circuit - Google Patents

Abstract

PURPOSE:To execute fade-out or fade-in by a simple bit shift operation by inputting a signal of (n) bits, holding its polarity bit as it is, and also bit-shifting the remaining bit group for every prescribed bit and at every prescribed time. CONSTITUTION:By only adding a bit shift by utilizing a shift register, the abso lute value of a digital signal Din decreases gradually by 1/2 each or increases gradually by two times each, and corresponds to fade-out and fade-in, respective ly. By adding a forward direction bit shift of 1 bit each to the digital signal Din whose amplitude is +1023, the amplitude is decreased gradually by about 1/2 such as +511 and +255, and fade-out in executed. On the other hand, for instance, when fade-in is executed by adding a reverse direction bit shift of 1 bit each to the digital signal whose amplitude is +1, and increasing gradually the amplitude by two times such as +1, +2, +4..., fade-out or fade-in is real ized without using a multiplier. In this way, both fade-out and fade-in can be realized easily.

Description

[Detailed Description of the Invention] [Summary] This is a digital fade circuit that inputs an n-focus signal, maintains its polarity bit as it is, and converts a group of bits indicating the remaining absolute value over a certain period of time. By bit-shifting by a fixed bit for each
Add a fade-out or fade-in operation to the signal. This makes it possible to fade out or fade in with a simple bit shift operation.

[Industrial application field]

The present invention relates to a fade circuit.

A fade circuit performs a fade-out or a fade-in on an input signal.
This is a circuit for adding each operation of (n), and is a common circuit in the audio field. In this audio field, it has been completed as an analog fade circuit.

On the other hand, the need for fade circuits has arisen in fields other than audio, such as the field of telephone switching.

This is required for various tone services, and by adding a fade-in at the rise of a certain tone and a fade-out at the fall of the tone, it is possible to provide a sound that is pleasant to listen to. Alternatively, when switching from tone A to tone B, if the switching between A and B is performed instantaneously, the sound will be extremely harsh and unpleasant.

In such cases, fade out to tone A and fade out to tone B.
By adding various fade-in operations to the above, high-quality tone service can be achieved. Note that the various tones mentioned here include dial tone, ringback tone, busy tone, and the like.

Incidentally, the telephone exchange system according to the above example has been increasingly digitized in recent years. Therefore, a digital fade circuit is also required as a fade circuit.

[Conventional technology]

When attempting to implement a fade circuit digitally, a multiplier is most commonly used. That is, the input digital signal to which the fade-in or fade-out is to be applied is used as the multiplicand, and the coefficient α is used as the multiplier, and the calculation α×D is executed. If α gradually increases or decreases over time, the desired fade-in or fade-out can be achieved.

[Problem that the invention seeks to solve]

In conventional fade circuits such as those described above, it is essential to use multipliers and to generate a gradually changing coefficient α. Therefore, a problem arises in that the circuit configuration becomes complicated.

[Means for solving problems]

FIG. 1 is a block diagram showing the principle structure of a fade circuit according to the present invention. In this figure, Din is a digital signal to which a fade-out or fade-in is added, and Dout is a digital signal to which a fade-out or fade-in is added. The digital signal Din is input to a shift register (SR) 11 and a polarity bit register (PR) 12.

Note that this digital signal Din is input in units of frames. One frame is usually 8 bits. Here, the polarity pit register 12 stores the most significant bit (MSB), ie, the polarity bit portion, of the digital signal Din in each frame.

The shift register 11 stores a bit group of the absolute value part excluding the polarity bit part for each frame.

The timing instruction instructs the timing to add a bit shift in the forward or reverse direction to the digital signal Din stored in the shift register 11 by a fixed number of bits each time a predetermined number of frames of digital signals are input. The shift register 11 is a circuit (TC) 13 based on instructions from the timing instruction circuit 13.
The content of is set as the absolute value bit group M, and the output register (
R) Hold at 14. and polarity pit register 12
A fade-out or fade-in digital signal Dout is obtained together with the polarity bit P from .

Whether fade-out or fade-in is added is determined by the fade control signal FC.

If a fade-out is to be added, the bits in the shift register 11 are shifted in the forward direction, and if a fade-in is to be added, the bits are shifted in the opposite direction.

Therefore 1. The signal FC is set to rise during fade-out and fall during fade-in (or vice versa).

FIG. 2 is a waveform diagram illustrating the operation of the blocks in FIG. 1. Columns (4) and (5) of this practice are the first
The digital signals Dout and Din shown in the figure are expressed in analog (sine waves) so that the fade-out and fade-in controls can be seen at a glance. In other words, analog converted signals ADout and AD
Indicates in. As shown in column (1) of the same figure, the signal ADin
When starting to add a fade-out to the signal ADin, the fade control signal FC rises; on the other hand, when starting to add a fade-in to the signal ADin, the signal FC falls. The timing instruction circuit 13 monitors the rise or fall of these signals FC, and sends out timing signals (solid line pulses) shown in column (2) of the figure. Note that the timing signal shown in the figure (21111jl) is expressed slightly differently from the actual one in order to make it easier to understand the operation that the timing instruction circuit 13 should perform. For example, compared to the constant frame generation timing (pulses indicated by dotted lines in the figure), during a fade-out, the timing signal is generated little by little later, and conversely, during a fade-in, the timing signal is generated little by little earlier.Such timing The signal shift is diagrammatically expressed in column (3) of FIG. 2 as a change in the number of bits of the absolute value bit group set in the output register 14 of FIG. →m -1-m -2-m -3...
The number of bits changes from 0 to 1 as it fades in.
It changes as 2-3... In other words, bit shifting is performed by a certain number of bits (in this case, one bit at a time).

[For production]

By simply applying a bit shift using a shift register (11 in FIG. 1), the absolute value (amplitude) of the digital signal Din gradually decreases by 2 or increases by 2. This corresponds to fade-out and fade-in, respectively. FIG. 3 is a bit pattern diagram for explaining the present invention in detail. In this figure, P is a polarity bit part of the digital signal Din, M is a bit group of its absolute value part,
As already explained. Suppose the absolute value is (111...
1), that is, a positive bit shift of 1 bit at a time is applied to the digital signal Din whose amplitude is +1023 to increase the amplitude to +511. Gradually decrease by about 2 like +255,
Perform a fade out. On the other hand, if the absolute value is (00...
・1), that is, 1 for a digital signal whose amplitude is +1
Add a bit-by-bit backward bit shift to increase the amplitude by +1
．． +2. A fade-in is performed by gradually increasing the number by 2 times, such as +4... Thus, a fade-out or fade-in is achieved without using a multiplier. Although the bit pattern diagram in FIG. 3 shows that the bits are shifted every frame, in reality, the digital signal Din for multiple frames, for example, 100 frames, is input to the shift register 11. Bit shift is performed each time the process is completed.

The number of frames at which the bit shift is performed is determined by the fade time for each fade-out and fade-in.

〔Example〕

FIG. 4 is a circuit diagram showing an embodiment of the fade circuit according to the present invention, and FIG. 5 is a waveform diagram of main signals used to explain the operation of the circuit shown in FIG. First, referring to FIG. 4, Din, Dout, and FC are the same as those already described in FIG. FR is a frame signal indicating frame division, CLK is a basic clock signal, CLK"
is a clock signal that determines the step timing. The shift register 11 in FIG. 1 is also shown as the shift register 11 in FIG. 4, and the output register 14
Although similarly depicted, the polarity bit register 12 of FIG. 1 is implemented as a 1-bit register 12-1 and a 1-bit register 12-2. The timing instruction circuit 13 in FIG. 1 also includes an up/down counter 13-1.
.

n-bit shift register 13-2, selector 13-3
, a bit counter 13-4, a decoder 13-5, and an inverter INV. Additionally, an AND gate and an output stage shift register REG are also provided.

The operation of the circuit shown in FIG. 4 can be easily understood from the waveforms of signals appearing in the main parts of the circuit, and these are shown in FIG. The waveforms shown in the (11-00) columns of FIG. 5 correspond to the waveforms of the signals appearing in the sections (11-00) of FIG. 4, respectively. The column (3) in FIG. 5 corresponds to the frame signal, and based on this frame signal, the outputs ■, ■, ■ of the shift register 11 are bit-shifted as shown in columns (4) to (6) in FIG. A digital signal Din is output. Also, (7
) column drives the 1-bit register 12-2 and captures the polarity bit portion (MSB) of the signal Din. Thereafter, this polarity bit is sent to the output stage shift register REG and held until the arrival of the next frame.

-・Output of shift register 13-2 ■-A, ■-B
, ■-〇, and ■-N appear mutually bit-shifted signals A, B, C, and N as shown in column (9), and any one of these is selected by the selector 13-3. selected. The selector 13-3 selects these sequentially according to the fade-out or fade-in, and realizes the operation shown in FIG. 3. In other words, A, B, C, N in Figure S α [column]
The output register 14 is controlled so as to obtain a signal such as , and the output of the shift register 11 is taken in. In the end, along with the polarity bit indicated by P in the column α in Figure 5, the same αI41111
The signals Din having absolute values indicated by A, B, C, and N are sequentially taken out from the register RUG as Dout, thereby realizing the desired fade-out or fade-in.

[Effects of the Invention] As explained above, according to the present invention, each time the absolute value of a digital signal is shifted by 1 bit, it gradually decreases by % or by 2
By focusing on the well-known fact of gradual increase by a factor of two, it is possible to easily achieve fade-out and fade-in without using large-scale and complicated hardware such as a multiplier. Note that the input digital signal Din is generally P
It is CM coded, and non-linear compression is often added. In this case, since the weight of each bit is different, it is necessary to perform nonlinear linear transformation (ROM
It is desirable to apply the present invention by performing the following steps.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the principle configuration of the fade circuit according to the present invention, Fig. 2 is a waveform diagram clarifying the operation of the blocks in Fig. 1, and Fig. 3 is a bit diagram for explaining the detailed explanation of the present invention. FIG. 4 is a circuit diagram showing an embodiment of the fade circuit according to the present invention, and FIG. 5 is a waveform diagram of main signals used to explain the operation of the circuit shown in FIG. 4. 11... Shift register, 12... Polarity bit register, 13... Timing instruction circuit, 14... Output register, Din, Dout... Digital signal, FC...
- Fade control signal, M... Absolute value bit group, P... Polarity bit. Figure 1 12: Polarity bit register 13; Timing instruction circuit 14: Output register P: Polarity bit M: Absolute value bit group Din, Dout: Digital signal Figure 2 FC: Fade control signal The operation of the block in Figure 1 is clarified. Waveform diagram (2),
+1113 (3) mmm-1m, =-001234---
14 Fig. 3 A bit pattern diagram for detailed explanation of the present invention Fig. 4 A circuit diagram showing an embodiment of the fade circuit according to the present invention

Claims (1)

[Claims] 1. A polarity bit register (12) for storing a polarity bit portion of a digital signal to be faded out or faded in for each frame, and an absolute value portion of the digital signal other than the polarity bit portion; A shift register (11
), and each time the digital signal for a predetermined plurality of frames is inputted, a fixed bit is added to the bit group of the absolute value part stored in the shift register (11) according to the fade-out or fade-in. a timing instruction circuit (13) that instructs the timing of adding bit shifts in the forward or reverse direction; and a timing instruction circuit (13) that transfers and temporarily holds the contents stored in the shift register (11) according to instructions from the timing instruction circuit (13). and an output register (14) for simultaneously sending out the polarity bit part and the absolute value part from the polarity bit register (12) and the output register (14), respectively, according to instructions from the timing instruction circuit (13). A fade circuit characterized in that it obtains the digital signal to which the fade-out or fade-in is applied.