JPS59114920A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To decrease the number of elements of an arithmetic device which calculates the interpolation digital data and to reduce the occupied area for IC formation, by having a serial transfer of the digital data. CONSTITUTION:The digital data fed from a sound synthesizer 21 is applied serially to a full adder 24, and at the same time the digital data stored in a shift register 28 is also applied to the adder 24. The arithmetic result of the adder 24 is stored in a shift register 23, and the half value of the memory contents of the register 23 is extracted and supplied serially to the adder 24. The arithmetic result of the adder 24 is also stored in the register 28, and the memory contents of the register 28 are supplied to a register 26 and then converted into analog signals by a D/A converter 27. Thus the number of elements can be decreased for a full adder, i.e., an arithmetic device and the occupied area can be reduced when a D/A converter is formed into an IC.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a D/A (digital/analog) converter, and particularly proposes a D/A converter that can perform digital interpolation to obtain a smooth analog output. It is.

The inventor of the present application proposed a D/A converter that performs digital interpolation at a frequency higher than the sampling frequency in Japanese Patent Application No. 55-109615.

The gist of this D/A converter is [a first register that stores input digital data at a first time, a second register that stores the stored contents of the first register at a second time, and a second register that stores input digital data at a first time; 1. An interpolation circuit that obtains and outputs an intermediate value based on each storage content of the second register, and a switch means that selectively inputs the storage content of the second register or the output of the interpolation circuit to a D/A converter. 1. The D/A converter is configured to obtain an analog output that changes at a higher frequency than the clock signal that defines the second time, but since the device transfers digital data in parallel, , the full adder for obtaining the intermediate value is l
In the case of /2 interpolation, l''i (number of data pits + 1) elements are required, which has the disadvantage of requiring a very large number of elements.

The present invention has been made to solve the above-mentioned difficulties, and by adopting a configuration in which data transfer is performed serially, the full adder can be reduced to 1 bit, and the wiring layer for data transfer can be reduced to 1. Therefore, it is an object of the present invention to provide a D/A converter that occupies a smaller area when integrated into an IC.

The present invention will be described in detail below with reference to drawings showing an embodiment using 1/2 interpolation when digital data has a 10-bit configuration and a sampling frequency of 8 kHz.

FIG. 1 is a block diagram of a D/A converter according to the present invention, and FIG. 2 is a time chart of control timing signals.

Referring to FIG. 1, 21 is a speech synthesizer, and 125/
Digital data of 10 pits is serially output with one period of 8 kHz, and this serial data can be given to the full adder 24 via a switch transistor (hereinafter referred to as a switch). The shift register 28 stores 10 pits of digital data, is shifted by the clock φ5, and the stored data is serially output and input to the full adder 24 via the switch 13 or via the switch 14 and the inverter 15. ◎ As will be described later, it plays an auxiliary role in the operation of the full adder 24.

The shift register 23 stores the calculation results of the full adder 24, and the calculation results of the full adder 24 are serially output and sent to the shift register 23 via the switch 7.
will be transferred to and stored here. Shift register 23#1
Using the output of the second bit from the LSB side, 1/2 the value of the stored contents can be retrieved, and this 1/2 value data is serially input to the full adder 24 via the switch 12. It is like that.

The operation result of the full adder 24 is also input to the shift register 28 via the switch 6 and is stored therein. The digital data stored here is outputted in parallel at a predetermined timing and transferred to the register 26, and then given to the D/A converter 27 as a parallel data, and a desired analog signal is obtained from this output. . In addition, switch 2 and nine switches are provided for circulating control of stored data in shift registers 23 and 28, respectively.

Next, the operation of this D/A converter will be explained.

First, as shown in Part 2 (a), the switch 10 control signal -
1 becomes high level and turns it on.

Data output from the speech synthesizer 21 is sent to the shift register 2.
3.28 respective shift clocks φ3. φ.

1 serially in synchronization with [same as shown in Figure 2 H]
The signals are performed pit by pit and are sequentially input to the full adder. Let this 10 pit data be I)I.

On the other hand, the 10-pit take stored in the shift register 28 is read. Then, this data D. is also serially output one bit at a time using the shift clock φ, and -
1 is given and the switch 14 is turned on and impark 1 is turned on.
5 to the full adder 24, the full adder 24 receives all bits from LSB to MSB. so that they correspond to -■). Let's play the first part
0 When subtracting the LSB, the tarokku φ1. [Figure 2 ()] is given in advance and set, and this "do" is added.

Furthermore, regarding the carry coefficient during addition, shift clock
Tarokku signal synchronized with 3 and -5 -8-4 [Figure 2 (e)
] and its inverted borrow sign ¥, [shown in FIG.

While such calculations are being performed, the control signal -7 applied to the switch 7 is set to high level as shown in FIG. 2(G), and the calculation results are transferred to the shift register 23 and stored therein. When the calculation for 10 pits is completed, 1 is stored in the shift register 23.
This means that the data of /'iD and -Do have been stored.

In addition, as shown in FIG. 2 (a), the switch 90 control signal -
8 has been at high level during this time, and the shift clock -
Shift register 28 indicates that 5 has been input 10 times.
The contents return to their original state 〇Shift clock - 3. -6
When 10 shots have been applied, the IJa signal -1 becomes low level, turning off the switch 1 and at the same time turning off the switch 1.
2 control signal-8, [Fig. 2 & S] is set to high level,
Turn on the switch 12. OAs I mentioned, the output of the 2nd bit from the 23rd LSB side of the shift register is sent to switch 1.
2, and the serial data output from the shift chronograph 3 is connected to the full adder 24 via the switch 12.
given to. The content of this data is (Di −DO)/
2.

On the other hand, at this time, the shift register 28 has a shift clock -
3 is given, and the inverted signal 71 of the control signal -1 is input to the switch 13, so the shift register 28 again outputs the original data D0 and supplies it to the full adder 24. This time, the device 24 will perform the calculation. Prior to the start of this operation, that is, immediately before addition of the LSB, a reset signal 11+o [FIG. 2(,2)3] is applied to the register 25 to reset its contents.

When the switch 1 turns off, the control signal φ7 of the switch 7 changes to low level and turns it off, and conversely, the control signal φ7 of the switch 6 [Fig. 82 (v)] changes to high level. Since this is turned on, the calculation results are sequentially inputted bit by bit to the shift register 28 via this switch 6.

Therefore, when the operation for 10 bits is completed, the shift register 28
This means that it has been memorized. During this time, as shown in FIG. 2(b), the control signal φ of the switch 2 is at a high level, so the data D, -Do in the shift register 23 is
gradually returns to its original state.

The 10-bit data stored in the shift register 28 is in the form of parallel data, and its control signal -〇 [Fig. 2 (ψ
] is read into the register 26 in synchronization with the rising edge of , and from there is outputted to the D/A converter 27 as parallel data.
The D/A converter 27 outputs an analog signal of (DO+DI)/2.

Note that during the period up to that point, the stored content D0 of the shift register 28 is being output.

Then, the control signal -8 of the switch 9 is set to high level, the switch 9 is turned on, and the 1θ of the shift clock -5 is turned on.
Maintain this state for the duration of the test.

As a result, the data in the shift register 28 returns to its original state and becomes (DO+DI)/2.

Next, control signals -6, φ, and 1 are set to high level, and control signal φ is set to high level.

With EtUh at low level, the data in the shift register 23 (based on DID[+) < (DI-DO)/2 and the data in the shift register 28 (Do + DI) /
Addition with 2 is performed. Prior to this addition, register 2
A reset pulse of -1° is applied to 5. Since the switch 6 is on, the addition result, the shift Dl, is sequentially input to the shift register 28 and stored. This data D1 is transferred to the register 26 at the next rising edge of control signal -8.
The signal is read in and input to the D/A converter 27, where it is converted into an analog signal and output.

The device of the present invention performs the above-mentioned operation at 12571s (8kHz).
) will be repeated as one cycle. Figures 3(a) and 3(b) show the output of the speech synthesizer 21 and the register 26.
This figure shows the contents of the output (or the input of the D/A converter 27) in analog form. , D,, D,, D.

...and changes in synchronization with the rise of the control signal -1, the output of the D/Af converter 27 will be an analog signal including a level interpolating between double period conversion levels. . This analog signal is output to the illustrated low-pass filter and further to the amplifier.

As described above, the D/A converter according to the present invention includes a plurality of shift registers, and a plurality of digital data selected from the digital data stored in each of these shift registers and the input digital data input in chronological order. arithmetic units for serially inputting data, and a predetermined shift register stores in time series interpolated digitized data of each input digital data obtained from the input digital data and the calculation results of the arithmetic units. , is configured to convert the data stored in the shift register into an analog signal, so the arithmetic unit, that is, the full adder in the above embodiment, can be made into a 1-bit one, and the wiring layer for data transfer can be made into a single tree. The area occupied when integrated into an IC can be reduced.

When the present invention is applied to speech synthesis as in the above-mentioned embodiment, the analog output of the D/A converter 27 contains almost no 8 kHz component of the sampling frequency, so it can be integrated into an IC as a low-pass filter in the subsequent stage. easy, 4k
It is possible to use a filter that cuts high frequencies at Hz and has an attenuation characteristic of 30bB10ct. That is 8kHz
In the case where a z component is included, in order to obtain the same level of audio quality as in the case of using the above-mentioned low-pass filter, it is necessary to cut the high frequency range at 4 kHz and have an attenuation characteristic of 60 dB 10 ct. Although it is extremely difficult to integrate a filter like the one described above into an IC, in the case of the present invention, it is possible to use an IC by using the filter as described above, and a system with high audio quality can be easily realized.

In the above-described embodiment, it is of course possible to interpolate intermediate values to be interpolated using old values.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram schematically showing its configuration, FIG. 2 is a time chart for explaining the operation, and FIGS. 3 (a) and (b) are respectively FIG. 2 is an explanatory diagram illustrating output data of a speech synthesizer and input data to a D/A converter 27 in an analog manner. 21...Speech synthesizer ff23, 28...Shift register 24...Full adder 25.26...Register 27...D/A converter Patent applicant Sanyo Electric Co., Ltd. agent Patent attorney Kawa Wild climbing dog

Claims (1)

[Claims] 1. Equipped with a plurality of shift registers and an arithmetic unit that serially inputs a plurality of digital data selected from the digital data stored in each of these shift registers and the input digital data input in chronological order. , a predetermined shift register is configured to store interpolated digital data of each input digital data obtained from the input digital data and the calculation result of the arithmetic unit in time series, and to convert the data stored in the shift register into an analog signal. A D/A conversion device characterized by: