JP2527017B2 - Digital filter - Google Patents

Description

Detailed Description of the Invention

TECHNICAL FIELD The present invention relates to a digital filter (oversampling filter) used in digital audio equipment and the like. "Prior Art" Digital filters are used in digital audio equipment such as CD (compact disc) players, BS (satellite broadcast) receivers, and DAT (digital audio tape recorders). According to this digital filter, the input digital signal is resampled at a frequency N times (N is an integer) the sampling frequency and output. If the digital signal output from the digital filter and having a high sampling frequency is D / A (digital / analog) converted, an analog signal in which the audio signal band and the unnecessary harmonic band are sufficiently separated can be obtained.
Therefore, unnecessary harmonics of the analog signal output from the D / A converter can be easily removed by the low-pass filter, and a high-quality audio signal can be reproduced. FIGS. 13A and 13B are block diagrams showing the configuration of an audio signal reproducing circuit for a CD (compact disc) player using a conventional digital filter. In FIG. 13 (a), 1 is a signal processing circuit. As an IC (integrated circuit) equipped with this type of circuit, for example, YM3623B manufactured by Yamaha Corporation is known. The pit information read from the CD is digitized by the signal processing circuit 1. Then, this signal processing circuit 1
From, digital data SDI corresponding to pit information,
It is serially output every predetermined sampling period FW = 1 / fs. In addition, from the signal processing circuit 1, digital data SDI
The bit clock BCI that is synchronized with each bit data of
SDSY is output. Reference numeral 2 is a digital filter, and an IC such as YM3414 manufactured by Yamaha Corporation is known. In this digital filter 2, the digital data SDI supplied from the signal processing circuit 1 is read at the timing of the bit clock BCI. Here, the digital data SDI consists of 16 bits per word. When the word clock SDSY is at "1" level, one word of L (left) channel data is "0".
When the level is set, one word of R (right) channel data is supplied from the signal processing circuit 1 to the digital filter 2. Then, the digital filter 2 detects the change in the word clock SDSY, thereby detecting the switching point of the word length of the digital data SDI, and detecting the R channel and the L channel.
Digital data SDI for one word for each channel is fetched internally. In this way, the digital data SDI is taken in every sampling cycle FW. Then, in the digital filter 2, digital data corresponding to a sampling frequency 8fs that is eight times the input sampling frequency fs is calculated. The digital data obtained as a result of this calculation is serially output as digital data DRO (for the right channel) and DLO (for the left channel) in sequence at every 1/8 cycle of the input sampling cycle FW. Also, this digital data DRO
An output bit clock BCO synchronized with each bit data of DLO and DLO, an output word clock WCO synchronized with the transmission of one word of digital data DRO and DLO, and a sample hold signal SHL are output. The digital filter 2 has an oscillation circuit 2X having an oscillation frequency of about 400fs.
Is provided. Then, the oscillation output of the oscillation circuit 2X is phase-synchronized by the bit clock BCI to generate an internal clock, and the internal clock causes each unit in the digital filter 2 to operate. That is, in the digital filter 2, the processing is advanced in phase with the signal processing circuit 1. 3R and 3L are D / A converters, which convert the digital data DRO and DLO output from the digital filter 2 to D / A, respectively.
A Convert and output. Digital data DRO and DLO are
D / A converters 3R and 3L depending on the bit clock BCO
Is serially input to. Then, when the word clock WCO changes, it is latched by an internal latch circuit, D / A converted, and output as analog signals AR and AL, respectively. Then, these analog signals AR and AL are sample-held by the sample-hold circuits 4R and 4L, and then unnecessary harmonics are removed by the analog filters 5R and 5L, and the R-channel audio signal RA and the L-channel audio signal are removed. Output as LA. As shown in FIG. 13B, the high-speed clock φ _A generated from the signal processing circuit 1 is supplied to the digital filter 2
Even if it is supplied to the oscillation circuit input terminal XI of
It is possible to configure an audio signal reproducing circuit having the same function as that shown in FIG. [Problems to be Solved by the Invention] By the way, in the above-described conventional digital filter 2, the input sampling frequency fs and the input timing of the number of bit clocks input for each sampling period FW (this number is called a bit clock rate), etc. The circuit is designed according to the specifications. However, there are various sampling frequencies fs for digital signals, such as 32 kHz for BS receiver, 44.1 kHz for CD player, and 48 kHz for DAT.
Various specifications are also used for the bit clock rate from 32fs to 192fs. Therefore, when designing a digital audio system, it is necessary to prepare a digital filter that meets these input timing specifications, and there is a problem that the design is difficult. Further, if a suitable digital filter is not available, it is necessary to newly purchase or develop it, which causes a problem that the cost of the system becomes high. Especially when the sampling frequency of the input digital data to the digital filter changes, the optimum timing for passing the output digital data that is the processing result of the digital filter to the subsequent circuits (digital-analog converter, sample hold circuit, etc.) changes. Therefore, it is extremely difficult to design a digital filter corresponding to a plurality of types of sampling frequencies. For example, simply delay the word clock WCO, etc. described above by a specified number of clocks, and
When the SHL is generated, if the sampling frequency of the input digital data changes, the bit clock rate changes accordingly, so the pulse width and output timing of the sample hold signal SHL also change, and the sample hold There is a possibility that the timing and the like may be shifted and the system may malfunction. The present invention has been made in view of the above-mentioned circumstances, and regardless of the input timing specifications, it is possible to cause the subsequent circuit to process the digital data as the processing result at the optimum timing, and to adapt to various input timing specifications. The purpose is to provide a digital filter capable of "Means for Solving the Problem" The present invention performs a predetermined product-sum operation on time-series digital data (serial data SDI) that is sequentially input (Fig. 1, operation unit 12, coefficient ROM 13, temporary ROM). RAM14), a digital filter that generates digital data (digital data DRO, DLO) corresponding to a sampling frequency (N · fs) that is N times (N is an integer) the sampling frequency (fs) of the input digital data, Start signal (output word clock WCO) having a frequency N times the sampling frequency of digital data
Start signal generating means (Fig. 5, delay circuits 113 and 11)
4, selector 115, delay circuit 116), and bit input speed (bit clock rate detection signals SA, SB, SC) of each bit forming the input digital data
For detecting bit input speed (Fig. 5, counter
103, a differentiating circuit 104, a latch circuit 105, a decoder 106) and a digital signal (digital data DRO, DLO) obtained as a result of the product-sum operation, which is activated by the activation signal, and a subsequent circuit Means for outputting a synchronization signal (output bit clock BCO, output word clock WCO, sample hold signal SHR, SHL) for digital-to-analog conversion based on digital data, said start signal based on said bit input speed Output means for controlling the output timings of the digital data and the synchronizing signal with respect to (see FIG. 1, P / S converter 17, BCO generator 19, fifth
Figure, counter 112, delay circuit 117,120 to 123,125,127L, 127
R, 128L, 128R, inverter 117a, pulse generation circuit 118R, 11
8L, a detection circuit 119, selectors 124 and 126, and an OR gate 129). "Operation" According to the above configuration, the timing generation circuit generates the activation signal according to the sampling frequency of the input digital signal. Further, the bit input speed of the input digital data is detected by the bit input speed detecting means. Then, activated by the activation signal, the output circuit outputs the digital data indicating the calculation result and the synchronization signal. Here, the output timing of these digital data and sync signal is controlled to the optimum state according to the input bit input speed. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a digital filter according to an embodiment of the present invention.
It is a block diagram showing a configuration of 2a. Further, FIG. 2 is a block diagram showing a configuration of an audio signal reproducing circuit using this digital filter 2a, and FIG.
The system, FIG. 2 (b), shows the 1DAC system. In FIGS. 2 (a) and 2 (b), portions corresponding to those in FIG. 13 described above are designated by the same reference numerals. In FIG. 1, reference numeral 11 is an S / P (serial / parallel) converter. Signal processing circuit 1 for each sampling cycle FW
Each bit of the serial data SDI supplied from {Fig. 2 (a), (b)} is sequentially read into the S / P conversion unit 11 at the timing of the bit clock BCI. Then, every time the word clock SDSY is switched, a total of 16 bits of serial data SDI read so far is output as 1-word parallel data. Reference numeral 12 denotes an arithmetic unit, which includes a shift register, a multiplier and an adder. S / P converter 1
The parallel data output from 1 is input to the shift register and sequentially shifted. Then, the digital data of each stage of the shift register is multiplied by the coefficient read from the coefficient ROM 13. Then, the respective multiplication results are added and output as digital data corresponding to the sampling frequency of N times. Reference numeral 14 denotes a temporary RAM (temporary storage circuit), in which the intermediate result of the calculation in the calculation unit 12 is stored. Reference numeral 15 denotes an overflow limiter, which has a function of correcting the calculation result in the calculation unit 12 to a predetermined value when the calculation result becomes an extremely large value that is far from reality. 16 is an output temporary buffer. Digital data obtained as a result of the calculation in the calculation unit 12 is temporarily stored in the output temporary buffer 16 via the overflow limiter 15. Reference numeral 17 denotes a P / S converter, which converts parallel data supplied from the output temporary buffer 16 into serial data DRO and DLO and outputs the serial data DRO and DLO. An arithmetic control unit 18 controls arithmetic processing in the arithmetic unit 12 and controls data transfer between the respective units. A BCO generator 19 generates and outputs an output bit clock BCO. The output bit clock BCO is generated in synchronization with the transmission timing of each bit of the serial data DRO and DLO output from the P / S conversion unit 17. Therefore, the D / A converters 3, 3R, 3L {FIG. 2 (a), (b)} following the digital filter 2a can read the serial data DRO, DLO by the bit clock BCO. In addition,
This digital filter has a configuration capable of switching whether the calculation result is output as 16-bit digital data or 18-bit digital data. When the switching signal 16/18 is at "0" level, 16 bits are specified, and when it is at "1" level, 18 bits are specified.
The number of bit clock BCOs according to the specification is transmitted. Reference numeral 20 is a sync signal generator. In this sync signal generator 20, the input word clock SDSY and the input bit clock
The sampling frequency fs is detected from the BCI, and based on the result, a synchronization signal having a frequency eight times the sampling frequency fs is generated. Then, the arithmetic control unit 18 is activated by being activated by this synchronization signal. Also,
The sync signal generator 20 generates an output word clock WCO and sample hold signals SHL and SHR synchronized with one word of the serial data DRO and DLO. Where the second
In FIG. 7A, the D / A converters 3R and 3L detect the falling of the output word clock WCO and latch the input serial data DRO and DLO.
The same applies to the D / A converter 3 shown in FIG. 2 (b). The sample and hold circuits 4R and 4L are connected to the D / A converters 3R and 3R in the previous stage according to the sample and hold signals SHL and SHR, respectively.
It is designed to sample and hold the analog output of L. This digital filter fixes the switching signal ST at "1" level when used in the 2DAC system as shown in Fig. 2 (a), and switches when used in the 1DAC system as shown in Fig. 2 (b). Fix the signal ST to "0" level. By doing so, a sample hold signal suitable for the operation of each system can be obtained. Reference numeral 21 is a crystal oscillation circuit, and a crystal oscillator is externally attached to the crystal mounting terminals XI and XO. As the oscillation frequency of the crystal oscillation circuit 21, a frequency (384 fs or more) sufficiently higher than the sampling frequency fs of the input digital data is selected. In FIG. 1, a portion surrounded by a broken line, that is, a calculation unit 12, a coefficient ROM 13, a temporary RAM 14, an overflow limiter 15, an output temporary buffer 16, a P / S conversion unit 17, a calculation control unit 18, and a BCO generation unit 19 are , And operates according to the oscillation output φ _M of the crystal oscillation circuit 21. Next, an outline of the operation of this digital filter will be described using the time chart of FIG. FIG. 2 (a),
From the signal processing circuit 1 of (b), a bit clock with a cycle FB
BCI is input and sampling cycle FW (= 1 / f
For each s), the word clock SDSY and the 16-bit serial data SDI for the L channel and the R channel are respectively input. Here, the L channel data is input when the word clock SDSY is at "1" level, and the R channel data is input when the word clock SDSY is at "0" level.
These serial data SDSY are input to the S / P conversion unit 11, and the serial data input so far are converted into parallel data at the change point of the word clock SDSY. On the other hand, the synchronizing signal generator 20 detects the rising edge of the word clock SDSY and the number of bits of the bit clock BCI input in one sampling cycle FW, and based on the result, the results are shown in FIG. As shown, an output word clock WCO having a frequency eight times the input sampling frequency fs is generated. Further, sample hold signals SHL and SHR synchronized with the word clock WCO are generated. Then, when the fall of the output word clock WCO is detected by the operation control unit 18, the operation control unit 18 sends a microprogram address, and the operation unit 12 executes the microprogram. Then, when the microprogram of the predetermined number of steps is executed, the falling edge of the output word clock WCO is next calculated by the arithmetic control unit 18.
The calculation unit 12 is in a standby state until it is detected by. Here, the above-mentioned processing by the arithmetic control unit 18 and the arithmetic unit 12 is executed in synchronization with the internal clock φ _M. Then, the arithmetic processing is executed at each falling edge of the word clock WCO, and in one sampling period FW, eight sets of digital data for the L channel and eight sets for the R channel are obtained, and these data are overflow limiter 15 and output temporary. It is sent to the P / S conversion unit 17 via the buffer 16.
Then, these eight sets of digital data are transmitted together with the word clock WCO. Also, each bit of each data is output as serial data DLO, DRO in synchronization with the output bit clock BCO in the BCO generator 19. In FIG. 2 (a), in the D / A converters 3R and 3L,
Input digital data is D / A converted at the falling edge of the word clock WCO. In addition, the sample hold circuit 4
R and 4L are in the sampling state when the sample and hold signals SHR and SHL are at "1" level, and are in the hold state when at "0" level. According to this digital filter 2a, as shown in FIG. 3, the sample hold signals SHR and SHL are at "0" level when the word clock WCO falls and rise to "1" level after a lapse of a predetermined time 2T. . Therefore, the D / A conversion is completed and the analog signal AR
Sample hold circuit after AL and AL are stable enough
Sampling at 4R and 4L is done. FIG. 4 is a time chart showing the relationship between the internal clock φ _M and the output signal. When the falling edge of the output word clock WCO is detected, the BCO generator 19 generates an output bit clock BCO synchronized with the internal clock φ _M. In this digital filter 2a, 18-bit digital data is obtained as the operation result, and the serial data
It is output as DLO and DRO. Here, the output order of each bit of serial data is such that each bit data from MSB (most significant bit; “M” in FIG. 4) to LSB (least significant bit; “L” in FIG. 4) The extension bits ("-1" and "-2" in FIG. 4) obtained as a result of the operation are sequentially output. However, if the digital system subsequent to this digital filter 2a is a 16-bit system, 2 bits for extension are not necessary. Therefore,
The digital filter 2a can switch the number of bit clocks BCO so that the digital filter 2a can be applied to both the 18-bit system and the 16-bit system. That is, the number of output bit clocks BCO is specified by the level of the switching signal 16/18, and the BCO generator 19 outputs the specified number of clocks. Next, the timing control method in the digital filter 2a will be described in more detail. FIG. 5 is a circuit diagram showing a partial configuration of the synchronization signal generator 20, the BCO generator 19, and the operation controller 18. The circuit of FIG. 5 is a mixture of a circuit that operates in synchronization with the internal clock φ _M generated by the crystal oscillator circuit 21 and a circuit that operates in synchronization with the input bit clock BCI. Further, the circuit of FIG. 5 is a circuit realized as an IC, and a circuit system is adopted so that stable operation can be obtained when the circuit is integrated into an IC. Therefore, first, a supplementary explanation will be given on the circuit system adopted for the IC implementation. A master-slave type flip-flop is used as a flip-flop forming each part of the circuit of FIG.
It is driven by a two-phase clock generated from the clock φ _M or the bit clock BCI. SRF1 and SRF2
From the clock φ _M and the bit clock BCI,
It is a circuit for generating two-phase clocks φ ₁₅ and φ ₁₆ and two-phase clocks φx and φy. FIG. 6 shows the operation of the circuit SRF1. As shown in this figure, the clocks φ ₁₅ and φ ₁₆ are the signals φ _M.
Immediately fall due to changes in. But the clock φ ₁₅
Looking at the rising edges of φ ₁₆ and φ ₁₆ , the clock φ ₁₅ rises when the clock φ ₁₆ falls, and conversely,
The clock φ ₁₆ rises when the clock φ ₁₅ falls. Therefore, the clocks φ ₁₅ and φ ₁₆ have a phase relationship in which the periods of “1” level do not overlap each other, and a high-quality two-phase clock can be obtained. Similarly, in the circuit SRF2, the two-phase clocks φx and φy are obtained from the bit clock BCI. The two-phase clock thus obtained is supplied to the master-side latch M and the slave-side latch S of each flip-flop that constitutes the circuit of FIG. 5, as shown in FIG. Since such a clock supply system is adopted, when the master side latch M is in the read state, the slave side latch S is surely in the cut-off state, and conversely, when the slave side latch S is in the read state, it is sure. The master side latch M is turned off. Therefore, stable operation of the flip-flop can be obtained. Further, in the circuit of FIG. 5, for timing adjustment,
A delay circuit using a master-slave flip-flop is used. In FIG. 5, "D", "nD" (n is an integer),
It is written as "Dx" or "nDx" (n is an integer). Here, “D” or “nD” is operated by the two-phase clocks φ ₁₅ and φ ₁₆ . Further, “Dx” or “nDx” operates by the two-phase clocks φx and φy. The integer n added to the head of "D" or "Dx" represents the number of flip-flop stages. This is the end of the supplementary description of the circuit of FIG. Hereinafter, the configuration and operation of each part of the synchronization signal generator 20, the BCO generator 19, and the operation controller 18 shown in FIG. 5 will be described.

[Sync Signal Generator 20] FIG. 8 is a time chart showing the operation of the sync signal generator 20. In the sync signal generator 20, the input word clock SDSY is input to the rising edge detection circuit 1 via the delay circuit 101.
Supplied to 02. Then, when the word clock SDSY rises (time t ₀ ), when the third clock φy rises (time t ₁ ) from the rise time (time t ₁ ), the rise detection circuit 102 outputs the width FB (FB is the clock φx, φy. Rising edge detection pulse RES1 is output. This pulse RES1 is supplied to the counter 103 as a reset pulse. The counter 103 is an 8-bit up counter having a synchronous reset function, and counts by two-phase clocks φx and φy obtained from the bit clock BCI. The toggle inhibit input TI is fixed to the power supply VDD. Therefore, the counter 103 continues to count up as long as the bit clock BCI is input. When the pulse RES1 at time t ₁ is input as a reset pulse, it is read in the immediately clock .phi.x,
Next, the counter 103 is reset at the clock φy,
The count value is "0" (time t _2). Then, counting up from the count value "0" is again performed by the bit clock BCI. On the other hand, the pulse RES ₁ output at time t ₁ is supplied to the latch circuit 105 via the differentiating circuit 104. As a result, the pulse La is output from the differentiating circuit 104 during the period of FB / 2 from the rising time t ₁ of the pulse RES1, which is the latch circuit 1
It is supplied to 05 as a latch signal. And counter 10
The upper 4 bits Q _{4 to} Q _{7 of 3} are taken into the latch circuit 105. In this way, each time the rising edge of the word clock SDSY is detected, the counter 103 is reset and the final count value of the counter 103 is taken into the latch circuit 105. Here, assuming that the bit clock rate is Nfs, that is, the number of bit clocks BCI input in one cycle FW of the word clock SDSY is N, the final count value immediately before the counter 103 is reset is “N−1”.
Becomes Then, the latch data of the latch circuit 105 becomes M1 = (N / 16) -1 (1). The latch data M1 of the latch circuit 105 is supplied to the decoder 106 and the comparison circuit 107. The decoder 106 decodes the latch data M1 and outputs the bit clock rate detection signal.
SA, SB, SC are output. The digital filter 2a is capable of handling bit clock rates that are integer multiples of 16 from 32fs to 192fs, and performs timing control suitable for each bit clock rate. The switching of the timing control is performed by the bit clock rate detection signals SA, SB, SC. here,
When the bit clock rate is 128fs or more, the signal SA becomes "1". When the bit clock rate is 48fs to 112fs, the signal SB becomes "1" and the bit clock rate becomes 32fs.
In the case of, the signal SC becomes "1". The comparison circuit 107, the counter 108, and the OR gate 109 form a variable frequency divider. Then, the variable frequency divider divides the bit clock B according to the latch data M1 of the latch circuit 105.
Divide the CI. The operation of this variable frequency divider will be described below with reference to the time chart of FIG. Word clock SDSY
Rises (time t ₃ ), the detection pulse RES 1 is generated (time t ₄ ) that accompanies it, but this pulse RE
S1 is supplied to the counter 108 as a reset pulse RES2 via the OR gate 109. And this reset pulse R
ES2 is read into the counter 108 at the clock φx immediately after the generation. Then, at the next clock φy, the counter 10
8 is reset and the count value becomes "0" (time
t _5). Then, from the count value “0”, the bit clock BC
Up count by I is performed. In the counter 108, up-counting proceeds with the input of the bit clock BCI. Then, the count value of the counter 108 is compared with the latch data M1 of the latch circuit 105 by the comparison circuit 107. Then, counting up proceeds, the count value is detected pulse EQ output from the comparator circuit 107 to coincide with the data M1, which is input to the counter 108 as a reset pulse RES2 (time t _6). Then, when the clock φy is next input, the counter 108 is reset and the count is repeated again from the count value “0”. In this way, the counter 108 performs the count operation according to the latch data M1, and the count values “0” to “M
1 ”is repeated. Then, each time the count value becomes “M1”, the comparison circuit 107 outputs the detection signal EQ. Therefore, the period FW _EQ of the detection pulse EQ is the bit clock
The length is "M1 + 1" pieces of BCI. Similarly to the above, when the number of bit clocks input in the sampling period FW is N, the period FW _EQ of the detection pulse _EQ is FW _EQ = {(M1 + 1) / N} FW ... (2). Then, in this case, M1 is given by the above-mentioned expression (1), so that FWEQ = {(N / 16) / N} FW = FW / 16 (3). In this way, the cycle of the detection pulse EQ is 1/16 of the sampling cycle FW, and 16 pulse EQs are generated every sampling cycle FW. That is, the frequency of the detection pulse EQ is 16 fs, which is 16 times the sampling frequency fs. Reference numeral 112 is a 2-bit counter having a synchronous reset function, which performs an up-counting operation by the bit clock BCI. The counter 112 has a toggle inhibit function, and the toggle inhibit signal TI is "1".
The counting operation is performed only for the level. The detection pulse RES1 generated each time the word clock SDSY rises is supplied to the counter 112 as a reset pulse RES3 via the delay circuit 110. Then, this reset pulse RES3 is read at the rising edge of the clock φx,
The counter 112 is reset at the rising edge of the clock φy (time t ₇ ). On the other hand, in the counter 112, the delay circuit 1
The pulse EQD obtained via 11 is supplied as a toggle inhibit signal. Therefore, the counter 112 has a pulse EQD
Every time is input, the counting operation is performed. As a result, from the Q ₀ output of the counter 112, a pulse P8F obtained by dividing the pulse EQD by 2
Is obtained. And the pulse EQD is the sampling period FW
Since 16 pulses are generated for each, as shown in FIG.
Eight P8Fs are output for each cycle FW. In this way, the pulse P having the frequency 8fs which is eight times the sampling frequency fs
8F can be obtained. The pulse P8F generated in this way causes the output word clock WCO and sample hold signals SHL, SH
R is generated. This operation will be described below with reference to the time chart of FIG. <Generation of Word Clock WCO> The pulse P8F is supplied to the delay circuit 114 and the selector 115 via the delay circuit 113. Then, the output signal of the selector 115 is output as the output word clock WCO via the delay circuit 116. The bit clock rate detection signal SA is supplied to the selector 115 as a select signal, and the delay time from the output of the pulse P8F to the output of the word clock WCO can be switched.
According to these circuits 113 to 116, when the bit clock rate is 128fs or more, the pulse P8F delayed by 5FB is used.
If the bit clock rate is 112fs or less, pulse P8F
The delayed 4FB is obtained as the word clock WCO. FIG. 9 shows the case where the bit clock rate is 112 fs or less. <Generation of Sample Hold Signals SHL, SHR> When the bit clock rate changes, the cycle FB of the bit clock BCI changes accordingly. Therefore, in the method in which the pulse P8F is simply delayed by the predetermined number of clocks to generate the sample hold signals SHL and SHR, the switching timing and pulse width of the sample hold signals SHL and SHR change with the bit clock rate. For this reason, even if a favorable sample hold timing is obtained for a certain bit clock rate, the sample hold timing is deviated at another bit clock rate and the system malfunctions. In this digital filter 2a, the sample hold signal SH is delayed by delaying the pulse P8F with a delay circuit.
In order to obtain L and SHR, the number of stages of the delay circuit is switched in correspondence with the bit clock rate. By doing so, the sample hold signals SHL and SHR with good timing can be obtained even if the bit clock rate changes. The Q ₁ output of the counter 112 is delayed by 2FB by the delay circuit 117 and input to the pulse generation circuit 118R as the signal Q1D,
Further, the signal Q1D is inverted by the inverter 117a and input to the pulse generation circuit 118L as the signal Q1DN. on the other hand,
The Q ₀ output (pulse P8F) of the counter 112 is input to the fall detection circuit 119. Then, when the pulse P8F falls, a detection pulse of width FB is output from the detection circuit 119,
This is delayed by 1 FB in the delay circuit 120 and output as a pulse NQ0. This detection pulse NQ0 is the pulse generation circuit 118R.
And 118L and are sequentially propagated to the delay circuits 121 to 123. Here, pulse generator circuits 118R and 118L
Have the same circuit configuration. The pulse generation circuit 118R is enabled when the signal Q1D is "1", and the pulse generation circuit 118L is enabled when the signal Q1DN is "1". The output signals of the delay circuits 121 to 123 are input to the selector 124. The bit clock rate detection signals SA to SC are supplied to the selector 124 as select signals. Therefore, when the bit clock rate is 128 fs or more, the output signal of the delay circuit 123 has a bit clock rate of 48 fs to 1 fs.
In the case of 12fs, the output signal of the delay circuit 122 is selected, and in the case where the bit clock rate is 32fs or less, the output signal of the delay circuit 121 is selected. Then, the selected output signal is input to the pulse generation circuits 118R and 118L as the pulse NQ0D via the delay circuit 125. Next, the operation of the pulse generation circuit 118L will be described. When Q ₀ and Q ₁ of the counter 112 fall (time t ₁₀ ), the pulse NQ 0 is input 1FB later. But at this time, the signal Q1DN
Is the "0" level, the output i of the NAND gate 118A is the "1" level, the output j of the AND gate 118B is the "0" level, and the output k of the OR-AND gate 118C is the flip-flop 118C.
It has the same signal level (in this case, "0" level) as the output 1 of D. Therefore, the output 1 of the pulse generation circuit 118L does not change at this point. When the bit clock rate is 48fs to 112fs, pulse N
Pulse NQ0D rises 3FB behind Q0. As a result, A
Output k output j and OR-the AND gate 118C the ND gate 118B becomes "1" level (time t _11). Then, one FB later, the pulse NQ0D falls, and the output j of the AND gate 118B falls (time t ₁₂ ). On the other hand, by the previous clock φx of time t ₁₂ the output k of the OR-the AND gate (in this case "1" level) is read into the flip-flop 118D, at time t ₁₂ is output from the flip-flop 118D.
Therefore, the output k of the OR-AND gate 118C eventually settles to the "1" level. Then, thereafter, the output signal 1 of the pulse generation circuit 118L becomes the "1" level. When the output signal 1 rises, the selector 126, the delay circuits 127L and 128L
Operate sequentially and the sample hold signal SHL rises. Here, the delay circuit 128L has a bit clock rate of
In the case of 32fs and the delay time of 0.5FB can be obtained only when the input signal falls. The operation of the delay circuit 128R described later is also the same. Next, at time t ₁₃ , the Q ₀ output (pulse P8F) of the counter 112 rises. In this case, the word clock WCO
Changes only after 4FB, and no operation is performed in the circuit related to the generation of the sample hold signal. Next, at time t ₁₄ , the Q ₀ output of the counter 112 falls and the Q ₁ output rises. Then, 1FB later, the pulse NQ0 rises, and 2FB later, the signal Q1DN falls.
At the rise of the pulse NQ0 (time t _15), the signal Q1DN is "1"
Since it is at the level, the output i of the NAND gate 118A falls, and the output k of the OR-AND gate 118C falls accordingly. Then, after a lapse of 1FB (time t _16), pulse NQ
Since 0 falls, the signal i rises. On the other hand, time t
An output k (“0” level in this case) of the OR-AND gate is read into the flip-flop 118D by the clock φx immediately before ₁₆ and at the time t ₁₆ , the flip-flop 118D is read.
Output from D. Therefore, the output k of the OR-AND gate 118C
Eventually settles down to the “0” level. Then, thereafter, the output signal 1 of the pulse generation circuit 118L becomes the "0" level. And
When this output signal 1 falls, the selector 126 and the delay circuits 127L and 128L operate sequentially, and the sample hold signal
SHL falls. The pulse generation circuit 118R also operates similarly to the circuit 118L. However, the pulse generation circuit 118R operates while the signal Q1D is at the "1" level. Then, the output signal of the pulse generation circuit 118R is output as the sample hold signal SHR via the delay circuits 127R and 128R. When the digital filter 2a is used in a 1DAC system, the switching signal ST is fixed at "0" level and used. In this case, the selector 126 selects the output signal of the pulse generation circuit 118L. Then, the sample hold signal SHR
The output signal from the pulse generation circuit 118R is output as, and the signal from the pulse generation circuit 118L is output as the sample hold signal SHL. Then, as shown in FIG. 3, signals SHR and SHL that rise alternately are obtained. When the digital filter 2a is used in a 2DAC system, the switching signal ST is fixed at "1" level and used. In this case, the selector 126 selects the output signal of the OR gate 129. Here, the output signals of the pulse generation circuits 118R and 118L are input to the OR gate 129. Therefore, as the sample hold signal SHL, the logical sum of the signal from the pulse generation circuit 118L and the signal from the pulse generation circuit 118R is output. Next, the phase relationship between the word clock WCO and the sample hold signals SHR and SHL in the digital filter 2a will be described. In this digital filter 2a, as can be seen from the above description, the output pulse P8F of the counter 112 is
, The word clock WCO and sample hold signals SHR and SHL having the following phase relationship are obtained. Delay from the change point of pulse P8F to the change point of word clock WCO a.128fs ~ ... 5FB b.48fs ~ 112fs ... 4FB c.32fs ... 4FB From the falling edge of pulse P8F Sample hold signal SH
Delay until R and SHL rises a.128fs to… 9FB b.48fs to 112fs… 6FB c.32fs… 5FB pulse P8F fall to sample hold signal SH
Delay until falling of R and SHL a.128fs ~ ... 3FB b.48fs ~ 112fs ... 3FB c.32fs ... 3.5FB Therefore, the phase relationship between the word clock WCO and sample hold signals SHR, SHL at each bit clock rate is , Margin from the fall of the word clock WCO to the rise of the sample hold signals SHR and SHL (“2T” in Fig. 3) a.128fs ~… 4FB b.48fs ~ 112fs… 2FB c.32fs… 1FB sample hold signal SHR , SHL fall to the next word clock WCO fall ("T" in Fig. 3) a.128fs ~ ... 2FB b.48fs ~ 112fs ... 1FB c.32fs ... 0.5FB. In this way, in this digital filter 2a, since the number of delay circuit stages is switched according to the bit clock rate, the word clock WCO and the sample hold signals SHR, SHL are sent with an appropriate phase difference even if the bit clock rate is changed. To be done.

[BCO Generation Unit 19, Operation Control Unit 18] The operation control unit 18 and the BCO generation unit 19 operate on the bit clock B
It operates with internal clocks φ ₁₅ and φ ₁₆ that are asynchronous with CI. The calculation control unit 18 and the BCO generation unit 19 are activated each time the falling edge of the output word clock WC0 is detected. When the word clock WCO falls, it is detected by the fall detection circuit 201. Then, according to the fall detection circuit 201, the detection pulse RPA having the width τ (τ is the period of the clocks φ ₁₅ and φ ₁₆ ) is generated at the first rise of the clock φ ₁₆ after the fall of the word clock WCO. To be done. This detection pulse RPA is supplied as a reset pulse RP to the BCO counter 203 in the BCO generator 19 via the jitter absorption circuit 202. Also, this pulse RP is
It is input to the BCO control circuit 204 and also to the address counter reset circuit 206 via the delay circuit 205.
The operation of the jitter absorbing circuit 202 will be described later. Now, the BCO generator 19 will be described. The counter 203 is a 6-bit up counter and has clocks φ ₁₅ and φ ₁₆
The up count operation is performed by. The outputs Q _{0 to} Q ₅ of the counter 203 are supplied to the decoder 207. The count value of the counter 203 is "33", "37", "44", "4".
7 ”, the decoder 207 outputs detection signals P33, P37, P44, and P47 corresponding to these count values, respectively. Here, when the count value is detected, the detection signals P33, P37, and P44 are at "1" level, and the detection signal P47 is at "0" level. The detection signal P47 is input to the counter 203 as a toggle inhibit signal. The counter 203 is reset by the reset pulse RP when the word clock WCO falls. Then, the counter 203 is up-counted from the count value “0” with the input of the clocks φ ₁₅ and φ ₁₆ . Then, when the count value reaches “47”, the detection signal P is output from the decoder 207.
As a result, 47 is output, and as a result, the counter 203 enters the toggle-inhibit state, and the counting operation is stopped even if the clocks φ ₁₅ and φ ₁₆ are input. And the next word clock
It waits at the count value "47" until WCO falls and the reset pulse RP is input. On the other hand, the Q ₀ output of the counter 203 is delayed by 2τ by the delay circuit 208 and input to the AND gate 211 via the inverter 210. The other input of this AND211 gate has a BCO
The signal STOP output from the control circuit 204 is input. Hereinafter, the operation of generating the bit clock BCO in the BCO generating unit 19 will be described with reference to the time chart of FIG. When the reset pulse RP is input, the counter 203 is reset at the timing of the next clock φ ₁₆ . Further, the reset pulse RP is read by the BCO control circuit 204, and the signal STOP rises with a delay of 2τ from the rising edge of the reset pulse RP. As a result, the transmission of the bit clock BCO is on standby. The Q ₀ output of the counter 203 is the delay circuit 20.
8, output through the inverter 210 and the AND gate 211 as a bit clock BCO. When the switching signal 16/18 is at “0” level, the detection signal P33 is supplied to the BCO control circuit 204 as the end signal ED via the selector 212 when the count value of the counter 203 reaches “33”. . As a result, the signal STOP falls 2τ after the rise of the end signal ED, and thereafter the transmission of the bit clock BCO is stopped. When the switching signal 16/18 is at "1" level, the count value "37" is detected, and the transmission of the bit clock BCO is stopped. In this way, the BCO control unit 19 outputs a predetermined number of bit clocks BCO every time the word clock WCO falls. Next, the calculation control unit 18 will be described. The address counter 214 is an 8-bit up counter, and its output Q ₀
~ Q ₇ are supplied to the micro program ROM as a micro program address. A clock generation circuit 209 generates two-phase clocks φ ₁ and φ ₂ from the Q ₀ output of the counter 203 in the BCO generation unit 19. Then, the address counter performs a counting operation by the clocks φ ₁ and φ ₂ . Reference numeral 214 denotes a decoder, which outputs a detection signal P191 when the count value of the address counter 213 becomes "191". The detection signal P191 is input as a reset signal to the counter 213 via the OR gate 215. Then, the counter 213 is reset at the timing of the clock φ ₂ after the input of the reset signal. That is, the address counter 21
At 3, the count value "0" to "191" is repeated according to the clocks φ ₁ and φ ₂ . The address counter 213 has a sampling cycle FW.
It is reset at the first falling edge of the word clock WCO at. Figure 11 shows the address counter reset circuit.
The operation of 206 is shown. Input word clock SDS
When Y rises and the sampling cycle FW starts, the detection pulse RES3D is sent to the address counter reset circuit 2
Entered in 06. As a result, the set / reset flip-flop 206A is set, and the signal R3 becomes "1" level.
Then, when the output word clock WCO falls and the detection pulse RPD is input, the output signal R1 of the AND gate 206B is output.
Becomes "1". Then, this signal R1 is the OR gate 206C,
Output as signal R4 via flip-flop 206D,
The address counter 213 is reset by this signal R4. On the other hand, the signal R1 is read by the flip-flop 206E and output as the signal R2. As a result, the signal R2
Thereby, the set / reset flip-flop 206A is reset, and the signal R3 becomes "0". As a result, even if the word clock WCO falls and the detection pulse RPD is input thereafter, the reset pulse is not supplied to the address counter 213. Thus, the address counter 213 is reset at the first fall of the word clock WCO in the sampling cycle FW. Then, thereafter, the counting operation is performed in accordance with the clocks φ ₁ and φ ₂ . Now, as described above, the clocks φ ₁ and φ ₂ are generated from the Q ₀ output of the counter 203. Also counter 2
03 cycles through the count values "0" to "47" every time the word clock WCO falls. Therefore, the clock φ ₁ ,
φ ₂ is 12 each time the word clock WCO falls
They are generated one by one, and the count of the address counter 213 is advanced. Then, the microprogram address is sent from the address counter 213, and the arithmetic unit 12 (FIG. 1) executes the arithmetic operation based on the microprogram. In this way, every time the word clock WCO falls, the 12-step microprogram is executed in synchronization with the clocks φ ₁ and φ ₂ . When the execution of the 12-step microprogram is completed, the address counter 213 is stopped and the arithmetic unit 12 is in the standby state until the next fall of the word clock WCO. Then, in the sampling cycle FW, the word clock WCO falls eight times, and the microprogram of 192 steps in total is executed in one sampling cycle FW, and the sampling frequency
Digital data corresponding to a sampling frequency 8fs that is eight times fs is calculated. Next, the operation of the jitter absorption circuit 202 will be described. In this digital filter 2a, the lower limit of the frequencies of the clocks φ ₁₅ and φ ₁₆ is 384fs. However, when the clock frequency is near 384fs, the operation speed will be considerably reduced, and the next word clock WCO will fall before the previous operation is completed. The jitter absorbing circuit 202 delays the detection pulse RPA and outputs it as a pulse RP after the completion of the operation if the previous operation is not completed at the time when the word clock WCO falls and the detection pulse RPA is generated. FIG. 12 is a time chart showing the operation of the jitter absorbing circuit 202. When the count value of the counter 203 in the BCO generator 19 becomes "44", the detection signal P44 is output. Then, the signal P44 is the clock phi _15, sequentially propagated to the delay circuit D45~D49 with the phi _16. Therefore, when the count value of the counter 203 is "44", the signal P44 is "1", when it is "45", the signal P45 is "1", and so on. After 1 τ has passed, it falls. Then, as in the case of (b), when the count value of the counter 203 is detection pulse RPA when "43" is input (time t _21), the detection pulse RPA is delayed circuit D50, D
51, the AND gate 202A, the delay circuit 202B, and the OR gate 202X, the time t at which the count value of the counter 203 becomes “47”.
_{At 22} , it is output as a pulse RP. Further, as in the case of (b), when the detection pulse RPA is input when the count value of the counter 203 is “45” (time t ₂₃ ), the detection pulse RPA is delayed by the delay circuits D50, D51, and the AND gate. It is output as a pulse RP at time t ₂₂ via the 202C and the OR gate 202X. Further, as in the case of (c), when the detection pulse RPA is input when the count value of the counter 203 is “47” (time t ₂₂ ), this detection pulse RPA is passed through the AND gate 202D and passed to the time t. _{At 22} , it is output as a pulse RP. Also,
As in the case of (d), when the detection pulse RPA is input after the counter 203 has finished counting (time t
₂₄ ) This detection pulse RPA is passed through delay circuits D50, D51, inverter 202E, NOR gate 202Y, OR gate 202X,
Output as pulse RP. Thus, the detection pulse RP
The count value of the counter 203 at the time of A input, that is,
The detection pulse RPA is delayed according to the progress of the previous calculation and is supplied to the BCO generating unit 19 as a pulse R. [Advantages of the Invention] As described above, according to the present invention, a start signal generating means for generating a start signal having a frequency N times the sampling frequency of input digital data, and each bit forming the input digital data. Bit input speed detecting means for detecting the bit input speed of the digital signal, and the digital signal which is activated by the activation signal and outputs the digital data obtained as a result of the product-sum operation, and the subsequent circuit performs digital-analog based on the digital data. A means for outputting a sync signal for conversion, and an output means for controlling the output timing of the digital data and the sync signal with respect to the start signal based on the bit input speed are provided.
Regardless of the input timing specification, the output digital data as the processing result can be processed by the subsequent circuit at an optimum timing, and a digital filter capable of adapting to various input timing specifications can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a digital filter 2a according to an embodiment of the present invention.
2 is a block diagram showing the configuration of the audio signal reproducing circuit according to the same embodiment, FIGS. 3 and 4 are time charts showing the operation of the same embodiment, and FIG. 5 is the same embodiment. Sync signal generator 20 and BCO generator 1 in the example
9, a circuit diagram showing the configuration of the arithmetic control unit 18, FIG. 6 is a time chart showing the operation of the clock generation circuit SRF1 in the same embodiment, and FIG. 7 is a two-phase clock supply method for each flip-flop in the same embodiment. 8 and 9 are time charts showing the operation of the synchronizing signal generator 20 in the same embodiment, and FIG. 10 is a BCO in the same embodiment.
FIG. 11 is a time chart showing the operation of the address counter reset circuit 206 in the same embodiment, and FIG. 12 is a time chart showing the operation of the jitter absorption circuit 202 in the same embodiment. FIG. 13 is a block diagram showing the configuration of an audio signal reproducing circuit using a conventional digital filter. 2a: Digital filter, 20: Sync signal generator, 18 ...
… Operation control part, 19 …… BCO generation part.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masamitsu Yamamura, No. 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha stock company (72) Yusuke Yamamoto, No. 10-1 Nakazawa-machi, Hamamatsu-shi, Shizuoka Yamaha stock company (56) References JP-A-2-141116 (JP, A) JP-A-63-120515 (JP, A) JP-A-62-101112 (JP, A) Actual development Sho-63-158028 (JP, U) U.S. Pat. T. SHELTO N: "Signal synchronization in digital audio" ICASSP'83 PROCEDI NGS, Boston, ma, 14th-16th April 1983, pages 435-438; TEREPIN et al. : "Architure and instructions s et of a programmable LSI digital filter"

Claims (1)

(57) [Claims] 1. A predetermined product-sum operation is performed on sequentially input time-series digital data to generate digital data corresponding to a sampling frequency N times (N is an integer) the sampling frequency of the input digital data. In the digital filter, a start signal generating means for generating a start signal having a frequency N times the sampling frequency of the input digital data, and a bit input speed detection for detecting a bit input speed of each bit forming the input digital data Means for outputting digital data obtained as a result of the product-sum operation, which is activated by the activation signal, and a synchronization signal for subsequent circuits to perform digital-analog conversion based on the digital data. The digital data for the activation signal based on the bit input speed. And digital filter, characterized by comprising output means for controlling the output timing of the synchronizing signal.