JPS61214551A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce generation of noise by providing a switch element which supplies the earth potential with a large ON resistance and a switch element which supplies the earth potential with a small ON resistance with a certain delay time to an external terminals. CONSTITUTION:A series resistance and a capacitance are added to an output terminal Dout of the output circuit OB. At the timing t1 where a drive signal turns to L from H, a bipolar transistor T11 turns OFF and thereby Dout gradually changes to L from H. Meanwhile, when the drive signal changes to H from L and it reaches a threshold value of FET Q41 at the comparatively quick timing t2, Q41 turns ON and Dout is set to L with a large ON resistance. At the time t3 after the time t1, FET Q42 turns ON to come to further low level L with a small resistance which is lower than a logical threshold voltage of T<2>L. Thereby, a current does not flow during the period from time t1-t2, an extracted current of L level flows during the period from time t2-t3 where Q41 is ON, the rated current IOL of L level flows after the time t3 where Q42 is ON and a peak current (indicated by a broken line) of it can be reduced. Accordingly, generation of noise can be inhibited.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, for example, a CMO3 (complementary MO3) static type RAM.
The present invention relates to a technique that is effective for use in a semiconductor memory device configured by incorporating a bipolar transistor into a part of the peripheral circuit of a (random access memory).

[Background technology]

CMO3- in which CMOS static RAM (random access memory) is directly accessed by ECL (emitter coupled logic) circuit.
ECL compatible RAM has been published in the International Digest on Technical Papers (ISSCD).
IGEST OF TBCHNICALPAPf! R.S.
) magazine, February issue, 1982, pages 1, 248-249. Furthermore, in order to increase the speed of CMOS static RAM, a method using bipolar transistors was proposed in Japanese Patent Application Laid-Open No. 56-58193, Nikkei McGraw-Hill, May 21, 1984, Nikkei Electronics, p. 198, etc. In this way, 0M03
RA that combines a circuit and a bipolar transistor circuit
Various types of M have been proposed.

Incidentally, in a semiconductor integrated circuit device, there is a load capacitance with a relatively large capacitance value, which is composed of stray capacitance existing in a mounting board such as a printed wiring board and the input capacitance of a signal input device that is coupled to the output terminal Dout. (parasitic capacitance) is required. Therefore, the output isostatic current causes a relatively large current to flow through the power supply line and the ground line of the circuit in order to charge up or discharge the load capacitance. The power supply voltage line Vcc in a semiconductor integrated circuit such as a RAM and the circuit ground line Vs3 are
Since each has non-negligible resistance and inductance, relatively large noise is generated in each. especially,
Noise in the ground line of the circuit causes deterioration of the level margin of, for example, a sense amplifier that amplifies a minute read signal from a memory cell or an input buffer. Also, ×4
In semiconductor integrated circuit devices that have multiple output circuits, such as RAMs that are accessed in units of multiple bits such as x8 bits, this is a major problem because the noise level increases with the number of output circuits. It is something that becomes.

(Object of the Invention) An object of the invention is to provide a semiconductor integrated circuit device including an output circuit in which noise generation is reduced.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a first output isolating resistor that supplies the circuit's ground potential with a relatively large on-resistance to the external terminal, and a first output isolator that operates later than the first switching element and has a relatively small on-resistance to the external terminal. and a second switching element that supplies the ground potential of the circuit.

〔Example〕

FIG. 1 shows a static type RA to which this invention is applicable.
A block diagram of M is shown. This figure shows the internal configuration of a RAM with a storage capacity of approximately 64 bits and an output of 4 bits. In the figure, each circuit section surrounded by a broken line is formed on a single semiconductor substrate such as single crystal silicon using semiconductor integrated circuit technology.

Each static type RAM in this embodiment has 12
It has four matrices (memory arrays M-ARY1 to M-ARY4) with a storage capacity of 8 columns (rows) x 12B rows (columns) - 16384 bits (approximately 16 bits), resulting in a total of approximately 64 bits. It has a storage capacity of . An address circuit for selecting a desired memory cell MC from each memory array M-ARY 1 to memory array M-ARY 4 having a plurality of memory cells MC includes an address buffer ADB and a row address decoder R.
-DCR, column address decoder C-DCR, column switches C-3WI to C-5W4, etc.

Although not shown, each of the memory cells MC has the same configuration, and includes a pair of N-channel storage MOSFETs whose gates and drains are cross-connected to each other, and a pair of N-channel storage MOSFETs whose gates and drains are cross-connected to each other. A resistor for holding information, and a pair of complementary data lines to the above-mentioned memory MOS FET.

and an N-channel transmission gate MO3FET provided between each of them and D. The above memory cell MC
holds stored information by supplying power supply voltage Vcc to the connection point of the resistor.

The above resistance is the memory cell M in the storage information retention state.
In order to reduce the power consumption of C, it is made to have a high resistance value, for example, several megohms to several gigaohms. Also,
The above resistance reduces the area occupied by the memory cell, so
For example, it is composed of a relatively high-resistance polysilicon layer formed on the surface of a semiconductor substrate forming a MOSFET with an insulating film interposed therebetween.

Signal circuits that handle reading/writing of information are not particularly limited, but include data input circuits DIBI to DIB4. Data output circuit DOBI-DOB4゜Sense amplifier SAI~
Consists of 5A16.

The timing circuit for controlling information read/write operations is not particularly limited, but may be internal! It consists of a II signal generation circuit COM-GE and a sense amplifier selection circuit GS.

The row address selection lines (word lines W1 to W128) have 128 lines obtained based on the address signals AO to A6.
A decoded output signal according to the row decoder R-OCR is sent out. This decode output signal is transmitted from two memory arrays M-ARYI arranged on the left and right sides of the row address decoder R-DCR, although not particularly limited.
M-ARY2 and memory array M-ARY3. M-ARY
It is commonly supplied to the four word lines W1 to W128.

128 decoded output signals obtained based on address signals A7 to A13 are sent to column-system address selection lines Yl to Y128 from a column decoder C-DCR. This decoded output signal is not particularly limited, but
Two column switches C-5WI and C- are placed on the left and right sides of the column address decoder C-DCR.
3W2 and C-3W3. Commonly supplied to C-5W4.

Address pants fADB receives address signals AO-A13 supplied from external terminals and forms internal complementary address signals aO-A13 based thereon. Note that the internal complementary address signal 0 is composed of an internal address signal aO having the same phase as the address signal AO, and an internal address signal aO having the phase inverted with respect to the address signal AO. The remaining internal complementary address signals! Similarly, signals 1 to 13 are composed of internal address signals a1 to a13 having the same phase and internal address signals al to 13 having phase inversion.

Among internal complementary address signals 10 to 13 formed by address buffer ADB, although not particularly limited,
Internal complementary address signals i7 to i13 are supplied to column address decoder C-DCH. Column address decoder C-DCR receives these internal complementary address signals a7
．． ~a13t7 is decoded (decoded), and the selection signal (decoded output signal) obtained by the decoding is sent to the MO5FE for the switch in the column switch c-swt~C-3W4.
T (insulated gate field effect transistor) Q6゜Q6~
Q7. Supplied to gates such as Q7.

Each memory array M-ARY1 to memory array M-ARY
Among the word lines W1 to W128 in 4, one word line designated by a combination of address signals AO-A6 from the outside is connected to the above-mentioned row address decoder R-
DCH selects the address signal A7 from the outside by the column address decoder C-DCR mentioned above.
A pair of complementary data lines specified by the combination of .about.A13 is selected from among 128 pairs of complementary data lines. As a result, in each memory array M-ARY1 to memory array M-ARY4, each one
memory cells MC are selected.

The storage information read from the selected memory cell MC is stored on four pairs of sub-common complementary data lines CDi, CDI~
CD4. Appears on one of CD4. That is, the subcommon complementary data lines CD1°CDI to CD4. CD4 corresponds to memory blocks M1 to M4 in which 128 pairs of complementary data lines are divided into 32 pairs each, like the memory array M-ARYI shown as a representative. Sense amplifiers SAI to SA4 are connected to the divided sub-common complementary data lines CD1. CDI~CD4. They are provided corresponding to C-4.

In this way, subcommon complementary data lines CDI, CD1 to CD
4. The purpose of dividing into CD4 and providing sense amplifiers SAI to SA4 for each is to divide (reduce) the parasitic capacitance of the common complementary data line and to speed up the information read operation from the memory cell.

The sense amplifier selection circuit GS receives the address signal A12.
．． Based on A13, four combinations are decoded to form sense amplifier selection signals ml to m4.

The above four sense amplifiers SAI to SA4 (SA5 to S
A8, SA9 to 5A12 and 5A13 to 5A16), one sense amplifier corresponding to the complementary data line selected by the column switch receives selection signals m1 to
activated by m4 and timing signal asc,
The output is transmitted to the common complementary data lines CDL, CDL.

The common complementary data lines CDL, CDL are coupled to the input terminal of the data output circuit DOB and the output terminal of the data input circuit DIB. In the write operation, the divided sub-common complementary data lines CD1. CDI~C
D4. , CD4 are transmission gate MOSFETs QI, Ql to Q5 . which receive the write control signal we. Shorted by Q5.

The internal control signal generation circuit COM-GS receives two external control signals CS (chip select signal) and WE (write enable signal) and generates internal chip selection signals csl and sa.
c (sense amplifier operation timing signal), we (write control signal), dic (data input control signal) and do
c (data output control signal), etc.

Figure 2 shows the sense amplifier SA and data output circuit DOB.
A circuit diagram of one embodiment is shown. In the same figure, MOSFETQ27 etc. with a straight line attached to the channel part are as follows:
P-channel MO3FET, N-channel MO5
It is distinguished from FETQ20 etc.

Sense amplifier SA connects subcommon complementary data lines CD, C
A differential bipolar transistor T5.D has its base coupled to T5. T6, and an N-channel MO3FETQ that is provided between its common emitter and the ground potential point of the circuit, and that selectively allows an operating current to flow in response to a control signal sac-mi.
21. This differential transistor T5.
The collector of T6 is the common complementary data line CDL, CDL
are respectively combined. Although not shown, the collectors of the differential transistors constituting the remaining three similar sense amplifiers shown in FIG. 1 are also commonly connected to the common complementary data 1jlcDL and CDL.

The output signal of the sense amplifier appearing on the common complementary data lines CDL, CDL is amplified into an output signal such as VECL (emitter coupled logic) by the first stage circuit PDO of the data output circuit DOB. The above common complementary data line CDL.

CDL is a common base amplification transistor T7. Coupled to the emitter of T8. These transistors T7. T8
At the base of the diode D1. A bias voltage (Vcc-2Vf) formed by D2 and MOSFET Q23 as a constant current source through which its operating current flows is supplied.

Note that Vf is the diode D1. This is the forward voltage of D2. Said transistor T7. A constant current source that flows the bias current is connected between the emitter of T8 and the ground potential point of the circuit, and a r(7) MOSFET Q22. Q24 will be established. The transistor T7. Load resistors R1 and R2 are provided at the collector of T8.

These common base type amplification transistors T7. The collector output of T8 is the emitter follower output transistor T9
．． TIO and level shift diode D3. It is transmitted to the next output circuit OB via D4.

Note that the output transistor T9. The emitter of TLQ is provided with MOSFETs Q25 and Q26 as constant current loads. MO3FETQ as each constant current source above
22 to Q26 are selectively activated by an internal chip selection signal cs, although this is not particularly limited. As a result, when the chip is not selected, the MO3FETs Q22 to Q26 are turned off to reduce power consumption.

The output circuit OB is selectively activated by a power switch MO3FET, and has a level conversion function by a differential amplifier circuit having an active load circuit in the form of a current mirror.
This realizes an output enable function. That is,
The above-mentioned ECL level complementary signal formed by the first stage circuit PDO is on the one hand connected to a P-channel type differential amplifier M.
Supplied to the gates of O3FETQ2B and Q29. This differential amplification MO5FETQ28. Between the common source of Q29 and the power supply voltage Vcc, there is a P-channel power switch MO5 that receives the operation timing signal doc.
FETQ27 is provided. Above differential increase @MO5FET
Q28. Between the drain of Q29 and the ground potential point of the circuit, there is an N-channel active load MO3FET Q30. Q31 is provided. Then, MO3FETQ29, which is the output of the differential amplifier circuit,
, Q31 and the ground potential point of the circuit are connected to an N-channel M which receives the control signal doc.
An O3FETQ3B is provided.

On the other hand, the ECL level complementary signals are supplied in opposite phases to the inputs of the similar differential amplifier circuits (Q32 to Q40). However, since the differential amplifier circuit of this embodiment forms two types of drive signals, two current mirror MO3FETs Q35°Q37 on the output side are provided. Two P-channel MO3FETQ3 receiving the same input signal are connected to the drains of these MOS FETQ35 and Q37.
4. Q36 is provided. Above MO5FETQ34. Q
One of the MO5FETQ34 among MO5FETQ34 forms a high-level drive signal at a relatively quick timing by making its conductance relatively large. On the other hand, the conductance of the other MOS FETQ36 is made relatively small, thereby forming a delayed drive signal that is brought to a high level at a later timing.

These differential increases @MO5FETQ32. Q34 and Q3
The common source of 6 includes the power switch MO
Operating current is commonly supplied from 3FETQ27. As a result, when the control signal doc is at a low level, the power switch MO3FETQ27 is turned on and supplies operating current to the two sets of differential amplifier circuits. An output signal is obtained. On the other hand, if the control signal doc is at a high level, the power switch MO3FETQ27 is turned off, so
Both sets of differential amplifier circuits are rendered inactive. In this case, the N-channel MO3FETs Q3B, Q39, and Q40 are all turned on by the high level of the control signal doc, so that output signals with all of them set to low level are obtained from their outputs.

When the control signal doc performs a level conversion operation when the control signal doc is at a low level, the differential amplification MOSFETQ28. Q29 (Q32
．． Q34 and Q36) Among them, the amplifier MO3FET Q28 (Q32) whose drain is connected to the drain of the current mirror MOSFET Q30 (Q33) on the input side is turned on by the low level signal supplied to its gate and outputs a low level side output signal. N channels M forming
It is sufficient to have an operating current sufficient to bring the gate of O3FETQ31 (Q35.Q37) to a high level. Therefore, although not particularly limited, these MOSFETQ2B,
The conductance of Q32 is made relatively small.

As a result, most of the operating current supplied from the power switch MO3FETQ27 flows to one differential amplifier circuit that forms a high-level output signal, and the remaining minute current flows to the other differential amplifier circuit that forms a low-level output signal. It is distributed so that it flows to the amplifier circuit. As a result, in the two sets of differential amplifier circuits of this embodiment, the operating current is used to efficiently form the output signal, so that the level conversion (amplification) operation can be performed after low power consumption. I can do it.

Although the output signals of the two sets of differential amplifier circuits are not particularly limited, the base of an emitter follower output transistor Tll constituted by a bipolar type NPN) transistor that sends a high level output signal to an external terminal Dout;
External terminal Dout Sends a low level output signal N
Channel output MO5FETQ41. This will be communicated to the gate of Q42.

Above output MO5FETQ41. Among Q42, the conductance of MO5FETQ41, which receives the drive signal set to high level at a relatively early timing as described above, is made relatively small. In other words, the on-resistance is made to have a relatively large resistance value. On the other hand, MO5FETQ42, which receives a drive signal that is brought to a high level at a late timing as described above, has a relatively large conductance.
TQ41 is made to have a relatively large resistance value sufficient to form a level lower than the logic threshold voltage of TTL by its on state. On the other hand, MO3FETQ42 has a combined resistance value of TT even when a low level drive current (IoL) is applied from the external terminal.
It is made to have a small on-resistance necessary to form an L low level. Note that in order to make the output signal sent to the external terminal Dout TTL level, the above transistor Tl
A diode D5 for level shifting is provided at the emitter of 1.

The operation of the output circuit OB will now be described with reference to FIG.

A series resistor and a capacitor constituting a power supply voltage dividing circuit as a known measuring load circuit are added to the output terminal of the output circuit shown in FIG. 2 above.

At timing t1 when the high-level drive signal is changed to low level, the transistor Tll is turned off.

As a result, the output terminal Dout is placed in a high impedance state, so that the high level output signal is gradually brought to a low level by the measuring resistance circuit. On the other hand, when the low level drive is set to high level and reaches the threshold voltage of MO3FETQ41 at a relatively early timing t2, this MO3FETQ41 is turned on and the output signal is pulled out to the low level by a relatively large on-resistance. reduces the output signal to a level below the logic threshold voltage of its TTL level. However, as a result of the relatively large on-resistance value of this MO3FET Q41, even if it continues to be in the on state, when a low level drive current (I oL) is flowing from the external terminal Dout, the current level as shown by the dotted line in the figure In this embodiment, only a low level with a relatively high residual voltage can be formed.
At timing t3 delayed from operation timing t2 of FETQ41, output MO5FETQ42 is turned on and its output signal is brought to a lower level. Thereby, a TTL low level can be formed even with the above-mentioned current. The current that flows due to the above operation does not flow from timing t1 to t2, and a current drawn to a low level flows between timing t2 and t3 when MO3FET Q41 is turned on. Furthermore, after timing t3 when MO5FETQ42 turns on, the low level rated current (I
oL) flows.

In this example, MO5F has a relatively large on-resistance.
Since the high-level output signal is changed to low level by the ETQ41, the peak current value can be reduced, and the generation of noise can be suppressed. MO3F has a relatively low on-resistance and turns on with a delay.
ETQ42 allows desired low level compensation.

Note that the MO3FETQ that forms the above low level signal
When 42 is turned on at an early timing t1, the fall of the output signal becomes faster as shown by the broken line in the same figure, but due to the large peak current flowing, the inductance and resistance components of the wiring, which cannot be ignored, cause the output signal to fall at a high level. This will generate noise.

〔effect〕

(1) A switching element with a relatively large on-resistance value changes a high-level output signal to a low level, and the on-state is delayed after this, and a switching element with a small on-resistance value compensates for the output low level. be. This makes it possible to limit the current when the output changes, thereby reducing the noise level generated in the ground line of the semiconductor integrated circuit. Therefore, it is possible to obtain the effect that the operating margin of the semiconductor integrated circuit can be increased.

(2) According to the above (1), since the peak current value flowing through the output circuit can be reduced, it is possible to reduce electromigration rays and improve reliability.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. For example, all switching elements making up the output circuit may be made up of MOSFETs or bipolar transistors.
Further, the driving signal for the switching element having a relatively small on-resistance may be any signal that is substantially delayed.

Furthermore, the memory cell M in the static RAM
C may use a CMOS flip-flop circuit using a P-channel MO3FET in place of the melon resistor.Furthermore, the specific circuit configuration of the other peripheral circuits constituting the static RAM may be determined by various implementations. It can take any form. For example, the present invention applies not only when the output level changes from "H" to "L", but also when switching from "L" to "H".
Effects can be obtained by using a similar circuit when switching to .

[Application field]

In addition to the above-mentioned static type RAM, this invention
It can be widely used in various semiconductor integrated circuit devices including output circuits that require relatively large current drive.

[Brief explanation of the drawing]

FIG. 1 shows a static type R showing an embodiment of the present invention.
A block diagram of the AM. FIG. 2 is a circuit diagram showing an embodiment of the sense amplifier and data output circuit, and FIG. 3 is an operation waveform diagram showing an example of the operation of the output circuit. M-ARYI~M-ARY4...Memory array (memory matrix), MC...Memory cell, GS...Sense amplifier selection circuit, C-DCR...Column address decoder, SAI~5A16...Sense amplifier, COM-G
E: Internal control signal generation circuit, R-DCR: Row address decoder, ADB: Address buffer, C-3W
I~C-5W4...Column switch, DIBI~DIB
4...Data input circuit, DOB 1 to DOB4...Data output circuit

Claims (1)

[Claims] 1. A first output switching element that receives a drive signal and supplies a circuit ground potential with a relatively large on-resistance to an external terminal, and a first output switching element that receives a substantially delayed signal of the drive signal. and a second switching element that supplies a ground potential of the circuit to the external terminal with a relatively small on-resistance. 2. A patent characterized in that the above two switching elements are provided with a third switching element that operates complementary to these switching elements and sends a signal on the power supply voltage side to an external terminal. A semiconductor integrated circuit device according to claim 1. 3. The first and second switching elements are MOSFETs.
3. The semiconductor integrated circuit device according to claim 1, wherein the third switching element is a bipolar transistor.