JPS61214496A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS61214496A JPS61214496A JP5734685A JP5734685A JPS61214496A JP S61214496 A JPS61214496 A JP S61214496A JP 5734685 A JP5734685 A JP 5734685A JP 5734685 A JP5734685 A JP 5734685A JP S61214496 A JPS61214496 A JP S61214496A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- adhesive
- circuit device
- hybrid integrated
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、混成集積回路装置に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a hybrid integrated circuit device.
第2図は従来の混成集積回路装wtを示す概略断面図で
、集積回路基板1上の゛電極2にチップ部品3を接着剤
4によって仮付けした後、半田5によって半田付けした
状態を示すものである。FIG. 2 is a schematic cross-sectional view showing a conventional hybrid integrated circuit device wt, showing a state in which a chip component 3 is temporarily attached to an electrode 2 on an integrated circuit board 1 with an adhesive 4 and then soldered with a solder 5. It is something.
上記のような従来の混成集積回路装置は、集積回路基板
1上の部品を構成すべき電極2間に適量と思われる仮付
は用の接着剤4を印刷機を用いて印刷し、その後チップ
部品3’にプV−シングする。In the conventional hybrid integrated circuit device as described above, a printing machine is used to print an appropriate amount of adhesive 4 for temporary bonding between the electrodes 2 constituting the components on the integrated circuit board 1, and then the chips are bonded together. V-thing part 3'.
接着剤4の塗布後、集積回路基板1を半田ディッピング
することKより、チップ部品3は電極2間に半田5によ
り半田付けされ、混成集積回路装置の組立が完了する。After applying the adhesive 4, the integrated circuit board 1 is subjected to solder dipping, whereby the chip component 3 is soldered between the electrodes 2 with the solder 5, and the assembly of the hybrid integrated circuit device is completed.
しかしながら、従来の接着剤4による仮付けでは第3図
に示すよ5に、ff1着剤4の印刷膜厚は接着剤4の物
理的性質のばらつきと、印刷条件などのばらつきKより
一定のものが得られず、チップ部品3をプレースしても
仮付けされなかったり。However, in the case of tacking using the conventional adhesive 4, the printed film thickness of the ff1 adhesive 4 is constant due to variations in the physical properties of the adhesive 4 and variations in printing conditions, etc. could not be obtained, and even if chip part 3 was placed, it could not be temporarily attached.
接着剤4が多すぎて電極2上やチップ部品3に付着して
外観または電気的不具合を生じるなど問題点かあづた。There were problems such as too much adhesive 4 adhering to the electrodes 2 and chip components 3, resulting in appearance or electrical defects.
この発明は、上記のような問題点を解消するため罠なさ
れたもので、接着剤が塗布された際の膜厚を一定に保ち
被接着部品の仮止めt接層不良が生ずることがないよう
にして組立ができる混成果積回路装置を提供することを
目的とする。This invention was made to solve the above problems, and it is designed to maintain a constant film thickness when adhesive is applied and to prevent bonding defects during temporary bonding of parts to be adhered. The object of the present invention is to provide a hybrid product circuit device that can be assembled by using the following methods.
この発明の混成集積回路装置は、被接層部品の仮付(す
用の接着剤中に、シリカまたはアルミナなどの所定形状
の固形物からなる安定物質を混入させ、この接着剤を使
用して被接着部品を仮付けするようにしたものである。The hybrid integrated circuit device of the present invention mixes a stable substance consisting of a solid substance of a predetermined shape, such as silica or alumina, into an adhesive for temporarily attaching layer components to be bonded, and uses this adhesive. This is for temporarily attaching parts to be adhered.
この発明においては、接着剤中に所定形状の安定物質を
混入したため、集積回路基板上に塗布された接着剤は一
定の膜厚が得られる。In this invention, since a stable substance having a predetermined shape is mixed into the adhesive, the adhesive coated on the integrated circuit board can have a constant thickness.
第1図はこの発明の一実施例を示す混成集積回路装置の
概略断面図である。第1図において−40はこの発明に
よる被接着部品の仮付は用の接着剤、41はその接着剤
40中に混入したシリカまたはアルミナ等の所定形状か
らなる安定物質であり、その他は第2図9第3図と同じ
ものである。FIG. 1 is a schematic sectional view of a hybrid integrated circuit device showing an embodiment of the present invention. In FIG. 1, -40 is an adhesive used for temporarily attaching parts to be bonded according to the present invention, 41 is a stable substance of a predetermined shape such as silica or alumina mixed in the adhesive 40, and the others are secondary FIG. 9 is the same as FIG. 3.
次Km着工程について説明する。Next Km arrival process will be explained.
集積回路基板1上に設けられた被接着部品1例えはチッ
プ部品3を塔載すべき電極2間に、この発明による被接
着部品の仮付は用の接着剤40′%:印刷する。この接
着剤40中には、適当な印刷膜厚が得られるような一定
形状の安定物質41が含浸させであるため、その大きさ
により印刷される接着剤40の膜厚は一定に保たれるた
めチップ部品3を仮付けした場合、接着剤40の少なす
ぎ。A 40% adhesive used for temporary attachment of the bonded components according to the present invention is printed between the electrodes 2 on which the bonded components 1, for example, the chip components 3, are to be placed on the integrated circuit board 1. Since the adhesive 40 is impregnated with a stable substance 41 having a certain shape to obtain an appropriate printing film thickness, the thickness of the printed adhesive 40 is kept constant depending on its size. Therefore, when the chip component 3 is temporarily attached, there is too little adhesive 40.
または多すぎによる接着不良を生ずることがなくなる。Also, there is no possibility of poor adhesion due to too much.
なお、上記実施例では、チップ部品3について説明した
が、他の部品でも集積回路基板との間隙を保つ必要のあ
る部品について同様に適用できる。In the above embodiment, the description has been made regarding the chip component 3, but the present invention can be similarly applied to other components that need to maintain a gap with the integrated circuit board.
また上記実施例では、印刷方式について令説明したが、
これ以外、゛例えばディスペンス方式で接着剤40を塗
布する方式でも、この安定物質41入りの接着剤4(l
使用することKより、安定な膜厚が得られる。In addition, in the above embodiment, the printing method was explained, but
In addition to this, for example, even if the adhesive 40 is applied by a dispensing method, the adhesive 4 (l) containing this stable substance 41 may be used.
By using K, a stable film thickness can be obtained.
この発明は以上説明したとおり、接着剤中に所定形状か
らなる安定@’X’を混入せしめたので、集積回路基板
上Km布された接着剤は一定の膜厚を保持することがで
き、接着剤の少なすぎ、または多すぎ罠よる被接層部品
の優者不良を生ずることがなくなり1歩留りのよい混成
集積回路装置が得られる利点がある。As explained above, in this invention, a stable @'X' having a predetermined shape is mixed into the adhesive, so that the adhesive spread over the integrated circuit board can maintain a constant film thickness. There is an advantage that a hybrid integrated circuit device with a high yield can be obtained since there is no possibility of defective parts in the contact layer due to too little or too much agent.
第1図はこの発明の一実施例を示す混成集積回路装置の
部分断面図、第2図、第3図は従来の混成集積回路装置
の部分断面図である。
図において、1は集積回路基板、2は電極、3はチップ
部品、5は半田、40は仮付は用の接着剤、41は安定
物質である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大岩 増雄 (外2名)
第1図
第2図
第3図
手続補正書(自発)FIG. 1 is a partial sectional view of a hybrid integrated circuit device showing an embodiment of the present invention, and FIGS. 2 and 3 are partial sectional views of a conventional hybrid integrated circuit device. In the figure, 1 is an integrated circuit board, 2 is an electrode, 3 is a chip component, 5 is solder, 40 is an adhesive for temporary bonding, and 41 is a stable substance. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3 Procedural amendment (voluntary)
Claims (1)
着剤により仮付けした後、前記集積回路基板上の電極間
に半田付けされる混成集積回路装置において、前記接着
剤中に所要の膜厚が得られる所定形状の安定物質を混入
したことを特徴とする混成集積回路装置。In a hybrid integrated circuit device in which an adhesive is applied onto an integrated circuit board, parts to be adhered are temporarily attached with the adhesive, and then soldered between electrodes on the integrated circuit board, a required film is added to the adhesive. A hybrid integrated circuit device characterized in that a stable substance having a predetermined shape that can obtain a thickness is mixed therein.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5734685A JPS61214496A (en) | 1985-03-19 | 1985-03-19 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5734685A JPS61214496A (en) | 1985-03-19 | 1985-03-19 | Hybrid integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61214496A true JPS61214496A (en) | 1986-09-24 |
Family
ID=13053009
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5734685A Pending JPS61214496A (en) | 1985-03-19 | 1985-03-19 | Hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61214496A (en) |
-
1985
- 1985-03-19 JP JP5734685A patent/JPS61214496A/en active Pending
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