JPS5999792A - Method of specifying solder amount on soldering surface after preliminary soldering - Google Patents
Method of specifying solder amount on soldering surface after preliminary solderingInfo
- Publication number
- JPS5999792A JPS5999792A JP21026982A JP21026982A JPS5999792A JP S5999792 A JPS5999792 A JP S5999792A JP 21026982 A JP21026982 A JP 21026982A JP 21026982 A JP21026982 A JP 21026982A JP S5999792 A JPS5999792 A JP S5999792A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- soldering
- chip carrier
- preliminary
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は１回路基板に搭載する部品の予備半田後の半田
面の半田量規制方法に係り、とくに搭載部品に予備半田
を行なったのち該半田量を規制する予備半田後の半田面
の半田量・の規制方法に関するものである。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a method for regulating the amount of solder on the solder surface after pre-soldering of components mounted on a circuit board, and particularly relates to a method for regulating the amount of solder on the solder surface after pre-soldering of components mounted on a circuit board. This invention relates to a method for regulating the amount of solder on the solder surface after preliminary soldering.
（１））従来技術と問題点
従来１回路基板上に搭載する部品たとえばチップキャリ
ヤパンゲージを搭載する場合、！！、ず前記回路基板上
に前記チップキャリヤパンゲージの端子に対応するパタ
ーンをスクリ−ン印刷法によってハン、クペーストを印
刷しておき、該半田ペースト上に前記チップキャリヤパ
ンゲージを搭載して半田付けが行なわれていた。このよ
う々チップキャリヤパンゲージの半田付は方法を第１図
に示し。(1)) Prior art and problems Conventionally, when mounting components such as a chip carrier pan gauge on a circuit board,! ! First, a pattern corresponding to the terminals of the chip carrier pan gauge is printed on the circuit board using a screen printing method, and the chip carrier pan gauge is mounted on the solder paste and soldered. was being carried out. The soldering method for the chip carrier pan gauge is shown in FIG.
（ａ）はチップキャリヤパンゲージの斜視図、（ｂ）は
回路基板の要部斜視図、（Ｃ）はチップキャリャ／＜ン
グージを実装した斜視図であって、ｌは＠囲に複数の端
子を典備してなるチップキャリヤパンゲージ。(a) is a perspective view of the chip carrier pan gauge, (b) is a perspective view of the main parts of the circuit board, (C) is a perspective view of the chip carrier/<gunge mounted, and l indicates a plurality of terminals surrounded by @. A chip carrier pan gauge is provided.
２はパターン２１を形成してなる回路基板、３はパター
ン２上上に印刷したバンククリーム、４は散乱した半田
粒残液である。2 is a circuit board formed with the pattern 21, 3 is the bank cream printed on the pattern 2, and 4 is the scattered solder grain residual liquid.
回路基板２の所定位置に形成してなるパターン２１上に
バンク”クリーム３をスクリーン印刷法により印刷し、
該ハンダクリーム３上にチンブキャリャパングージ１′
ｆ：載置した状態で、前記回路基板を熱板またはトンネ
ル炉等でリフローツルターリングするか、または回路基
＆２上にチンブキャリヤパンケージｌを紫外線硬化形振
着剤等で固定しておきティンツーソルダリングする方法
がとられている。ところが前者は第１図（ｃ）に示すよ
うにチップキャリヤパッケージ１の下面あるいは近辺に
はんだ残渣が散乱し、後渚は半田フリンジ等が発生する
というそれぞれ問題点があった。Bank "cream 3 is printed on the pattern 21 formed at a predetermined position of the circuit board 2 by screen printing method,
Apply chimbu kya panguji 1' on the solder cream 3.
f: In the mounted state, reflow the circuit board with a hot plate or tunnel furnace, or fix the chimbu carrier pange l on the circuit board &2 with an ultraviolet curing adhesive or the like. A method of soldering is used. However, as shown in FIG. 1(c), the former method has problems in that solder residue is scattered on or near the bottom surface of the chip carrier package 1, and solder fringes are generated at the rear edge.
（Ｃ） 発明の目的
木発グｊは、上記従来の問題点に鑑み２回路基板にチッ
プキャリヤパッケージを搭載するに先立ち、該チップキ
ャリヤパッケージの端子に予備半田を行なって半田付け
するようにした予備半田後の半田面の半田量規制方法を
提供するとさを目的とするものである。 “
（ｃｌ） 発明の構成
前述の目的を達成するために本発明は１回路基板に搭載
部品を半田付けする工程における予価半田後の半田面の
半田量規制力法であって１前記搭載部酷に予備半田を行
なったのち、該予備半田面を熱板上に搭載した半田の行
名し難い部材からなる基板上に載Ｉｌｉ′ｉシて、前記
予備半田面の半田量を規制するようにしたことによって
達成される。(C) Purpose of the Invention In view of the above-mentioned problems with the conventional technology, Kichihagu J has developed a method in which the terminals of the chip carrier package are pre-soldered and soldered before the chip carrier package is mounted on the circuit board. The purpose of this invention is to provide a method for regulating the amount of solder on the solder surface after preliminary soldering. (cl) Structure of the Invention In order to achieve the above-mentioned object, the present invention provides a method for regulating the amount of solder on the solder surface after pre-soldering in the process of soldering components mounted on a circuit board, and 1. After pre-soldering, the pre-soldered surface is placed on a board made of a material whose solder line is difficult to name, which is mounted on a hot plate, and the amount of solder on the pre-soldered surface is regulated. achieved by doing.
（ｅ）発明の実施例
以下図面を参照しながら本発明に係る予備半田後の半田
面の半田量規制方法の実施例について詐細に説明する。(e) Embodiments of the Invention Hereinafter, embodiments of the method for regulating the amount of solder on the solder surface after preliminary soldering according to the present invention will be described in detail with reference to the drawings.
第２図は本発明の一実施例を説明するだめの（ａ）はチ
ップキャリヤパッケージの斜視図、（ｂ）は予備半田を
行なったチップキャリヤパッケージの斜視図、（Ｃ）は
予備半田を行なったチップキャリヤパッケージを熱板に
載置した半田が付着し難い基板上に搭載した正面図７（
ｄ）は半田かを規制したチップキャリヤパッケージの正
面図、（ｅ）は回路基板の斜視図、（ｆ）回路基板上に
チップキャリヤパンゲージを搭載した斜視図であって、
前回と同等の部分については同一符号を付しており、５
は端子１１に予備半田５１を行なったチップキャリヤパ
ッケージ１６は半田ＴＡ演、７は半田が付層し難いたと
えばアルミ板等から々る基板、８は熱板である。2 illustrates an embodiment of the present invention. (a) is a perspective view of a chip carrier package, (b) is a perspective view of a chip carrier package after preliminary soldering, and (C) is a perspective view of a chip carrier package after preliminary soldering. Front view 7 shows a chip carrier package mounted on a hot plate to which solder is difficult to adhere.
d) is a front view of a chip carrier package with controlled solder, (e) is a perspective view of a circuit board, and (f) is a perspective view of a chip carrier pan gauge mounted on the circuit board,
The same parts as the previous one are given the same reference numerals, and 5
The chip carrier package 16 with preliminary solder 51 applied to the terminals 11 is a solder TA process, 7 is a substrate made of, for example, an aluminum plate to which solder is difficult to be deposited, and 8 is a hot plate.
チップキャリヤパッケージ１を回路基板２に搭載するに
先立ち、Ｕ記チンプキャリャパンクージ１の端子１１に
予備半田５１を行うと、チップキャリヤパッケージ５０
下部端子に半田残渣６を形成する。この半田残渣６はす
べての端子に同量となるとけ限らない。しだがってこの
ままの状態で回路基板２に搭載するとチップキャリヤパ
ッケージ５が頷いたり溶着しない端子ができて信頼性上
よくない結果となるおそれがある３、そこで該チップキ
ャリヤパッケージ５を熱板８上に搭載したアルミ板等か
らなる基板７上に載置して水平状に押圧するとすべての
端子の半田残渣６が等量となる。Before mounting the chip carrier package 1 on the circuit board 2, preliminary soldering 51 is applied to the terminals 11 of the U chimp carrier package 1.
Solder residue 6 is formed on the lower terminal. The amount of solder residue 6 is not necessarily the same for all terminals. Therefore, if the chip carrier package 5 is mounted on the circuit board 2 in this state, there is a risk that the chip carrier package 5 will bend or some terminals will not be welded, resulting in poor reliability. When placed on a substrate 7 made of an aluminum plate or the like mounted above and pressed horizontally, the amount of solder residue 6 on all terminals becomes equal.
このように半田ｈ１が規制して半田残渣６′としたチッ
プキャリヤパッケージ５を回路基板２上に形成したパタ
ーン２１に合致するよう載置して、トンネル併重たは熱
板で前記チップキャリヤパンケージ５の半田残渣６′を
溶融して回路基板２のパターン２１と接着した状態で除
冷すればよい。The chip carrier package 5 which has been regulated by the solder h1 and has become the solder residue 6' is placed so as to match the pattern 21 formed on the circuit board 2, and the chip carrier package 5 is placed on the circuit board 2 using a tunnel or a hot plate. The solder residue 6' of the cage 5 may be melted and allowed to cool while being adhered to the pattern 21 of the circuit board 2.
なお１本実施例では半田か付名し難い基板７をアルミ板
について説明したが、アルミ板に限らずアルミナ板その
他であっても構わない。また搭載部品もチップキャリヤ
パッケージ１について詳述したが、チップキャリヤパッ
ケージに限らず平面的に接着する他の搭載部品にも適用
が可能である。In this embodiment, an aluminum plate is used as the substrate 7, which is difficult to label with solder. However, the substrate 7 is not limited to an aluminum plate, but may be an alumina plate or the like. Further, although the mounted components have been described in detail with respect to the chip carrier package 1, the present invention is not limited to the chip carrier package, but can be applied to other mounted components that are bonded in a planar manner.
（ｆ＋ 発明の効果
以上の説明からＥＪ４らかなように本発明に係る予備半
田後の半田面の半田量規制方法によれば、従来の予備半
田を行わないチップキャリヤパッケージの接着にくらべ
て半田残渣の散乱および半田ブリッジ等の障害を発生す
るおそれが無くなり接着が確実に行えるので、信頼性の
向上に寄与するところが犬である。(f+ Effects of the Invention From the above explanation, it is clear that according to the method for regulating the amount of solder on the solder surface after pre-soldering according to the present invention, the amount of solder residue on the solder surface after pre-soldering is reduced compared to the conventional bonding of a chip carrier package without pre-soldering. Since there is no risk of problems such as scattering of solder and solder bridges, and bonding can be performed reliably, the dog contributes to improved reliability.
【図面の簡単な説明】
第１図は従来のチンプキャリャノ・ングージの半田付は
方法を説明するための（ａ）はチップキャリヤパッケー
ジの斜視図、（ｂ）は回路基板の要部斜視図。
（Ｃ）はチップキャリヤパッケージを実装した斜視図。
第２図は本発明に係る予備半田後の半田面の半田量規制
方法の一実施例を説明するだめの（ａ）はチップキャリ
ヤパッケージの斜視図、（ｂ）は予備半田を行なったチ
ップキャリヤパンゲージの斜視図、（Ｃ）は予備半田を
行なったチップキャリャパングージを熱板に載置した半
田が付着し難い基板上に搭載した止血図、（ｄ）は半田
量を規制したチンプキャリャバングージの正面図、（ｅ
）は回路基板の斜視図。
（ｆ）は回路基板上にチンプキャリャノくンクージを搭
載した斜視図である。
図において、１および５はナンプキャリャバンケージ、
２は回路基板１３は半田クリーム、４は半田粒残渣、６
および６′は半田伐浩、７は基板。
８は熱板、１］は端子 ２１はバクーン、５１は予価半
田をそれぞれ示す。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a chip carrier package, and FIG. 1B is a perspective view of a main part of a circuit board, for explaining a conventional Chimp Caliano-Nguzi soldering method. (C) is a perspective view of a chip carrier package mounted thereon. FIG. 2 illustrates an embodiment of the method for controlling the amount of solder on the solder surface after preliminary soldering according to the present invention. (a) is a perspective view of a chip carrier package, and (b) is a perspective view of the chip carrier after preliminary soldering. A perspective view of a pan gauge, (C) is a hemostatic diagram with a pre-soldered chip carrier pan gauge placed on a hot plate on which solder does not easily adhere, and (d) is a chimp with a controlled amount of solder. Front view of Kyaravanguj, (e
) is a perspective view of the circuit board. (f) is a perspective view of the chimp carrier mounted on the circuit board. In the figure, 1 and 5 are number carrier bank cages,
2 is solder cream for the circuit board 13, 4 is solder grain residue, 6 is
and 6' is Norihiro Handa, and 7 is the board. 8 is a hot plate, 1] is a terminal, 21 is a back cover, and 51 is a preliminary solder.
Claims (1)
備半田後の半田面の半田ｌ規制方法であって、前記搭載
部品に予備半田を行なっためち、該予備半田面を熱板上
に搭載した半田の付着し難い部材からなる基板上に載置
して、前記予備半田面の半田量を規制するようにしたこ
とを特徴とする予備半田後の半田面の半田１規制力法。- A method for regulating solder on a solder surface after preliminary soldering in the process of soldering mounted components on a circuit board, wherein preliminary soldering is performed on the mounted components and the preliminary soldered surface is mounted on a hot plate. 1. A solder 1 regulating force method for a solder surface after preliminary soldering, characterized in that the amount of solder on the preliminary solder surface is regulated by placing the substrate on a substrate made of a material to which solder does not easily adhere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21026982A JPS5999792A (en) | 1982-11-29 | 1982-11-29 | Method of specifying solder amount on soldering surface after preliminary soldering |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21026982A JPS5999792A (en) | 1982-11-29 | 1982-11-29 | Method of specifying solder amount on soldering surface after preliminary soldering |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5999792A true JPS5999792A (en) | 1984-06-08 |
Family
ID=16586591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21026982A Pending JPS5999792A (en) | 1982-11-29 | 1982-11-29 | Method of specifying solder amount on soldering surface after preliminary soldering |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5999792A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62128595A (en) * | 1985-11-29 | 1987-06-10 | 富士通株式会社 | Soldering of chip carrier |
| US7296792B2 (en) | 2004-01-19 | 2007-11-20 | Marquip, Llc | Self-valving vacuum distribution for a belt-driven sheet conveyor |
-
1982
- 1982-11-29 JP JP21026982A patent/JPS5999792A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62128595A (en) * | 1985-11-29 | 1987-06-10 | 富士通株式会社 | Soldering of chip carrier |
| US7296792B2 (en) | 2004-01-19 | 2007-11-20 | Marquip, Llc | Self-valving vacuum distribution for a belt-driven sheet conveyor |
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