JPS61211897A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To control an output amplitude by using a MOSFET in which a conductance is changed by a control voltage as a collector loading means of a differential transistor for an electric current switch circuit. CONSTITUTION:As a collector loading means of a differential transistor T2, two parallel formations of MOSFET Q30, Q31 are used and a substantially constant voltage VI is supplied to a gate and the MOSFET Q30 is operated as a fixed resistance. To a gate of the MOSFET Q31, a control voltage VC is supplied, thereby the MOSFET Q31 operates as a fixed resistance during selecting a chip and is turned off during selecting no chip. Since an ECL circuit operates with a comparatively large operating current during selecting the chip, an output signal is changed at high speed. During selecting no chip, a comparatively small current flows, so that a low power consumption is obtained, in accordance with a change-over of the operating current, a loading resistance value is changed over and an output level thereof can be substantially fixed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, in which, for example, 12 peripheral circuits include ECL circuits, and a main circuit array is a static type R circuit composed of CMO:: circuits.
The present invention relates to a technology that is effective for use in AM (Random Access Memory).

[Background technology]

CM OS Nuctic RAM (Random Access Memory) and ECL (Emitter Coupled Logic) circuit number i! C, which is accessed directly
M OS-E CI, Compatible RAM, Digest of Technical Helpers (rssc n1GusT OF TECHNTCAI)
.

P A 11 E 17 Scarcity;) Magazine, February 1982 issue, II+) 248-249. Also,
In order to increase the speed of CMOS state-type RΔm・l, a bipolar type single transistor was used in JP-A-56.
It has been proposed by Nikkei Electronics Co., Ltd., page 198, published by Nikkei McGraw-Hill, May 21, 1984.

The applicant of this application uses CMOS static type RAM.
In order to increase the speed of processing, we have already developed a RAM that incorporates an ECL circuit made up of bipolar transistors in part of the address buffer and data input/output circuit. RA that combines such ECL circuit and CMO3 circuit
In M, since the operating current of the ECL circuit side is regulated by a constant current source, the current consumption and operating speed remain constant regardless of fluctuations in the power supply voltage. On the other hand, CMO
On the third circuit side, as the power supply voltage increases, the operating current increases and the operating speed also increases. Therefore, the current consumption, which is the performance of the entire RAM, is determined by the relatively large current consumption due to the upper limit power supply voltage, while the operating speed is determined by the relatively slow operation speed due to the lower limit power supply voltage. Live.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device including a current switch circuit that can be applied to a wide range of applications.

Another object of the present invention is to provide a semiconductor memory device whose operating speed and power consumption are less dependent on power supply.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by using a MOSFET whose conductance is carbonized by a control voltage as a collector load means of a differential transistor serving as a current switch circuit, the output amplitude thereof can be controlled.

[Example 1] FIG. 1 shows a static type RA to which this invention is applied.
A circuit diagram of one embodiment of M is shown.

Although not particularly limited, the RAM shown in the figure is formed on a single semiconductor substrate such as single crystal silicon using known integrated circuit technology. In addition, in the same figure, P channel M
The OS FET is distinguished from the N-channel type by adding a straight line between its source and drain.

One specific circuit of the memory cell MC is shown as a representative, and is an N-channel storage MO3FETQ.
The gates and drains of I, Q2 are cross-wired together. Although not particularly limited, between the drains of the MO3FETs QI and Q2 and the power supply voltage Vcc, there are high resistances R1 and R formed of a polysilicon layer for information retention.
, 2 are provided. An N-channel transmission gate MO3FETQ3. is connected between the common connection point of the MO3FETQI, Q2 and the complementary data lines Do, DO. Q4 is provided. Other memory cells MC also have similar circuit configurations. These memory cells are arranged in a matrix. Transfer gate 1-νI (J S FET Q 3 ) of memory cells arranged in the same row.

Gates such as C4 are commonly connected to corresponding word I/lines WO, Wn, etc. shown as examples, and input/output terminals of memory cells arranged in the same column are shown as examples. A corresponding pair of complementary data (or human data) i
! Connected to DO, T)O, Lll, DI, etc.

In the memory cell MC described above, in order to suppress it to a low extinction force, its resistance r<1 is MOS FE i''
MOS FlΣ′ when Ql is turned off and C
■゛The resistance value of Q2 is set to the same level that allows the voltage to be maintained above the threshold (k voltage).Similarly, the resistance R2 is also set to a high resistance value.6 In other words, Resistance R
First, it is necessary to supply enough current to prevent the information charge stored in the gate capacitance (not shown) of the MOS FET Q 2 from being dissipated due to the drain leakage current of the MOS FIC'r Q 1. He is made to have the ability to bind. Incidentally, instead of "-other anti-I<i, R2, Pjanor MOS)'E"f' may be used.

Although not particularly limited, there is an N-channel load MO3 between the representative pair of complementary data lines Do, DO in the memory array M-ARY and the power supply voltage Vcc.
FETQ5. G6 is provided. Complementary data line DI is shown as another representative.

Similar MO3FET Q7 to 51. A QB is provided.

In the figure, the word line WO is connected to the X address decoder
The selection is made by the output signal formed by the NOR gate circuit G1 forming the DCR. This also applies to other word lines Wn.

The X address decoder XDCR has mutually similar NOR gate times FII! rG1. Consists of G2 etc. The input terminals of these NOR gate circuits Gl, 02, etc. are provided with an X address buffer XADB that receives an external address signal AO=Ai (address signal output from an appropriate circuit device not shown) consisting of multiple bits, as described later.
The internal complementary address signals formed by the above are applied in a predetermined combination. In addition, the above-mentioned X address decoder XDCR
Each unit circuit is one NOR gate circuit Gl.

02, etc., but in order to reduce the number of gates in the entire address decoder and to reduce parasitic input capacitance, it is desirable to configure the address decoder by dividing it into multiple stages, such as by arranging a pre-decoder. .

A pair of complementary data lines DO, lower 0 and DI, DI in the memory array are connected to transmission gates MO3FETQ9. QlO and Qll, G12
It is connected to the common complementary data lines CD, CD through a column switch circuit composed of the following.

MO3FETQ9 that constitutes the above column switch circuit.
A selection signal formed by a Y address decoder YDCR is supplied to the gates of QIO, Qll, and G12, respectively. This Y address decoder YDCR is constituted by mutually similar NOR gate circuits G3, 04, etc., as described above.

These NOR gate circuits G3. G4 etc. have multiple pitch I.
Y receives an external address signal AO-Aj (address signal output from an appropriate circuit device not shown) consisting of
Internal complementary address signals formed by address buffers Y-AI)B are applied in a predetermined combination.

The common complementary data lines CD and CD are connected to the readout circuit R.
The input terminal of A and the output terminal of the write circuit [lWA are connected. The readout circuit RA has a common complementary data line CD
, a sense amplifier that amplifies the CD read signal, and E
CL output circuit and sends out an ECL level read signal to the output terminal Dout. The write circuit WA amplifies the ECI level write data signal inputted from the input terminal Din, forms a CMOS level write signal, and sends it to the common complementary data lines CD, Cr).

The timing control circuit TC receives control signals from the external terminals WE and C8, and forms operation control signals for the read circuit @RA and the write circuit WA.

The above-mentioned X address decoder XDCR is one of the circuits (
unit circuit) is shown as a representative.

That is, the address signal from the external terminal AO is transmitted through the bipolar transistor Tl and the level shift diode D1.
and MO3FE as a current source that forms its operating current.
Via an emitter follower circuit consisting of TQI 3, it is fed to the next ECLl path. The ECL circuit includes differential transistors T2. T3 and MO3FETQI as a current source provided at its common emitter and forming its operating current.
4, and the differential transistor T2. As the collector load means of T3 - this MO3FETQ27. Q28. In this embodiment, MO as the current source
3FETQI 3. Ql 4 generates a variable current when its gate is supplied with a control voltage VB generated by a voltage generation circuit as described later. In order to prevent the output level from fluctuating due to such variable current, the MO3FETQ27. A control voltage VB' as described later is supplied to the gate of Q2B. At the base of one of the differential transistors T2,
The output signal of the emitter follower circuit is supplied, and the base of the other differential transistor T3 is supplied with a reference voltage vbb as a logic threshold voltage. Each of the above circuit elements constitutes an input circuit IB.

The ECL level complementary signal, which is sent from the collector of the differential amplification transistor T2゜T3 of the input circuit IB and consists of an address signal in phase with the address signal supplied from the external terminal AO and an address signal in opposite phase, is as follows. It is converted to a CMOS level by a level conversion circuit LVC. That is, the above complementary signal is transmitted to the P channel MO3FETQ1.
5. Supplied to the gate of Qi6. These MO3FE
TQ15. The drain of Qi6 has an N-channel jL in a current mirror configuration, MO3FBTQI 7. Qi8 is provided. In this MO3 amplifier circuit, complementary signals having opposite phases to each other are supplied to the gates of the P-channel MO5FETs QI5 and Qi6.
5. The drain current of Qi 6 flows differentially. For example, when the current in MO3FET QI 5 is made relatively large, the current in MO5FET QI 6 is made relatively small. In this case, a large current is supplied to the MO3FET QI 7 in the current mirror form through the MO3FET Q15, so that the current of the MO3FET QI 8 is also increased accordingly. Therefore, complementary P-channel MO
Since the 3FET QI 6 and the N-channel MO5FET Q1B are operated, a low level output signal similar to the ground potential of the 5 circuits is obtained from the output N1. Furthermore, when the current of MO3FETQ16 is made relatively large by a reverse input signal, the current of MO5FETQ1.5 is made relatively small, and as a result, the current mirror type MO
5FETQ1? , Qi8 becomes small, and a high-level output signal such as the power supply voltage Vcc is obtained from the output N1.

In order to form an address signal (N2) having a phase opposite to the internal address signal formed by the above level conversion circuit, a level conversion circuit constituted by the above-described MO5FETs QI 9 to Q22 is provided. MO3FETQ19. which is the input of this level conversion circuit. At the gate of Q20,
A complementary signal having an ECL level opposite to that in the above case is supplied.

In this embodiment, the following output circuit OB is provided in order to drive at high speed a load capacitor having a relatively large capacitance value consisting of the input capacitors of a large number of gate circuits constituting the address decoder. That is, one output signal N1 of the complementary signals formed by the level conversion circuit LVC is as follows.
Bipolar type N P N output I transistor'■゛lL
supplied to the base of This output transistor T4 is
Charges a capacitive load. Above output transistor 1-4
an output transistor T similar to the above, connected in cascade with
5 discharges the capacitive load. In order to operate this output transistor T5f complementary to the output transistor T4, a MO5FETQ23 is provided between the base and collector of the transistor T5. This MO3
The level conversion circuit LV is connected to the gate of FF and TQ23.
The other output signal N2 of the complementary signals formed by C is provided. The output signal aO is connected between the base of the output transistor T5 and the negative power supply voltage -Vee.
A MO3FET Q24 is provided to receive the signal.

The output circuit that forms the output signal aO having the opposite phase to the output signal aO is also connected to the transistors T6, T7 and MO of the Q(lu).
3FI KoTQ25. Consists of Q26. However, the base of the output transistor T6 that charges the capacitive load is supplied with the other level-converted output signal N2, and the MO3FET Q25 that is provided between the base and collector of the output transistor T7 that discharges the capacitive load is supplied with the other level-converted output signal N2. The one level-converted output signal N1 is supplied to the gate of .

The operation of this output circuit OB is as follows.

When one of the level-converted output signals N1 is at a high level (ground potential of the circuit), the output transistors 1 and 4 are turned on and the output signal aQ is set at a high level. At this time,
Since the other level conversion output signal N2 is at a low level (negative power supply voltage -Vee), the MO5FETQ23 is turned off, and the high level of the output (M aO) turns the MO3FETQ24 on.
Due to the ON state of ETQ24, a low level is supplied to the base of the output transistor T5. This turns the output transistor T5 off.

Therefore, the capacitive load is quickly charged, and the output signal a0 is quickly charged to a high level.

From the above state, one of the above level conversion output signals N 1
When the other level conversion output signal N2 changes to a low level and the other level conversion output signal N2 changes to a high level, the output 1 transistor T4 is turned off due to the low level of the one level conversion output N1. The other above, Bell conversion output signal N2
MO3FETQ23 is turned on by the level of the bar.Due to the on-state of MO3FBTQ23, the high level of the output signal aO is set to the output transistor T.
This output transistor T5 is turned on by being supplied to the base of T5. In other words, M.O.5
The output transistor T5 is turned on by the on state of FETQ23.
is connected by its base and collector.
It is formed into a diode and rapidly discharges the high level output signal aO. At this time, the MO3FETQ24 is turned on by the high level of the output signal aO, but its conductance is set smaller than that of the MO5FETQ23 so as not to inhibit the on-operation of the output transistor T5. be made into

The operation of the output circuit that forms the output signal aQ having the opposite phase to the output signal aO is different from that in the above case because the level-converted output signal is supplied with the opposite phase.
6. T7 is controlled on/off in reverse.

In addition, in order to prevent the output transistor T5 from being driven in the saturation region, the drain of MO3FETQ23 is connected to the collector of the transistor T5 instead of the circuit ground potential, and similarly prevents the transistor T7 from being driven in the saturation region. Therefore, the drain of MO3FETQ25 is connected not to the ground potential of the circuit but to the collector of transistor T7. This aims to speed up the switching operation.

In the embodiment No. 1, by using a polar type transistor with a large current driving capacity in the output section of the address buffer 1, the gate capacitance added to the gates of many MOSFETs constituting the address decoder as a load is reduced. It is possible to charge/discharge a parasitic capacitance that has a relatively large capacitance value, such as, at high speed. Such an output circuit OB is
Although not shown, the address decoder XD in FIG. 1 above
By also providing the output section of CR, YDCR, or the output section of the pre-decoder, it is possible to speed up the selection operation of the memory array.

In this embodiment, the following voltage ordering circuit is provided to control the operating current of the input circuit IB in the address buffer.

The voltage generating circuit generates a control voltage VB that changes in inverse proportion to a fluctuation in absolute value of the power supply voltage -Vee. That is, voltage dividing resistors R5 and R6 are provided between the ground potential point of the circuit and the power supply voltage -Vee. This voltage dividing resistor R
The divided voltage formed by 5 and R6 is supplied to the base of an NPN transistor 8. Resistors R7 and R8 are provided at the collector and emitter of this transistor T8, respectively, for setting the gain of the inverting amplifier circuit.

By appropriately setting the ratio of the resistors R7 and R8, a voltage 1R is formed at the collector of the transistor T8, which changes inversely with the fluctuation of the divided voltage (power supply voltage -Vee). Ru. This voltage signal is applied to the base of emitter follower transistor T9. The emitter of this 1-transistor T9 has a level shift diode D2. D3 and a load resistor RIO are provided in series. The collector of the L-transistor 'I'9 is connected to the ground potential point of the circuit via a resistor R9, although this is not particularly limited. Thereby, the voltage signal is level-shifted through the base, emitter and diodes D2 and D3 of the transistor 'I'9, and the MOS I? as the current source is level-shifted. Lami TQ13. It is sent out as a control voltage VB supplied to the gate of Ql4, etc. That is, this control voltage VB is applied to the input circuit IN in the unit of address buffer shown as a representative of -1, the input circuit of similar address buffers XADB and YADB, the write circuit WA, the read circuit RA, and the control circuit. M forming the operating current of the ECL circuit in the circuit 'rC
It is used as a control voltage for OS FET.

The voltage generating circuit generates a control voltage VB that changes in inverse proportion to a fluctuation in the absolute value of the power supply voltage -Vee, and controls the operating current of each ECT and circuit.

For example, when the level of the power supply voltage -Vee is increased in absolute value, the control voltage V T3 is decreased in absolute value inversely proportional to this.

MO3FETQI as a current source with such a control voltage VB supplied to its gate 3. The operating current of Ql 4 etc. is reduced.

By setting the operating current on the ECL circuit side using such a variable current source, for example, the power supply voltage -
By reducing the operating current of each logic circuit that handles ECL level signals in response to a variation in Vee, the current consumption is reduced and the operating speed thereof is relatively slowed down. However, on the CMO3 circuit side,
As its operating current increases, its operating speed increases.

Therefore, the operating speed and current consumption of the entire RAM are made such that fluctuations in the operating speed and current consumption of the ECL circuit and the CMO5 circuit compensate for each other.

As a result, the dependence of the operating speed and current consumption of the RAM as a whole on the mold opening voltage is reduced. however,
Due to the fluctuation of the operating current mentioned above, level conversion times g! 1LV
The signal level supplied to C also fluctuates. There,
Although not particularly limited, the control voltage VB' is applied by 1υ from the emitter of the emitter follower transistor 'I'9.
According to the above N-channel MO3FETQ27. Q2
This controls the conductance of B. That is,
When the operating current decreases as described above as the control voltage VB decreases, the control voltage VB'' also decreases, causing the conductance of MO3FETQ27 and Q28 to become smaller. Due to such a change in conductance, , the output amplitude can be kept constant even though the operating current is reduced.If necessary, a voltage generating circuit similar to the above may be provided to
Q27. The conductance, such as Q28, may have a desired change characteristic.

[Embodiment 2] FIG. 2 shows a circuit diagram of another embodiment of the input circuit IB. In this embodiment, the above MO3FBTQI 3. shown in FIG. Instead of Ql 4, NPN l-
Transistors TIO, Tll and their emitter resistance R11
, R12 are used. ”2 Transistor TIO,T
A constant voltage VO is supplied to the base of ll, so that the operating current is kept constant. On the other hand, MO3FETQ27. as a load means. When Q28 is an N-channel O5FET, its gate is connected to the power supply voltage -
Control voltage V that changes proportionally to absolute value fluctuations in Vee
B' to MO5FETQ27. Change the conductance of Q28.

As a result, for example, when the operation of the CMO3 circuit side becomes relatively slow due to a decrease in the power supply voltage -Vee in absolute value, the conductance is reduced by decreasing in absolute value of the control voltage VB''. Therefore, under a constant operating current as described above, the output amplitude is increased, so by driving the CMO5 circuit with a large signal amplitude, it is possible to compensate for the decrease in its operating speed. .

Conversely, if the operation of the 0M03 circuit becomes relatively faster as the power supply voltage -Vee increases in absolute value, its conductance is increased by increasing the control voltage VB'' in absolute value. As a result, under a constant operating current as described in item 2, the output amplitude is reduced, so by driving the 0M03 circuit with a small signal amplitude, its operating speed is slowed down. Such a change in the ECL level makes it possible to reduce the dependence of the operating speed of the RAM as a whole on the power supply.

For example, by setting the constant operating current to a relatively small operating current that is -equal to the operating current under the upper limit supply voltage in FIG. 1, the embodiment of FIG. Similarly, it is possible to reduce power consumption.

[Embodiment 3] FIG. 3 shows a circuit diagram of another embodiment of a current switch circuit such as the input circuit IB described above. In this embodiment, in order to reduce power consumption in the chip non-selected state,
To form the operating current of the ECl-circuit, two MO5
FETQ34. Q35 is used. One MO5FE
A constant voltage (2) is supplied to the gate of TQ34 to perform constant current operation. On the other hand, the gate of the other MO3FET Q35 is supplied with a control voltage VC° that performs constant current operation only in the chip selection state. That is, the control voltage vc' is set to a constant voltage when the chip is selected, thereby operating the MO3FE'l'Q35 at a constant current, and is set to a low level (-Vee) when the chip is not selected. This turns 6MO3FE'rQ35 off.

On the other hand, two parallel MO3FETs Q30°Q31 are used as collector load means for the differential transistor T2. Among these, one of the MOS FETQ30 is
By supplying a constant voltage (1) similar to that described above to its gate, it is operated as a fixed resistor. By supplying the control voltage VC to the gate of the other MO3FET Q31, the MO3FET Q31 operates as a fixed resistor when the chip is selected, and is turned off when the chip is not selected.

As a result, the ECL circuit operates with a relatively large operating current when in the chip selection state, and therefore changes the output signal at high speed. On the other hand, when the chip 7 is not selected, only a relatively small current flows, so that power consumption can be reduced.

Since the load resistance value is also switched in accordance with the switching of the operating current, the output level can be kept constant.

〔effect〕

(11E By using MO8FET whose conductance can be changed by the control voltage as the load means of the CL circuit, it is possible to keep the output amplitude constant or change the output amplitude when the operating current is changed. can get.

(2) By changing the operating current of the ECL circuit in inverse proportion to fluctuations in the power supply voltage using +11 above, the operating speed and current consumption of the ECL circuit and 0M03 circuit can be prevented from canceling each other out. In order to reduce the operating speed of the entire RAM and the power supply voltage dependence of current consumption,
The output amplitude of the ECL circuit can be made constant. This provides the effect that adjustment between the ECL side and the CMOS side can be easily performed since there is no need to take into account fluctuations in signal amplitude on the ECL side.

(3) According to (1) above, the load MO5 on the ECL circuit side
A simple configuration in which a control voltage according to the power supply voltage is supplied to the gate of the FET has the effect of reducing the operating speed of the RAM as a whole and the dependence of current consumption on the power supply.

(4) With the above fil, ECL in chip non-selected state
This has the effect of reducing the power consumption of the circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, a level conversion circuit that converts an ECL level signal to a CMOS level is
Numerous embodiments can be adopted, such as those using multiple stages of CMOS inverter circuits. Moreover, the output circuit may be configured by a CMOS inverter circuit. In general, any circuit may be used to form a control voltage that changes inversely and proportionally to fluctuations in the power supply voltage.

[Application field]

The present invention can be widely used in semiconductor integrated circuit devices including current switch circuits such as ECL circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of a static RAM according to the present invention, FIG. 2 is a circuit diagram showing another embodiment of its input circuit, and FIG. 3 is a circuit diagram showing one embodiment of a current switch circuit. FIG. 2 is a circuit diagram showing an example. XADB...X address buffer, YADB...Y address buffer, XDCR...X address decoder, YD
CR...Y address decoder, MC...memory cell, W
A: Write circuit, RA: Read circuit, TC: Timing control circuit, IB: Input circuit, LVC: Level conversion circuit, OB: Output circuit Figure 2 Figure 3 VC /C

Claims (1)

Claims: 1. A semiconductor integrated circuit device comprising a current switch circuit comprising a differential transistor and a load means configured by a MOSFET provided at the collector of the differential transistor and receiving a predetermined control voltage. 2. The semiconductor integrated circuit device has an input circuit that receives an external signal at ECL level, a level conversion circuit that receives the output signal of this input circuit and converts it to CMOS level, and a level conversion circuit that receives the output signal of this level conversion circuit and converts it to CMOS level. an address decoder circuit that forms a selection signal, a CMOS-configured memory array selected by this address decoder circuit, and a read signal from this memory array;
A RAM that includes an output circuit that sends an ECL level read signal to an external terminal, and a current source control circuit that controls the operating current of the logic circuit that handles the ECL level signal in inverse proportion to fluctuations in the power supply voltage. The current switch circuit constitutes a logic circuit that handles the ECL level signal, and the predetermined control voltage supplied to the gate of the MOSFET serving as the load means changes the output signal level due to changes in its operating current. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a variable voltage that compensates for. 3. The semiconductor integrated circuit device has an input circuit that receives an external signal at ECL level, a level conversion circuit that receives the output signal of this input circuit and converts it to CMOS level, and a level conversion circuit that receives the output signal of this level conversion circuit and converts it to CMOS level. an address decoder circuit that forms a selection signal, a CMOS-configured memory array selected by this address decoder circuit, and a read signal from this memory array;
The RAM includes an output circuit that sends an ECL level read signal to an external terminal, and the current switch circuit includes:
A predetermined control voltage supplied to the gate of the MOSFET that constitutes the logic circuit that handles the ECL level signal and serves as its load means decreases the conductance of the MOSFET inversely proportionally as the absolute value of the power supply voltage increases. Claim 1 characterized in that the voltage is variable such that
The semiconductor integrated circuit device described in Section 1.