JPS61190790A - Semi-conductor memory device - Google Patents

Abstract

PURPOSE:To realize a rapid operation through a simple circuit configuration by performing charge and discharge functions of an output load capacity after supplying a complementary signal which is converted to a CMOS level to each output transistor directly and indirectly. CONSTITUTION:The complementary signal of a ECL level which is obtainable from an input circuit IB is converted to the CMOS level by a level conversion circuit LVC. When a conversion output N2 is situated at a H level, an output transistor T4 is set to ON the conversion output N1 is situated at a level L. Consequently a T5 is set to OFF through a transmission gate MOSFET Q23 and a capacitive load is rapidly charged. And when a signal N2 becomes 'L' and a signal N1 becomes 'H' while the T4 is set to OFF and the T5 is set to ON, its load is discharged at a high speed. Since an output circuit OB opera tion which forms output signals a0 and a0 is supplied by signals N1 and N2 in reverse phase T6 and T7 are ON/OFF controlled in the opposite way of T4 and T5.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
Peripheral circuit includes ECL circuit, memory array is 0M03
The present invention relates to a technique that is effective for use in static RAM (random access memory) configured by circuits.

[Background technology]

Monthly issue, pp24 to allow direct access to CMOS static RAM (Random Access Memory) using ECL (emitter coupled logic) circuits.
8-249. It is known by In addition, in order to increase the speed of CMOS static type RAM, one using bipolar type transistors was proposed in Japanese Patent Application Laid-open No. 56-58193, Nikkei McGraw-Hill Publishing, "Nikkei Electronics", May 21, 1984, page 198, etc. ing.

The applicant of this application uses CMOS static type RAM.
In order to increase the speed of processing, we have already developed a RAM that incorporates an ECL circuit made up of bipolar transistors in part of the address buffer and data input/output circuit. RA that combines such ECL circuit and 0M03 circuit
In M, a level conversion circuit is required to convert the ECL level to the CMOS level. Further, an address decoder configured with a large number of gate circuits has a relatively large input capacitance. Therefore, the output circuit of the address buffer is required to have a relatively large current driving capability for high-speed operation. For these reasons, the level conversion circuit and output circuit described above are relatively complicated.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that can realize high-speed operation with a simple circuit configuration.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, one of the complementary signals converted to a CMOS level is directly supplied to the base of the output transistor that charges the output load capacitance, and the other signal is supplied to the base of the output transistor that discharges the output load capacitance. teeth,
The signal is supplied via a transmission gate (MOSFET) which operates upon receiving the output signal of the output transistor.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Although not particularly limited, the RAM shown in the figure is formed on a semiconductor substrate such as single crystal silicon using known integrated circuit technology. In the figure, the P-channel MO3FET is It is distinguished from the N-channel type by adding a straight line between the drains.

One specific circuit of the memory cell MC is shown as a representative, and is an N-channel storage MO3FETQ.
The gates and drains of I, Q2 are cross-wired together. Although not particularly limited, between the drains of the MO3FETs QI and Q2 and the power supply voltage Vcc, there are high resistances R1 and R formed of a polysilicon layer for information retention.
2 is provided. An N-channel type transmission gate MO3FETQ3. Q4 is provided. Other memory cells MC also have similar circuit configurations. These memory cells are arranged in a matrix. The gates of the transmission gates MO3FETQ3゜Q4, etc. of the memory cells arranged in the same row are commonly connected to the corresponding word lines WO, Wn, etc. shown by way of example, and are connected to the inputs of the memory cells arranged in the same column. The output terminals are connected to a corresponding pair of complementary data (or bit) lines DO, DO and Di, DI, etc., respectively, which are exemplarily shown.

In the memory cell MC, in order to reduce power consumption, the resistor R1 is set to a level that allows the gate voltage of MOS FETQ2 to be maintained above the threshold voltage when MO3FETQ1 is turned off. It is made to have a high resistance value. Similarly, the resistor R2 is also made to have a high resistance value.

In other words, the resistor R1 has enough current supply ability to prevent the information charge stored in the gate capacitor N (not shown) of MO3FET Q2 from being discharged due to the drain leakage current of MO3FET QI. . Note that a P-channel MOS FET may be used instead of the resistors R1 and R2.

A pair of complementary data #IADO2DO and power supply voltage Vcc shown as a representative in the above memory array M-ARY
There is no particular restriction between N channel load M
O3FETQ5. Q6 is provided. Complementary data line DI is shown as another representative.

Similar MO3FETQ for DI? , G8 are provided.

In the figure, the word line WO is connected to the X address decoder
The selection is made by the output signal formed by the NOR gate circuit G1 forming the DCR. This also applies to other word lines Wn.

The X address decoders XDCR are mutually similar NOR gate circuits G1. Consists of G2 etc. The input terminals of these NOR gate circuits Gl, G2, etc. are supplied with external address signals AO to AO consisting of multiple bits as described later.
Internal complementary address signals formed by an X address buffer XADB receiving At (an address signal output from an appropriate circuit device not shown) are applied in a predetermined combination. Note that each unit circuit of the X address decoder XDCR is one NOR gate circuit Gl.

02, etc., but in order to reduce the number of gates in the entire address decoder and to reduce parasitic input capacitance, it is desirable to configure the address decoder by dividing it into multiple stages, such as by arranging a pre-decoder. .

A pair of complementary data lines Do, D in the memory array
O, Dl, and Dl are transmission gates MO3FETQ9.0 and D1 for data line selection, respectively. QlO and Qll, G12
It is connected to the common complementary data lines CD, CD through a column switch circuit composed of the following.

MO3FEi:TQ that constitutes the above column switch circuit
9. A selection signal formed by a Y address decoder YDCR is supplied to the gates of QIO, Qll, and G12, respectively. This Y address decoder YDCR is a mutually similar NOR gate circuit G3. G4
It is composed of etc.

These NOR gate circuits G3. In G4, etc., an internal complementary address signal formed by a Y address buffer Y-ADH that receives external address signals AO to Aj (address signals output from an appropriate circuit device not shown) consisting of multiple bits is output by a predetermined combination. applied.

The common complementary data line CD, τ100 is the readout circuit R
It is connected to the input terminal of A and the output terminal of write circuit WA. The readout circuit RA includes a common complementary data line CD,
A sense amplifier that amplifies the CD read signal and an ECL
It includes an output circuit and sends out an ECL level read signal to the output terminal Dout. The write circuit WA has an input terminal D
The write data signal at the ECL level inputted from the in is amplified to form a write signal at the CMOS level and sent to the common complementary data lines CD, CD.

The timing control circuit TC receives chip selection signals and write enable signals supplied from external terminals WE and Cτ, and forms operation control signals for the read circuit RA and write circuit WA.

The above-mentioned X address decoder XDCR is one of the circuits (
unit circuit) is shown as a representative.

That is, the address signal from the external terminal AO is transmitted through the bipolar transistor T1 and the level shift diode DI.
and MO3FE as a current source that forms its operating current.
It is supplied to the next ECL circuit via an emitter follower circuit consisting of TQI 3. The ECL circuit includes differential transistors T2. T3 and MO3FETQI as a current source provided at its common emitter and forming its operating current.
4, and the differential transistor T2. It is composed of load resistors R3 and R4 provided at the collector of T3.

MO3FETQI as the above current source 3. Ql 4 operates as a constant current source by supplying a constant voltage Vo to its gate. One of the differential transistors T
The base of the differential transistor T3 is supplied with the output signal of the emitter follower circuit, and the base of the other differential transistor T3 is supplied with a reference voltage vbb as a logic threshold voltage.
is supplied.

Each of the above circuit elements constitutes an input circuit IB.

The complementary signal at the ECL level, which is derived from the collector of the input circuit IBO differential amplification transistor T2゜T3 and consists of an address signal in phase with the address signal supplied from the external terminal AO and an address signal in opposite phase, is at the next level. It is converted to CMOS level by a conversion circuit LVC. That is, the above complementary signal is transmitted to the P channel MO3FETQ1.
5. Supplied to the gate of Q16. These MOSFEs
TQI5. The drain of Q16 is connected to an N-channel MO3FET Q17. in a current mirror configuration. Q18 is provided. In this MO3 amplifier circuit, complementary signals having opposite phases to each other are supplied to the gates of the P-channel MO3FETs Q15 and Q16. Q16
For example, if the drain current flows differentially in a MOSFE
If the current of TQI5 is relatively thick (if it is, the MOSFET
The current in QI6 is made relatively small. In this case, a large current is supplied to the current mirror type MOSFET QI 7 through the MO3FET QI 5, so that the current of the MOSFET QI B is also increased accordingly.

Therefore, complementary P-channel MOSFETQI
6 and the N-channel MO3FET Q1B are operated, so that a low level output signal like the ground potential of the Z circuit is obtained from the output Nl. Moreover, when the current of MOSFETQI6 is made relatively large by the opposite input signal, the current of MOSFETQI5 is made relatively small, and as a result, the current mirror type MO3FETQ1? ,
The operating current of Q18 becomes smaller, and the output N1 becomes less
A high level output signal like the power supply voltage Vcc can be obtained.

In order to form an address signal (N2) having a phase opposite to the internal address signal formed by the above level conversion circuit, a level conversion circuit constituted by MOSFETs QI9 to Q22 similar to those described above is provided. MOSFET QI9. which is the input of this level conversion circuit. At the gate of Q20,
A complementary signal having an ECL level opposite to that in the above case is supplied.

In this embodiment, the following output circuit OB is provided in order to drive at high speed a load capacitance having a relatively large capacitance value consisting of the input capacitances of a large number of gate circuits constituting the address decoder. That is, one output signal N2 of the complementary signals formed by the level conversion circuit LVC is as follows.
It is supplied to the base of bipolar NPN output transistor T4. This output transistor T4 charges the capacitive load. A similar output transistor T5, connected in cascade with the output transistor T4, discharges the capacitive load. In order to operate complementary to the transmission gate MO3F, the base of the transistor T5 is connected to the transmission gate MO3F.
The other output signal N1- of the complementary signals is supplied via ETQ23. This transmission gate MO3FETQ
23 is constituted by an N-channel MOS FET, and the output signal aO is supplied to the gate thereof.

The output circuit that forms the output signal 0 having the opposite phase to the output signal aO is also the transistor T6 similar to the above. It consists of T7 and transmission gate MO3FETQ24. However, at the base of the output transistor T6 that charges the capacitive load,
The base of the output transistor T7, to which the other level-converted output signal Nl is supplied, discharges the capacitive load.
The one level conversion output signal N2 is supplied through the transmission gate MO3FETQ24.

The operation of this output circuit OB is as follows.

When the one level-converted output signal N2 is at a high level (ground potential of the circuit), the output transistor T4 is turned on and the output signal aO is set at a high level. At this time, since the other level conversion output signal N1 is at a low level (negative power supply voltage -Vee), the base of the transistor T5 is brought to a low level through the MOSFET Q23 turned on by the high level of the output aO. This turns transistor T5 off. Due to such operations of transistors T4 and T5, the capacitive load is charged at high speed, and the output signal aO is charged to a high level at high speed.

From the above state, when the one level conversion output signal N2 changes to a low level and the other level conversion output signal N1 changes to a high level, the output transistor T4 is turned off by the low level of the one level conversion output N2. . The high level of the other level-converted output signal N1 is transmitted to the base of the output transistor T5 through the MO3FET Q23, which is turned on by the high level of the output signal aO.
5 is turned on. As a result, the high level output signal aQ is discharged at high speed. Note that MO3FETQ23 is turned off by this discharging operation. Therefore, along with the above-described discharging operation, the output transistor T5 is also turned off.

However, since the capacitive load is held at a low level, the output signal aO can remain at a low level.

The operation of the output circuit that forms the output signal TO having a phase opposite to that of the output signal aQ is different from that in the above case because the level-converted output signal is supplied with the phase opposite.
6. T7 is controlled on/off in reverse.

In this embodiment, by using a bipolar transistor with a large current driving capacity in the output section of the address buffer, a relatively large capacitance such as a gate capacitance is added to the gates of many MOSFETs that constitute the address decoder as a load. It is possible to charge/discharge the parasitic capacitance that has been set to a value at high speed. Such an output circuit OB is
Although not shown, the address decoder XD in FIG. 1 above
By also providing the output section of CR, YDCR, or the output section of the pre-decoder, it is possible to speed up the selection operation of the memory array.

〔effect〕

One of the complementary CMO3 signals subjected to +1 level conversion controls the transistor that charges the load capacitance, and the base of the transistor that discharges the load capacitance is connected to the other one of the complementary CMO3 signals through a transmission gate MOSFET. By supplying a signal, the operation timing of this transistor can be delayed. That is, the transistor that performs the charging operation is immediately turned on or off by being directly supplied with one CMO3 signal. On the other hand, the transistor that performs the discharging operation is turned off upon completion of the discharging operation because the other CMO3 signal is supplied to its base via the transmission gate MO3FET which operates in response to the output signal.

Further, when the device is turned on, it is turned on with a delay. This has the effect that it is possible to prevent the generation of a large through current as would be the case when directly cascade-connected output transistors are controlled by the complementary CMO5 signal.

(2) With (1) above, it is possible to speed up the charging and discharging of capacitive loads such as address decoders with relatively large capacitance values, resulting in the effect of speeding up the selection operation of word lines, etc. It will be done.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without advancing the gist of the invention. For example, a level conversion circuit that converts an ECL level signal to a CMOS level is
Numerous embodiments can be adopted, such as those using multiple stages of CMo5 inverter circuits. The constant current source that generates the operating current of the ECL circuit may be constituted by a bipolar transistor.

[Application field]

The present invention can be widely used in semiconductor memory devices configured by a combination of an ECL circuit and an 0M05 circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. XADB...X address buffer, YADB...Y address buffer, XDCR...X address decoder, YD
CR...Y address decoder, MC...memory cell, W
A: Write circuit, RA: Read circuit, TC: Timing control circuit, IB: Input circuit, L, v c...
Level conversion circuit, OB...output circuit

Claims (1)

[Claims] 1. An input circuit that receives an external signal at an ECL level, a pair of level conversion circuits that receive a complementary output signal of this input circuit and convert the level into a complementary CMOS signal, and an output signal of one of the pair of level conversion circuits. a bipolar output transistor T4 that charges the output load capacitance in response to the output voltage, a bipolar output transistor T5 that is cascade-connected to the output transistor T4 and discharges the output load capacitance, and a connection between the output transistors T4 and T5. an output circuit consisting of a transmission gate MOSFET which receives the output signal obtained from the point and transmits the output signal of the other of the pair of level conversion circuits to the base of the output transistor T5; and a level conversion output through this output circuit. CM received
An address decoder circuit that forms an OS level selection signal and a CM selected by this address decoder circuit.
A semiconductor memory device comprising: a memory array having an OS configuration; and an output circuit that receives a read signal from the memory array and sends an ECL level read signal to an external terminal.