JPS6120785Y2 - - Google Patents
Info
- Publication number
- JPS6120785Y2 JPS6120785Y2 JP1976064474U JP6447476U JPS6120785Y2 JP S6120785 Y2 JPS6120785 Y2 JP S6120785Y2 JP 1976064474 U JP1976064474 U JP 1976064474U JP 6447476 U JP6447476 U JP 6447476U JP S6120785 Y2 JPS6120785 Y2 JP S6120785Y2
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate
- electrode
- source
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 3
- 239000002184 metal Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【考案の詳細な説明】
本考案は接合型電界効果トランジスタの改良に
関するものである。[Detailed Description of the Invention] The present invention relates to an improvement of a junction field effect transistor.
接合型電界効果トランジスタ（以下Ｊ−FET
と略称する）の高周波特性や低周波特性を改善す
るには、ゲートの直列抵抗値が重要な要素とな
る。すなわち、高周波用Ｊ−FETにおいては、
入力等価回路のゲート直列抵抗値と、ゲート・ソ
ース間容量値との時定数が高周波縛性に大きく影
響する。低周波用Ｊ−FETにおいては、入力端
子をシヨートするとゲース直列抵抗を介してシヨ
ートしたことになり、この直列抵抗により発生す
る雑音が無視できなくなる。したがつてゲート直
列抵抗値を減少させることが特性改善上必要とさ
れる。ところが一般のＪ−FETでは、ゲート直
列抵抗値を減少させるためにはゲート領域の巾を
大きくとらねばならず、ゲート領域の巾を大きく
するとチヤネル長が長くなることから相互コンダ
クタンスの低下等の不都合が生じてしまう。 Junction field effect transistor (J-FET)
The series resistance value of the gate is an important factor in improving the high-frequency characteristics and low-frequency characteristics of In other words, in high frequency J-FET,
The time constant between the gate series resistance value of the input equivalent circuit and the gate-source capacitance value greatly affects the high frequency locking property. In a low frequency J-FET, when the input terminal is shot, the shot is passed through a gated series resistor, and the noise generated by this series resistor cannot be ignored. Therefore, it is necessary to reduce the gate series resistance value in order to improve the characteristics. However, in general J-FETs, in order to reduce the gate series resistance value, the width of the gate region must be increased, and increasing the width of the gate region increases the channel length, resulting in disadvantages such as a decrease in mutual conductance. will occur.
これを回避するため、従来では第１図に示すよ
うな構造のＪ−FETが案出されている。すなわ
ち第１図では、Ｐ型半導体基体１の表面に臨む所
定位置にチヤネルとなるＮ型領域２が形成され、
このＮ型領域２内部には、N+型のソース領域３
およびドレイン領域４が形成されている。これら
領域３，４間にはP+型で狭巾かつ短かい長さの
ゲート領域５が形成され、所定位置５ａで前記基
体１と電気的に接続されている。このＰ型基体１
はＮ型領域２の下部全面で下部ゲートとなる。こ
のような構成のＪ−FETでは、ゲート領域５の
巾は狭いが長さが短かいためゲート抵抗値が小さ
くとれる。ところが上部ゲート（ゲート領域５）
と下部ゲート（Ｐ型基体１）とを電気的接続して
いるため、２個のFETをカスコード接続するカ
スコード型FET素子等のように上部と下部ゲー
トとを切り離して使用する場合には、上記構成は
使用できない。また一般に入出力容量も大きくな
る。 In order to avoid this, conventionally a J-FET having a structure as shown in FIG. 1 has been devised. That is, in FIG. 1, an N-type region 2 serving as a channel is formed at a predetermined position facing the surface of a P-type semiconductor substrate 1,
Inside this N type region 2, an N + type source region 3 is provided.
and a drain region 4 are formed. A narrow and short gate region 5 of P + type is formed between these regions 3 and 4, and is electrically connected to the base 1 at a predetermined position 5a. This P-type substrate 1
The entire lower part of the N-type region 2 becomes the lower gate. In the J-FET having such a configuration, the width of the gate region 5 is narrow but the length is short, so that the gate resistance value can be kept small. However, the upper gate (gate area 5)
and the lower gate (P-type substrate 1) are electrically connected, so when using the upper and lower gates separately, such as in a cascode type FET device that connects two FETs in cascode, the above Configuration not available. In addition, the input/output capacity generally increases.
本考案は上記実情に鑑みてなされたもので、ゲ
ート直列抵抗値が小さく、相互コンダクタンスは
大きく、しかも上部ゲートと下部ゲートとを分離
して使用できるＪ−FETの提供を目的とする。 The present invention was developed in view of the above circumstances, and aims to provide a J-FET that has a small gate series resistance value, a large mutual conductance, and whose upper and lower gates can be used separately.
以下本考案に係る好ましい一実施例について、
第２図ないし第６図を参照しながら説明する。こ
れらの図において、第２図は実施例の平面図、第
３図ないし第６図はそれぞれ第２図−線ない
し−線の断面端面図である。 The following is a preferred embodiment of the present invention.
This will be explained with reference to FIGS. 2 to 6. In these drawings, FIG. 2 is a plan view of the embodiment, and FIGS. 3 to 6 are cross-sectional end views taken along line - - - in FIG. 2, respectively.
一導電型、たとえばＰ型の半導体基体２１内部
には、この基体２１の上部表面に臨んでＮ型領域
２２が形成されている。このＮ型領域２２内部に
はN+型のソース領域２３、ドレイン領域２４お
よびP+型のゲート領域２５が形成されている。
このゲート領域２５は、比較的広い面積の部分２
５１と、狭巾の線状部分２５２，２５３，２５４
とから成り、線状部分２５２は各広面積部分２５
１を連絡し、線状部分２５３は蛇行パターンを構
成し、線状部分２５４は蛇行した線状部分２５３
の一方の曲折部を短絡している（以下これらを連
絡部２５２、蛇行部２５３、短絡部２５４と称
す）。ソース領域２３およびドレイン領域２４
は、ゲート領域２５を挟むように配置されるが、
蛇行部２５３と短絡部２５４とで囲まれる部分
は、外部のソース領域２３から孤立し、島状ソー
ス領域２３１となる。 An N-type region 22 is formed inside a semiconductor substrate 21 of one conductivity type, for example, a P-type, facing the upper surface of the substrate 21 . Inside this N type region 22, an N + type source region 23, a drain region 24, and a P + type gate region 25 are formed.
This gate region 25 has a relatively large area 2
51 and narrow linear portions 252, 253, 254
The linear portion 252 consists of each wide area portion 25.
1, the linear portion 253 constitutes a meandering pattern, and the linear portion 254 connects the meandering linear portion 253.
(hereinafter, these are referred to as the connecting portion 252, meandering portion 253, and short-circuiting portion 254). Source region 23 and drain region 24
are arranged so as to sandwich the gate region 25,
A portion surrounded by the meandering portion 253 and the short circuit portion 254 is isolated from the external source region 23 and becomes an island-like source region 231.
これらソース領域２３、ドレイン領域２４、お
よびゲート領域２５は、基体２１の上部表面に被
着されたSio2などの絶縁膜２６の窓部を介して、
拡散法などにより形成される。この拡散時には、
各領域２３，２４，２５表面にSio2などの絶縁酸
化膜が形成されるため、Al等の金属電極を接続
する際には再度パターンニングをして窓開けをす
る必要がある。このときソース、ドレイン領域２
３，２４上には、これらの形状に応じて窓開けを
するが、ゲート領域２５に関しては、狭巾の線状
部分２５２、２５３、２５４上には窓開けを行な
わず、広い面積の部分２５１上にのみ窓開けを行
なつている。Al等の金属電極２７，２８，２９
はこれらの窓開け部を介してそれぞれ各領域２
３，２４，２５に電気的に接続される。ここでソ
ース用金属電極２７はソース領域２３上に窓開け
部を介して被着形成されるわけであるが、さらに
ゲート領域短絡部２５４に対応する絶縁膜２６上
にはソース用金属電極２７の接続部２７１が形成
されており、孤立した島状ソース領域２３１と外
部のソース領域２３とを電気的に接続している。 These source region 23, drain region 24, and gate region 25 are connected to each other through windows of an insulating film 26 such as Sio 2 deposited on the upper surface of the base 21.
It is formed by a diffusion method or the like. During this spread,
Since an insulating oxide film such as Sio 2 is formed on the surface of each region 23, 24, 25, it is necessary to perform patterning again to open a window when connecting a metal electrode such as Al. At this time, source and drain regions 2
Windows 3 and 24 are opened according to their shapes, but regarding the gate region 25, windows are not opened over the narrow linear parts 252, 253, and 254, and the wide area part 251 is opened. Windows are opened only at the top. Metal electrodes 27, 28, 29 such as Al
are connected to each area 2 through these window openings.
3, 24, and 25. Here, the source metal electrode 27 is deposited on the source region 23 through the window opening, and the source metal electrode 27 is also formed on the insulating film 26 corresponding to the gate region short-circuit portion 254. A connecting portion 271 is formed to electrically connect the isolated island-shaped source region 231 and the external source region 23 .
以上の説明から明らかなように、ゲート領域２
５の蛇行部２５３の一部を短絡部２５４で短絡し
ているため、ゲーソ直列抵抗値が低くとれ、高周
波特性の改善および低周波雑音の低減が図れる。
しかも蛇行部２５３と短絡部２５４とで囲まれる
孤立島状ソース領域２３１は、短絡部２５４上の
絶縁膜２６上に形成された接続部２７１により外
部のソース領域２３と電気的接続されるため、全
ソース領域が有効に働く。またＪ−FETのチヤ
ネル制御はゲート領域２５の狭巾線状の連絡部２
５２、蛇行部２５３により行なわれるため、高効
率かつ高相互コンダクタンスの素子が容易に得ら
れる。また、上部ゲート端子G1と下部ゲート端
子G2とが電気的に分離できるため、カスコード
接続素子として最適であることに注目すべきであ
る。 As is clear from the above explanation, gate region 2
Since a part of the meandering portion 253 of No. 5 is short-circuited by the short-circuiting portion 254, the gausser series resistance value can be kept low, and high frequency characteristics can be improved and low frequency noise can be reduced.
Moreover, the isolated island-like source region 231 surrounded by the meandering portion 253 and the short circuit portion 254 is electrically connected to the external source region 23 by the connection portion 271 formed on the insulating film 26 on the short circuit portion 254. All source areas work effectively. In addition, the channel control of the J-FET is performed using the narrow linear communication portion 2 of the gate region 25.
52 and the meandering portion 253, a device with high efficiency and high mutual conductance can be easily obtained. Furthermore, it should be noted that since the upper gate terminal G1 and the lower gate terminal G2 can be electrically separated, it is optimal as a cascode connection element.
さらに本実施例の固有の効果としては、ゲート
領域２５の広い面積の２５１上にのみ窓開けを行
ない、狭巾線状部分２５２，２５３，２５４上の
困難な窓開けを不要としているため、窓開け作業
が容易に行なえ、しかも金属電極２９との電気的
接続が確実に行なえる。また連絡部２５２に沿つ
て金属電極２９を被着形成し、各広い面積の部分
２５１を高導電率の金属電極２９により電気的接
続しているため、ゲート直列抵抗値をさらに低下
できる。 Furthermore, as a unique effect of this embodiment, the window is opened only on the wide area 251 of the gate region 25, and the difficult window opening on the narrow linear portions 252, 253, 254 is not required. The opening operation can be easily performed, and the electrical connection with the metal electrode 29 can be made reliably. Further, since the metal electrode 29 is formed along the connecting portion 252 and each large area portion 251 is electrically connected by the high conductivity metal electrode 29, the gate series resistance value can be further reduced.
第１図は従来例を示す平面図、第２図ないし第
６図は本考案に係る一実施例を示し、第２図は平
面図、第３図ないし第６図はそれぞれ第２図の
−線ないし−線に沿う断面図である。
１，２１……Ｐ型半導体基体、２，２２……Ｎ
型領域、３，２３……ソース領域、４，２４……
ドレイン領域、５，２５……ゲート領域。
Fig. 1 is a plan view showing a conventional example, Figs. 2 to 6 show an embodiment of the present invention, Fig. 2 is a plan view, and Figs. 3 to 6 are respectively - FIG. 3 is a cross-sectional view taken along the line. 1, 21...P-type semiconductor substrate, 2, 22...N
Type area, 3, 23... Source area, 4, 24...
Drain region, 5, 25...gate region.
Claims (1)
該基体２１の一主面に臨む反対導電型の領域２２
と、この領域２２内に形成された反対導電型のソ
ース領域２３およびドレイン領域２４と、前記領
域２２内に前記半導体基体２１の一主面に達しか
つ前記ソース領域２３およびドレイン領域２４に
挟まれるように形成された一導電型のゲート領域
２５と、前記基体２１の一主面の全面に形成され
た絶縁膜２６と、この絶縁膜２６上において前記
ソース領域２３、ドレイン領域２４およびゲート
領域２５に対応して形成されこれら各領域２３，
２４，２５に前記絶縁膜２６に設けられた窓部を
通して接触するソース電極２７、ドレイン電極２
８およびゲート電極２９とより成る接合型電界効
果トランジスタにおいて、前記ゲート領域２５
に、複数の広巾部２５１とこれらに連続しかつ一
部が蛇行パターン２５３を形成している狭巾線状
部２５２、２５３とを設けるとともにこの蛇行パ
ターン２５３の一方の曲折部を短絡してこの蛇行
パターン２５３に囲まれるソース領域２３または
ドレイン領域２４を島状に孤立せしめる短絡部２
５４を設け、さらにこのゲート領域２５のゲート
電極２９との接触は前記複数の広巾部２５１にお
いて絶縁膜２６に設けた窓部を通して行なうよう
にし、前記ソース領域２３またはドレイン領域２
４の島状孤立部を、外部のソース領域２３または
ドレイン領域２４の上にあつてこれに接触してい
るソース電極２７またはドレイン電極２８より前
記短絡部２５４上の絶縁膜２６の上を通つてこの
島状孤立部の上にまで伸びてきた電極部分に、絶
縁膜２６に設けた窓部を通して接触させたことを
特徴とする接合型電界効果トランジスタ。 A region 22 of an opposite conductivity type formed in a semiconductor substrate 21 of one conductivity type and facing one main surface of the substrate 21
A source region 23 and a drain region 24 of opposite conductivity types are formed in this region 22 and reach one main surface of the semiconductor substrate 21 in the region 22 and are sandwiched between the source region 23 and the drain region 24. a gate region 25 of one conductivity type formed as shown in FIG. These regions 23,
A source electrode 27 and a drain electrode 2 are in contact with 24 and 25 through a window provided in the insulating film 26.
8 and a gate electrode 29, the gate region 25
, a plurality of wide width parts 251 and narrow width linear parts 252 and 253 which are continuous with these and partially form a meandering pattern 253 are provided, and one bent part of the meandering pattern 253 is short-circuited. Short-circuit portion 2 that isolates source region 23 or drain region 24 surrounded by meandering pattern 253 into an island shape
54 is provided, and the gate region 25 is brought into contact with the gate electrode 29 through a window provided in the insulating film 26 in the plurality of wide width portions 251, and the source region 23 or the drain region 2
4 through the insulating film 26 on the short circuit part 254 from the source electrode 27 or drain electrode 28 which is on and in contact with the external source region 23 or drain region 24. A junction field effect transistor characterized in that the electrode portion extending above the island-like isolated portion is brought into contact through a window portion provided in the insulating film 26.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976064474U JPS6120785Y2 (en) | 1976-05-20 | 1976-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976064474U JPS6120785Y2 (en) | 1976-05-20 | 1976-05-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52155473U JPS52155473U (en) | 1977-11-25 |
| JPS6120785Y2 true JPS6120785Y2 (en) | 1986-06-21 |
Family
ID=28528639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1976064474U Expired JPS6120785Y2 (en) | 1976-05-20 | 1976-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6120785Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4984583A (en) * | 1972-12-19 | 1974-08-14 |
-
1976
- 1976-05-20 JP JP1976064474U patent/JPS6120785Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4984583A (en) * | 1972-12-19 | 1974-08-14 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52155473U (en) | 1977-11-25 |
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